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authorMichael Abed <michaelabed@gmail.com>2012-02-17 12:10:31 -0500
committerMichael Abed <michaelabed@gmail.com>2012-02-17 12:10:31 -0500
commit59d89428d6160fb672c2b6a41339505cc69344d0 (patch)
treea774e809a31fc7eae7b0fd0777714c86ffedc9d6 /planAhead_run_2/lab2.data/constrs_1/designprops.xml
parent0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a (diff)
downloadec311-lab2-master.tar.gz
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diff --git a/planAhead_run_2/lab2.data/constrs_1/designprops.xml b/planAhead_run_2/lab2.data/constrs_1/designprops.xml
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+<?xml version="1.0"?>
+<Compat Version="1" Minor="4">
+ <CompatParts>
+ </CompatParts>
+ <ConfigModes>
+ <Mode Id="JTAG"/>
+ </ConfigModes>
+ <PortProps>
+ <Port Name="A[3]" OffChipTerm="NONE"/>
+ <Port Name="A[2]" OffChipTerm="NONE"/>
+ <Port Name="A[1]" OffChipTerm="NONE"/>
+ <Port Name="A[0]" OffChipTerm="NONE"/>
+ <Port Name="S[1]" OffChipTerm="NONE"/>
+ <Port Name="S[0]" OffChipTerm="NONE"/>
+ <Port Name="AN0" OffChipTerm="FP_VTT_50"/>
+ <Port Name="AN1" OffChipTerm="FP_VTT_50"/>
+ <Port Name="AN2" OffChipTerm="FP_VTT_50"/>
+ <Port Name="AN3" OffChipTerm="FP_VTT_50"/>
+ <Port Name="ao" OffChipTerm="FP_VTT_50"/>
+ <Port Name="bo" OffChipTerm="FP_VTT_50"/>
+ <Port Name="co" OffChipTerm="FP_VTT_50"/>
+ <Port Name="do" OffChipTerm="FP_VTT_50"/>
+ <Port Name="eo" OffChipTerm="FP_VTT_50"/>
+ <Port Name="fo" OffChipTerm="FP_VTT_50"/>
+ <Port Name="go" OffChipTerm="FP_VTT_50"/>
+ <Port Name="sign" OffChipTerm="FP_VTT_50"/>
+ </PortProps>
+</Compat>
+