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authorMichael Abed <michaelabed@gmail.com>2012-02-17 12:10:31 -0500
committerMichael Abed <michaelabed@gmail.com>2012-02-17 12:10:31 -0500
commit59d89428d6160fb672c2b6a41339505cc69344d0 (patch)
treea774e809a31fc7eae7b0fd0777714c86ffedc9d6 /planAhead_run_2/lab2.data/sources_1
parent0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a (diff)
downloadec311-lab2-master.tar.gz
ec311-lab2-master.tar.bz2
ec311-lab2-master.zip
finish itHEADmaster
Diffstat (limited to 'planAhead_run_2/lab2.data/sources_1')
-rwxr-xr-x[-rw-r--r--]planAhead_run_2/lab2.data/sources_1/fileset.xml112
-rwxr-xr-xplanAhead_run_2/lab2.data/sources_1/ports.xml28
2 files changed, 89 insertions, 51 deletions
diff --git a/planAhead_run_2/lab2.data/sources_1/fileset.xml b/planAhead_run_2/lab2.data/sources_1/fileset.xml
index 3358a4c..81193a8 100644..100755
--- a/planAhead_run_2/lab2.data/sources_1/fileset.xml
+++ b/planAhead_run_2/lab2.data/sources_1/fileset.xml
@@ -1,51 +1,61 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DARoots Version="1"
- Minor="19">
- <FileSet Name="sources_1"
- Type="DesignSrcs"
- RelSrcDir="$PSRCDIR/sources_1">
- <Filter Type="Srcs"/>
- <File Path="$PPRDIR/../sev_seg_disp.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../ALU.v">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../ALUSHOW.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <Config>
- <Option Name="DesignMode"
- Val="RTL"/>
- <Option Name="TopModule"
- Val="ALUSHOW"/>
- <Option Name="TopLib"
- Val="work"/>
- <Option Name="TopRTLFile"
- Val="$PPRDIR/../ALUSHOW.vf"/>
- <Option Name="TopAutoSet"
- Val="TRUE"/>
- </Config>
- </FileSet>
-</DARoots>
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1"
+ Minor="19">
+ <FileSet Name="sources_1"
+ Type="DesignSrcs"
+ RelSrcDir="$PSRCDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../sev_seg_disp.vf">
+ <FileInfo>
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../ALU.v">
+ <FileInfo>
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../ALUSHOW.vf">
+ <FileInfo>
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <File Path="$PDATADIR/sources_1/ports.xml">
+ <FileInfo SFType="PortsDb">
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode"
+ Val="RTL"/>
+ <Option Name="TopModule"
+ Val="ALUSHOW"/>
+ <Option Name="TopLib"
+ Val="work"/>
+ <Option Name="TopRTLFile"
+ Val="$PPRDIR/../ALUSHOW.vf"/>
+ <Option Name="TopAutoSet"
+ Val="TRUE"/>
+ </Config>
+ </FileSet>
+</DARoots>
diff --git a/planAhead_run_2/lab2.data/sources_1/ports.xml b/planAhead_run_2/lab2.data/sources_1/ports.xml
new file mode 100755
index 0000000..1eae741
--- /dev/null
+++ b/planAhead_run_2/lab2.data/sources_1/ports.xml
@@ -0,0 +1,28 @@
+<?xml version="1.0"?>
+<Interface Version="1" Minor="1">
+ <Ifc Id="ROOT" Top="1">
+ <Bus Id="A">
+ <Port Id="3" Dir="IN"/>
+ <Port Id="2" Dir="IN"/>
+ <Port Id="1" Dir="IN"/>
+ <Port Id="0" Dir="IN"/>
+ </Bus>
+ <Bus Id="S">
+ <Port Id="1" Dir="IN"/>
+ <Port Id="0" Dir="IN"/>
+ </Bus>
+ <Port Id="AN0" Dir="OUT"/>
+ <Port Id="AN1" Dir="OUT"/>
+ <Port Id="AN2" Dir="OUT"/>
+ <Port Id="AN3" Dir="OUT"/>
+ <Port Id="ao" Dir="OUT"/>
+ <Port Id="bo" Dir="OUT"/>
+ <Port Id="co" Dir="OUT"/>
+ <Port Id="do" Dir="OUT"/>
+ <Port Id="eo" Dir="OUT"/>
+ <Port Id="fo" Dir="OUT"/>
+ <Port Id="go" Dir="OUT"/>
+ <Port Id="sign" Dir="OUT"/>
+ </Ifc>
+</Interface>
+