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Diffstat (limited to 'ALUSHOW.par')
| -rwxr-xr-x | ALUSHOW.par | 148 |
1 files changed, 148 insertions, 0 deletions
diff --git a/ALUSHOW.par b/ALUSHOW.par new file mode 100755 index 0000000..a06c8a1 --- /dev/null +++ b/ALUSHOW.par @@ -0,0 +1,148 @@ +Release 13.3 par O.76xd (nt64) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. + +ECE-PHO115-08:: Thu Feb 16 21:15:44 2012 + +par -w -intstyle ise -ol high -mt off ALUSHOW_map.ncd ALUSHOW.ncd ALUSHOW.pcf + + +Constraints file: ALUSHOW.pcf. +Loading device for application Rf_Device from file '6slx16.nph' in environment C:\Xilinx\13.3\ISE_DS\ISE\. + "ALUSHOW" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3 + +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) +Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) + +INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
+ -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
+ internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
+ reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
+ Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". + +Device speed data version: "PRODUCTION 1.20 2011-10-03". + + + +Device Utilization Summary: + +Slice Logic Utilization: + Number of Slice Registers: 0 out of 18,224 0% + Number of Slice LUTs: 860 out of 9,112 9% + Number used as logic: 860 out of 9,112 9% + Number using O6 output only: 365 + Number using O5 output only: 1 + Number using O5 and O6: 494 + Number used as ROM: 0 + Number used as Memory: 0 out of 2,176 0% + +Slice Logic Distribution: + Number of occupied Slices: 268 out of 2,278 11% + Nummber of MUXCYs used: 540 out of 4,556 11% + Number of LUT Flip Flop pairs used: 860 + Number with an unused Flip Flop: 860 out of 860 100% + Number with an unused LUT: 0 out of 860 0% + Number of fully used LUT-FF pairs: 0 out of 860 0% + Number of slice register sites lost + to control set restrictions: 0 out of 18,224 0% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + +IO Utilization: + Number of bonded IOBs: 18 out of 232 7% + Number of LOCed IOBs: 18 out of 18 100% + +Specific Feature Utilization: + Number of RAMB16BWERs: 0 out of 32 0% + Number of RAMB8BWERs: 0 out of 64 0% + Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% + Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% + Number of BUFG/BUFGMUXs: 0 out of 16 0% + Number of DCM/DCM_CLKGENs: 0 out of 4 0% + Number of ILOGIC2/ISERDES2s: 0 out of 248 0% + Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0% + Number of OLOGIC2/OSERDES2s: 0 out of 248 0% + Number of BSCANs: 0 out of 4 0% + Number of BUFHs: 0 out of 128 0% + Number of BUFPLLs: 0 out of 8 0% + Number of BUFPLL_MCBs: 0 out of 4 0% + Number of DSP48A1s: 0 out of 32 0% + Number of ICAPs: 0 out of 1 0% + Number of MCBs: 0 out of 2 0% + Number of PCILOGICSEs: 0 out of 2 0% + Number of PLL_ADVs: 0 out of 2 0% + Number of PMVs: 0 out of 1 0% + Number of STARTUPs: 0 out of 1 0% + Number of SUSPEND_SYNCs: 0 out of 1 0% + + +Overall effort level (-ol): High +Router effort level (-rl): High + +Starting initial Timing Analysis. REAL time: 5 secs +Finished initial Timing Analysis. REAL time: 5 secs + +Starting Router + + +Phase 1 : 4795 unrouted; REAL time: 6 secs + +Phase 2 : 4285 unrouted; REAL time: 6 secs + +Phase 3 : 2216 unrouted; REAL time: 7 secs + +Phase 4 : 2216 unrouted; (Par is working to improve performance) REAL time: 8 secs + +Updating file: ALUSHOW.ncd with current fully routed design. + +Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs + +Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs + +Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs + +Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs + +Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs + +Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs +Total REAL time to Router completion: 9 secs +Total CPU time to Router completion: 8 secs + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Generating "PAR" statistics. +INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode. +Timing Score: 0 (Setup: 0, Hold: 0) + + + +Generating Pad Report. + +All signals are completely routed. + +Total REAL time to PAR completion: 19 secs +Total CPU time to PAR completion: 9 secs + +Peak Memory Usage: 317 MB + +Placer: Placement generated during map. +Routing: Completed - No errors found. + +Number of error messages: 0 +Number of warning messages: 0 +Number of info messages: 2 + +Writing design to file ALUSHOW.ncd + + + +PAR done! |