diff options
Diffstat (limited to 'ALUSHOW.syr')
| -rwxr-xr-x | ALUSHOW.syr | 512 |
1 files changed, 502 insertions, 10 deletions
diff --git a/ALUSHOW.syr b/ALUSHOW.syr index f10b0f6..88aa446 100755 --- a/ALUSHOW.syr +++ b/ALUSHOW.syr @@ -4,13 +4,13 @@ Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.11 secs +Total CPU time to Xst completion: 0.13 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.12 secs +Total CPU time to Xst completion: 0.13 secs --> Reading design: ALUSHOW.prj @@ -105,18 +105,510 @@ Slice Utilization Ratio Delta : 5 ========================================================================= * HDL Parsing * ========================================================================= -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\sev_seg_disp.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab2\sev_seg_disp.vf" into library work Parsing module <sev_seg_disp>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab2\ALU.v" into library work Parsing module <ALU>. -ERROR:HDLCompiler:44 - "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 26: out3 is not a constant -ERROR:HDLCompiler:598 - "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 21: Module <ALU> ignored due to previous errors. -Verilog file \\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v ignored due to errors +WARNING:HDLCompiler:751 - "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab2\ALU.v" Line 27: Redeclaration of ansi port o is not allowed +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab2\ALUSHOW.vf" into library work +Parsing module <sev_seg_disp_MUSER_ALUSHOW>. +Parsing module <ALUSHOW>. + +========================================================================= +* HDL Elaboration * +========================================================================= + +Elaborating module <ALUSHOW>. + +Elaborating module <sev_seg_disp_MUSER_ALUSHOW>. + +Elaborating module <BUF>. + +Elaborating module <GND>. + +Elaborating module <VCC>. + +Elaborating module <AND3>. + +Elaborating module <AND2>. + +Elaborating module <OR5>. + +Elaborating module <INV>. + +Elaborating module <OR4>. + +Elaborating module <XNOR2>. + +Elaborating module <XOR2>. + +Elaborating module <OR3>. + +Elaborating module <OR2>. + +Elaborating module <ALU>. +WARNING:HDLCompiler:413 - "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab2\ALU.v" Line 33: Result of 32-bit expression is truncated to fit in 4-bit target. +WARNING:HDLCompiler:413 - "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab2\ALU.v" Line 35: Result of 32-bit expression is truncated to fit in 4-bit target. + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit <ALUSHOW>. + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab2/alushow.vf". + Summary: + no macro. +Unit <ALUSHOW> synthesized. + +Synthesizing Unit <sev_seg_disp_MUSER_ALUSHOW>. + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab2/alushow.vf". + Summary: + no macro. +Unit <sev_seg_disp_MUSER_ALUSHOW> synthesized. + +Synthesizing Unit <ALU>. + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab2/alu.v". + Found 4-bit adder for signal <n0021> created at line 34. + Found 4-bit adder for signal <GND_15_o_GND_15_o_add_8_OUT> created at line 34. + Found 32-bit adder for signal <GND_15_o_GND_15_o_add_13_OUT> created at line 35. + Found 32-bit adder for signal <GND_15_o_GND_15_o_add_16_OUT> created at line 35. + Found 4-bit 4-to-1 multiplexer for signal <o> created at line 31. + Summary: + inferred 4 Adder/Subtractor(s). + inferred 4 Multiplexer(s). +Unit <ALU> synthesized. + +Synthesizing Unit <mod_4u_2u>. + Related source file is "". + Found 6-bit adder for signal <GND_16_o_b[1]_add_1_OUT> created at line 0. + Found 5-bit adder for signal <GND_16_o_b[1]_add_3_OUT> created at line 0. + Found 4-bit adder for signal <a[3]_b[1]_add_5_OUT> created at line 0. + Found 4-bit adder for signal <a[3]_GND_16_o_add_7_OUT> created at line 0. + Found 4-bit adder for signal <a[3]_GND_16_o_add_9_OUT> created at line 0. + Found 6-bit comparator lessequal for signal <BUS_0001> created at line 0 + Found 5-bit comparator lessequal for signal <BUS_0002> created at line 0 + Found 4-bit comparator lessequal for signal <BUS_0003> created at line 0 + Found 4-bit comparator lessequal for signal <BUS_0004> created at line 0 + Found 4-bit comparator lessequal for signal <BUS_0005> created at line 0 + Summary: + inferred 5 Adder/Subtractor(s). + inferred 5 Comparator(s). + inferred 17 Multiplexer(s). +Unit <mod_4u_2u> synthesized. + +Synthesizing Unit <mod_32u_2u>. + Related source file is "". + Found 34-bit adder for signal <GND_17_o_b[1]_add_1_OUT> created at line 0. + Found 33-bit adder for signal <GND_17_o_b[1]_add_3_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_b[1]_add_5_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_7_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_9_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_11_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_13_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_15_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_17_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_19_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_21_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_23_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_25_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_27_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_29_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_31_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_33_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_35_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_37_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_39_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_41_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_43_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_45_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_47_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_49_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_51_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_53_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_55_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_57_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_59_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_61_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_63_OUT> created at line 0. + Found 32-bit adder for signal <a[31]_GND_17_o_add_65_OUT> created at line 0. + Found 34-bit comparator lessequal for signal <BUS_0001> created at line 0 + Found 33-bit comparator lessequal for signal <BUS_0002> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0003> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0004> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0005> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0006> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0007> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0008> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0009> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0010> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0011> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0012> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0013> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0014> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0015> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0016> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0017> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0018> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0019> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0020> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0021> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0022> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0023> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0024> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0025> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0026> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0027> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0028> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0029> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0030> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0031> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0032> created at line 0 + Found 32-bit comparator lessequal for signal <BUS_0033> created at line 0 + Summary: + inferred 33 Adder/Subtractor(s). + inferred 33 Comparator(s). + inferred 1025 Multiplexer(s). +Unit <mod_32u_2u> synthesized. + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Adders/Subtractors : 42 + 32-bit adder : 33 + 33-bit adder : 1 + 34-bit adder : 1 + 4-bit adder : 5 + 5-bit adder : 1 + 6-bit adder : 1 +# Comparators : 38 + 32-bit comparator lessequal : 31 + 33-bit comparator lessequal : 1 + 34-bit comparator lessequal : 1 + 4-bit comparator lessequal : 3 + 5-bit comparator lessequal : 1 + 6-bit comparator lessequal : 1 +# Multiplexers : 1046 + 1-bit 2-to-1 multiplexer : 1040 + 2-bit 2-to-1 multiplexer : 2 + 32-bit 2-to-1 multiplexer : 2 + 4-bit 2-to-1 multiplexer : 1 + 4-bit 4-to-1 multiplexer : 1 + +========================================================================= + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# Adders/Subtractors : 42 + 2-bit adder : 2 + 32-bit adder : 34 + 4-bit adder : 6 +# Comparators : 38 + 32-bit comparator lessequal : 31 + 33-bit comparator lessequal : 1 + 34-bit comparator lessequal : 1 + 4-bit comparator lessequal : 3 + 5-bit comparator lessequal : 1 + 6-bit comparator lessequal : 1 +# Multiplexers : 1046 + 1-bit 2-to-1 multiplexer : 1040 + 2-bit 2-to-1 multiplexer : 2 + 32-bit 2-to-1 multiplexer : 2 + 4-bit 2-to-1 multiplexer : 1 + 4-bit 4-to-1 multiplexer : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit <ALUSHOW> ... + +Optimizing unit <sev_seg_disp_MUSER_ALUSHOW> ... + +Optimizing unit <ALU> ... + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block ALUSHOW, actual ratio is 14. + +Final Macro Processing ... + +========================================================================= +Final Register Report + +Found no macro +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Design Summary * +========================================================================= + +Top Level Output File Name : ALUSHOW.ngc + +Primitive and Black Box Usage: +------------------------------ +# BELS : 1959 +# AND2 : 13 +# AND3 : 7 +# BUF : 4 +# GND : 1 +# INV : 13 +# LUT2 : 4 +# LUT3 : 267 +# LUT4 : 35 +# LUT5 : 519 +# LUT6 : 183 +# MUXCY : 468 +# MUXF7 : 5 +# OR2 : 1 +# OR3 : 1 +# OR4 : 4 +# OR5 : 1 +# VCC : 1 +# XNOR2 : 1 +# XOR2 : 1 +# XORCY : 430 +# IO Buffers : 18 +# IBUF : 6 +# OBUF : 12 + +Device utilization summary: +--------------------------- + +Selected Device : 6slx16csg324-3 + + +Slice Logic Utilization: + Number of Slice LUTs: 1021 out of 9112 11% + Number used as Logic: 1021 out of 9112 11% + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 1021 + Number with an unused Flip Flop: 1021 out of 1021 100% + Number with an unused LUT: 0 out of 1021 0% + Number of fully used LUT-FF pairs: 0 out of 1021 0% + Number of unique control sets: 0 + +IO Utilization: + Number of IOs: 18 + Number of bonded IOBs: 18 out of 232 7% + +Specific Feature Utilization: + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +Timing Report + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +No clock signals found in this design + +Asynchronous Control Signals Information: +---------------------------------------- +No asynchronous control signals found in this design + +Timing Summary: +--------------- +Speed Grade: -3 + + Minimum period: No path found + Minimum input arrival time before clock: No path found + Maximum output required time after clock: No path found + Maximum combinational path delay: 98.229ns + +Timing Details: +--------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 138831793042386680000000000000000000 / 8 +------------------------------------------------------------------------- +Delay: 98.229ns (Levels of Logic = 125) + Source: A<2> (PAD) + Destination: do (PAD) + + Data Path: A<2> to do + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 85 1.222 2.007 A_2_IBUF (A_2_IBUF) + LUT4:I1->O 1 0.205 0.000 XLXI_4/Madd_GND_15_o_GND_15_o_add_13_OUT_cy<3>1117 (XLXI_4/Madd_GND_15_o_GND_15_o_add_13_OUT_cy<3>1116) + MUXCY:S->O 1 0.172 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Madd_a[31]_GND_17_o_add_25_OUT_cy<20> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Madd_a[31]_GND_17_o_add_25_OUT_cy<20>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Madd_a[31]_GND_17_o_add_25_OUT_cy<21> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Madd_a[31]_GND_17_o_add_25_OUT_cy<21>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Madd_a[31]_GND_17_o_add_25_OUT_cy<22> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Madd_a[31]_GND_17_o_add_25_OUT_cy<22>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Madd_a[31]_GND_17_o_add_25_OUT_cy<23> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Madd_a[31]_GND_17_o_add_25_OUT_cy<23>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Madd_a[31]_GND_17_o_add_25_OUT_cy<24> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Madd_a[31]_GND_17_o_add_25_OUT_cy<24>) + XORCY:CI->O 2 0.180 0.961 XLXI_4/GND_15_o_PWR_15_o_mod_14/Madd_a[31]_GND_17_o_add_25_OUT_xor<25> (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[31]_GND_17_o_add_25_OUT<25>) + LUT5:I0->O 3 0.203 1.015 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[25]_a[31]_MUX_567_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[25]_a[31]_MUX_567_o) + LUT6:I0->O 1 0.203 0.684 XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0014_INV_501_o22 (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0014_INV_501_o21) + LUT6:I4->O 26 0.203 1.435 XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0014_INV_501_o24 (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0014_INV_501_o) + LUT3:I0->O 3 0.205 1.015 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[24]_a[31]_MUX_600_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[24]_a[31]_MUX_600_o) + LUT6:I0->O 28 0.203 1.579 XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0015_INV_534_o21 (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0015_INV_534_o2) + LUT6:I1->O 5 0.203 1.079 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[30]_a[31]_MUX_626_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[30]_a[31]_MUX_626_o) + LUT6:I0->O 1 0.203 0.808 XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0016_INV_567_o22 (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0016_INV_567_o21) + LUT6:I3->O 57 0.205 1.822 XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0016_INV_567_o23 (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0016_INV_567_o) + LUT3:I0->O 1 0.205 0.944 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[25]_a[31]_MUX_663_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[25]_a[31]_MUX_663_o) + LUT6:I0->O 1 0.203 0.944 XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0017_INV_600_o21 (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0017_INV_600_o2) + LUT6:I0->O 36 0.203 1.693 XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0017_INV_600_o23 (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0017_INV_600_o) + LUT5:I0->O 3 0.203 0.995 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[22]_a[31]_MUX_698_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[22]_a[31]_MUX_698_o) + LUT5:I0->O 1 0.203 0.808 XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0018_INV_633_o21 (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0018_INV_633_o2) + LUT5:I2->O 34 0.205 1.549 XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0018_INV_633_o24 (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0018_INV_633_o) + LUT3:I0->O 3 0.205 1.015 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[21]_a[31]_MUX_731_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[21]_a[31]_MUX_731_o) + LUT6:I0->O 36 0.203 1.596 XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0019_INV_666_o21 (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0019_INV_666_o2) + LUT5:I1->O 5 0.203 1.059 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[30]_a[31]_MUX_754_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[30]_a[31]_MUX_754_o) + LUT5:I0->O 3 0.203 0.879 XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0020_INV_699_o31 (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0020_INV_699_o3) + LUT5:I2->O 66 0.205 1.882 XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0020_INV_699_o34 (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0020_INV_699_o) + LUT3:I0->O 1 0.205 0.944 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[29]_a[31]_MUX_787_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[29]_a[31]_MUX_787_o) + LUT6:I0->O 3 0.203 0.898 XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0021_INV_732_o31 (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0021_INV_732_o3) + LUT5:I1->O 43 0.203 1.793 XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0021_INV_732_o34 (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0021_INV_732_o) + LUT5:I0->O 8 0.203 1.147 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[30]_a[31]_MUX_818_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[30]_a[31]_MUX_818_o) + LUT5:I0->O 0 0.203 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0022_INV_765_o_lutdi3 (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0022_INV_765_o_lutdi3) + MUXCY:DI->O 1 0.145 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0022_INV_765_o_cy<3> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0022_INV_765_o_cy<3>) + MUXCY:CI->O 46 0.213 1.835 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0022_INV_765_o_cy<4> (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0022_INV_765_o) + LUT5:I0->O 4 0.203 0.931 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[13]_a[31]_MUX_867_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[13]_a[31]_MUX_867_o) + LUT5:I1->O 1 0.203 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0023_INV_798_o_lut<0> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0023_INV_798_o_lut<0>) + MUXCY:S->O 1 0.172 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0023_INV_798_o_cy<0> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0023_INV_798_o_cy<0>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0023_INV_798_o_cy<1> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0023_INV_798_o_cy<1>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0023_INV_798_o_cy<2> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0023_INV_798_o_cy<2>) + MUXCY:CI->O 43 0.213 1.449 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0023_INV_798_o_cy<3> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0023_INV_798_o_cy<3>) + LUT3:I2->O 2 0.205 0.981 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0023_INV_798_o_cy<4> (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0023_INV_798_o) + LUT6:I0->O 3 0.203 0.755 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[10]_a[31]_MUX_902_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[10]_a[31]_MUX_902_o) + LUT5:I3->O 1 0.203 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0024_INV_831_o_lut<0> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0024_INV_831_o_lut<0>) + MUXCY:S->O 1 0.172 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0024_INV_831_o_cy<0> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0024_INV_831_o_cy<0>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0024_INV_831_o_cy<1> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0024_INV_831_o_cy<1>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0024_INV_831_o_cy<2> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0024_INV_831_o_cy<2>) + MUXCY:CI->O 45 0.213 1.477 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0024_INV_831_o_cy<3> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0024_INV_831_o_cy<3>) + LUT4:I3->O 2 0.205 0.981 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0024_INV_831_o_cy<4> (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0024_INV_831_o) + LUT6:I0->O 5 0.203 0.819 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[9]_a[31]_MUX_935_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[9]_a[31]_MUX_935_o) + LUT5:I3->O 1 0.203 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0025_INV_864_o_lut<0> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0025_INV_864_o_lut<0>) + MUXCY:S->O 1 0.172 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0025_INV_864_o_cy<0> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0025_INV_864_o_cy<0>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0025_INV_864_o_cy<1> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0025_INV_864_o_cy<1>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0025_INV_864_o_cy<2> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0025_INV_864_o_cy<2>) + MUXCY:CI->O 1 0.213 0.580 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0025_INV_864_o_cy<3> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0025_INV_864_o_cy<3>) + LUT5:I4->O 94 0.205 2.066 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0025_INV_864_o_cy<4> (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0025_INV_864_o) + LUT3:I0->O 4 0.205 1.028 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[9]_a[31]_MUX_967_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[9]_a[31]_MUX_967_o) + LUT5:I0->O 1 0.203 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0026_INV_897_o_lut<0> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0026_INV_897_o_lut<0>) + MUXCY:S->O 1 0.172 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0026_INV_897_o_cy<0> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0026_INV_897_o_cy<0>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0026_INV_897_o_cy<1> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0026_INV_897_o_cy<1>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0026_INV_897_o_cy<2> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0026_INV_897_o_cy<2>) + MUXCY:CI->O 1 0.213 0.580 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0026_INV_897_o_cy<3> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0026_INV_897_o_cy<3>) + LUT6:I5->O 98 0.205 2.209 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0026_INV_897_o_cy<4> (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0026_INV_897_o) + LUT5:I0->O 2 0.203 0.961 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[11]_a[31]_MUX_997_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[11]_a[31]_MUX_997_o) + LUT5:I0->O 1 0.203 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0027_INV_930_o_lut<1> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0027_INV_930_o_lut<1>) + MUXCY:S->O 1 0.172 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0027_INV_930_o_cy<1> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0027_INV_930_o_cy<1>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0027_INV_930_o_cy<2> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0027_INV_930_o_cy<2>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0027_INV_930_o_cy<3> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0027_INV_930_o_cy<3>) + MUXCY:CI->O 1 0.213 0.684 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0027_INV_930_o_cy<4> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0027_INV_930_o_cy<4>) + LUT6:I4->O 52 0.203 1.905 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0027_INV_930_o_cy<5> (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0027_INV_930_o) + LUT5:I0->O 4 0.203 1.028 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[10]_a[31]_MUX_1030_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[10]_a[31]_MUX_1030_o) + LUT5:I0->O 1 0.203 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0028_INV_963_o_lut<1> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0028_INV_963_o_lut<1>) + MUXCY:S->O 1 0.172 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0028_INV_963_o_cy<1> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0028_INV_963_o_cy<1>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0028_INV_963_o_cy<2> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0028_INV_963_o_cy<2>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0028_INV_963_o_cy<3> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0028_INV_963_o_cy<3>) + MUXCY:CI->O 53 0.213 1.568 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0028_INV_963_o_cy<4> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0028_INV_963_o_cy<4>) + LUT3:I2->O 2 0.205 0.981 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0028_INV_963_o_cy<5> (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0028_INV_963_o) + LUT6:I0->O 3 0.203 0.755 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[5]_a[31]_MUX_1067_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[5]_a[31]_MUX_1067_o) + LUT5:I3->O 1 0.203 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0029_INV_996_o_lut<0> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0029_INV_996_o_lut<0>) + MUXCY:S->O 1 0.172 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0029_INV_996_o_cy<0> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0029_INV_996_o_cy<0>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0029_INV_996_o_cy<1> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0029_INV_996_o_cy<1>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0029_INV_996_o_cy<2> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0029_INV_996_o_cy<2>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0029_INV_996_o_cy<3> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0029_INV_996_o_cy<3>) + MUXCY:CI->O 55 0.213 1.581 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0029_INV_996_o_cy<4> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0029_INV_996_o_cy<4>) + LUT4:I3->O 2 0.205 0.981 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0029_INV_996_o_cy<5> (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0029_INV_996_o) + LUT6:I0->O 5 0.203 0.819 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[4]_a[31]_MUX_1100_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[4]_a[31]_MUX_1100_o) + LUT5:I3->O 1 0.203 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0030_INV_1029_o_lut<0> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0030_INV_1029_o_lut<0>) + MUXCY:S->O 1 0.172 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0030_INV_1029_o_cy<0> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0030_INV_1029_o_cy<0>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0030_INV_1029_o_cy<1> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0030_INV_1029_o_cy<1>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0030_INV_1029_o_cy<2> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0030_INV_1029_o_cy<2>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0030_INV_1029_o_cy<3> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0030_INV_1029_o_cy<3>) + MUXCY:CI->O 5 0.213 0.715 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0030_INV_1029_o_cy<4> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0030_INV_1029_o_cy<4>) + LUT5:I4->O 110 0.205 2.132 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0030_INV_1029_o_cy<5> (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0030_INV_1029_o) + LUT3:I0->O 3 0.205 0.995 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[4]_a[31]_MUX_1132_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[4]_a[31]_MUX_1132_o) + LUT5:I0->O 1 0.203 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0031_INV_1062_o_lut<0> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0031_INV_1062_o_lut<0>) + MUXCY:S->O 1 0.172 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0031_INV_1062_o_cy<0> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0031_INV_1062_o_cy<0>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0031_INV_1062_o_cy<1> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0031_INV_1062_o_cy<1>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0031_INV_1062_o_cy<2> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0031_INV_1062_o_cy<2>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0031_INV_1062_o_cy<3> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0031_INV_1062_o_cy<3>) + MUXCY:CI->O 1 0.213 0.580 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0031_INV_1062_o_cy<4> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0031_INV_1062_o_cy<4>) + LUT6:I5->O 89 0.205 2.149 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0031_INV_1062_o_cy<5> (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0031_INV_1062_o) + LUT5:I0->O 2 0.203 0.961 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[6]_a[31]_MUX_1162_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[6]_a[31]_MUX_1162_o) + LUT5:I0->O 1 0.203 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0032_INV_1095_o_lut<1> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0032_INV_1095_o_lut<1>) + MUXCY:S->O 1 0.172 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0032_INV_1095_o_cy<1> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0032_INV_1095_o_cy<1>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0032_INV_1095_o_cy<2> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0032_INV_1095_o_cy<2>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0032_INV_1095_o_cy<3> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0032_INV_1095_o_cy<3>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0032_INV_1095_o_cy<4> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0032_INV_1095_o_cy<4>) + MUXCY:CI->O 2 0.213 0.721 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0032_INV_1095_o_cy<5> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0032_INV_1095_o_cy<5>) + LUT6:I4->O 29 0.203 1.594 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0032_INV_1095_o_cy<6> (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0032_INV_1095_o) + LUT5:I0->O 2 0.203 0.961 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mmux_a[5]_a[31]_MUX_1195_o11 (XLXI_4/GND_15_o_PWR_15_o_mod_14/a[5]_a[31]_MUX_1195_o) + LUT5:I0->O 1 0.203 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0033_INV_1128_o_lut<1> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0033_INV_1128_o_lut<1>) + MUXCY:S->O 1 0.172 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0033_INV_1128_o_cy<1> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0033_INV_1128_o_cy<1>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0033_INV_1128_o_cy<2> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0033_INV_1128_o_cy<2>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0033_INV_1128_o_cy<3> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0033_INV_1128_o_cy<3>) + MUXCY:CI->O 1 0.019 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0033_INV_1128_o_cy<4> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0033_INV_1128_o_cy<4>) + MUXCY:CI->O 2 0.213 0.617 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0033_INV_1128_o_cy<5> (XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0033_INV_1128_o_cy<5>) + LUT3:I2->O 1 0.205 0.000 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0033_INV_1128_o_cy<6>_G (N15) + MUXF7:I1->O 4 0.140 1.028 XLXI_4/GND_15_o_PWR_15_o_mod_14/Mcompar_BUS_0033_INV_1128_o_cy<6> (XLXI_4/GND_15_o_PWR_15_o_mod_14/BUS_0033_INV_1128_o) + LUT6:I1->O 1 0.203 0.827 XLXI_4/Mmux_o34 (XLXI_4/Mmux_o33) + LUT5:I1->O 1 0.203 0.000 XLXI_4/Mmux_o35_G (N13) + MUXF7:I1->O 8 0.140 0.802 XLXI_4/Mmux_o35 (ALU_OUT<2>) + INV:I->O 7 0.568 1.118 XLXI_2/XLXI_38 (XLXI_2/B_BAR) + AND2:I1->O 2 0.223 0.864 XLXI_2/XLXI_49 (XLXI_2/XLXN_126) + OR4:I2->O 1 0.320 0.579 XLXI_2/XLXI_52 (XLXI_2/XLXN_156) + INV:I->O 1 0.568 0.579 XLXI_2/XLXI_69 (do_OBUF) + OBUF:I->O 2.571 do_OBUF (do) + ---------------------------------------- + Total 98.229ns (23.504ns logic, 74.725ns route) + (23.9% logic, 76.1% route) + +========================================================================= + +Cross Clock Domains Report: +-------------------------- + +========================================================================= + + +Total REAL time to Xst completion: 16.00 secs +Total CPU time to Xst completion: 16.02 secs + --> -Total memory usage is 201016 kilobytes +Total memory usage is 263104 kilobytes -Number of errors : 2 ( 0 filtered) -Number of warnings : 0 ( 0 filtered) +Number of errors : 0 ( 0 filtered) +Number of warnings : 3 ( 0 filtered) Number of infos : 0 ( 0 filtered) |