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Diffstat (limited to 'ALUSHOW_map.map')
| -rwxr-xr-x | ALUSHOW_map.map | 138 |
1 files changed, 138 insertions, 0 deletions
diff --git a/ALUSHOW_map.map b/ALUSHOW_map.map new file mode 100755 index 0000000..e6cbc8f --- /dev/null +++ b/ALUSHOW_map.map @@ -0,0 +1,138 @@ +Release 13.3 Map O.76xd (nt64) +Xilinx Map Application Log File for Design 'ALUSHOW' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol
+high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
+-pr off -lc off -power off -o ALUSHOW_map.ncd ALUSHOW.ngd ALUSHOW.pcf +Target Device : xc6slx16 +Target Package : csg324 +Target Speed : -3 +Mapper Version : spartan6 -- $Revision: 1.55 $ +Mapped Date : Thu Feb 16 21:15:30 2012 + +Mapping design into LUTs... +Running directed packing... +Running delay-based LUT packing... +Updating timing models... +INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
+ (.mrp). +Running timing-driven placement... +Total REAL time at the beginning of Placer: 7 secs +Total CPU time at the beginning of Placer: 6 secs + +Phase 1.1 Initial Placement Analysis +Phase 1.1 Initial Placement Analysis (Checksum:d622556c) REAL time: 8 secs + +Phase 2.7 Design Feasibility Check +Phase 2.7 Design Feasibility Check (Checksum:d622556c) REAL time: 8 secs + +Phase 3.31 Local Placement Optimization +Phase 3.31 Local Placement Optimization (Checksum:d622556c) REAL time: 8 secs + +Phase 4.2 Initial Placement for Architecture Specific Features +Phase 4.2 Initial Placement for Architecture Specific Features
+(Checksum:d622556c) REAL time: 9 secs + +Phase 5.36 Local Placement Optimization +Phase 5.36 Local Placement Optimization (Checksum:d622556c) REAL time: 9 secs + +Phase 6.30 Global Clock Region Assignment +Phase 6.30 Global Clock Region Assignment (Checksum:d622556c) REAL time: 9 secs + +Phase 7.3 Local Placement Optimization +Phase 7.3 Local Placement Optimization (Checksum:d622556c) REAL time: 9 secs + +Phase 8.5 Local Placement Optimization +Phase 8.5 Local Placement Optimization (Checksum:d622556c) REAL time: 9 secs + +Phase 9.8 Global Placement +........................... +............. +Phase 9.8 Global Placement (Checksum:bb0f3624) REAL time: 9 secs + +Phase 10.5 Local Placement Optimization +Phase 10.5 Local Placement Optimization (Checksum:bb0f3624) REAL time: 9 secs + +Phase 11.18 Placement Optimization +Phase 11.18 Placement Optimization (Checksum:7898aed4) REAL time: 10 secs + +Phase 12.5 Local Placement Optimization +Phase 12.5 Local Placement Optimization (Checksum:7898aed4) REAL time: 10 secs + +Phase 13.34 Placement Validation +Phase 13.34 Placement Validation (Checksum:7898aed4) REAL time: 10 secs + +Total REAL time to Placer completion: 10 secs +Total CPU time to Placer completion: 9 secs +Running post-placement packing... +Writing output files... + +Design Summary +-------------- + +Design Summary: +Number of errors: 0 +Number of warnings: 0 +Slice Logic Utilization: + Number of Slice Registers: 0 out of 18,224 0% + Number of Slice LUTs: 860 out of 9,112 9% + Number used as logic: 860 out of 9,112 9% + Number using O6 output only: 365 + Number using O5 output only: 1 + Number using O5 and O6: 494 + Number used as ROM: 0 + Number used as Memory: 0 out of 2,176 0% + +Slice Logic Distribution: + Number of occupied Slices: 268 out of 2,278 11% + Nummber of MUXCYs used: 540 out of 4,556 11% + Number of LUT Flip Flop pairs used: 860 + Number with an unused Flip Flop: 860 out of 860 100% + Number with an unused LUT: 0 out of 860 0% + Number of fully used LUT-FF pairs: 0 out of 860 0% + Number of slice register sites lost + to control set restrictions: 0 out of 18,224 0% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + +IO Utilization: + Number of bonded IOBs: 18 out of 232 7% + Number of LOCed IOBs: 18 out of 18 100% + +Specific Feature Utilization: + Number of RAMB16BWERs: 0 out of 32 0% + Number of RAMB8BWERs: 0 out of 64 0% + Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% + Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% + Number of BUFG/BUFGMUXs: 0 out of 16 0% + Number of DCM/DCM_CLKGENs: 0 out of 4 0% + Number of ILOGIC2/ISERDES2s: 0 out of 248 0% + Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0% + Number of OLOGIC2/OSERDES2s: 0 out of 248 0% + Number of BSCANs: 0 out of 4 0% + Number of BUFHs: 0 out of 128 0% + Number of BUFPLLs: 0 out of 8 0% + Number of BUFPLL_MCBs: 0 out of 4 0% + Number of DSP48A1s: 0 out of 32 0% + Number of ICAPs: 0 out of 1 0% + Number of MCBs: 0 out of 2 0% + Number of PCILOGICSEs: 0 out of 2 0% + Number of PLL_ADVs: 0 out of 2 0% + Number of PMVs: 0 out of 1 0% + Number of STARTUPs: 0 out of 1 0% + Number of SUSPEND_SYNCs: 0 out of 1 0% + +Average Fanout of Non-Clock Nets: 4.13 + +Peak Memory Usage: 363 MB +Total REAL time to MAP completion: 11 secs +Total CPU time to MAP completion: 10 secs + +Mapping completed. +See MAP report file "ALUSHOW_map.mrp" for details. |