diff options
Diffstat (limited to '_xmsgs')
| -rwxr-xr-x | _xmsgs/bitgen.xmsgs | 9 | ||||
| -rwxr-xr-x | _xmsgs/map.xmsgs | 27 | ||||
| -rwxr-xr-x | _xmsgs/ngdbuild.xmsgs | 9 | ||||
| -rwxr-xr-x | _xmsgs/par.xmsgs | 15 | ||||
| -rwxr-xr-x | _xmsgs/pn_parser.xmsgs | 24 | ||||
| -rwxr-xr-x | _xmsgs/trce.xmsgs | 15 | ||||
| -rwxr-xr-x | _xmsgs/xst.xmsgs | 7 |
7 files changed, 92 insertions, 14 deletions
diff --git a/_xmsgs/bitgen.xmsgs b/_xmsgs/bitgen.xmsgs new file mode 100755 index 0000000..c42b14a --- /dev/null +++ b/_xmsgs/bitgen.xmsgs @@ -0,0 +1,9 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +</messages> +
diff --git a/_xmsgs/map.xmsgs b/_xmsgs/map.xmsgs new file mode 100755 index 0000000..4ecf2a7 --- /dev/null +++ b/_xmsgs/map.xmsgs @@ -0,0 +1,27 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
+</msg>
+ +<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
+</msg>
+ +<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
+</msg>
+ +<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
+</msg>
+ +<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
+</msg>
+ +<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
+</msg>
+ +</messages> +
diff --git a/_xmsgs/ngdbuild.xmsgs b/_xmsgs/ngdbuild.xmsgs new file mode 100755 index 0000000..c42b14a --- /dev/null +++ b/_xmsgs/ngdbuild.xmsgs @@ -0,0 +1,9 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +</messages> +
diff --git a/_xmsgs/par.xmsgs b/_xmsgs/par.xmsgs new file mode 100755 index 0000000..5f1f5f1 --- /dev/null +++ b/_xmsgs/par.xmsgs @@ -0,0 +1,15 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +<msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
+</msg>
+ +<msg type="info" file="Par" num="459" delta="old" >The Clock Report is not displayed in the non timing-driven mode.
+</msg>
+ +</messages> +
diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs index 2211003..ee464b0 100755 --- a/_xmsgs/pn_parser.xmsgs +++ b/_xmsgs/pn_parser.xmsgs @@ -1,12 +1,12 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!-- IMPORTANT: This is an internal file that has been generated --> -<!-- by the Xilinx ISE software. Any direct editing or --> -<!-- changes made to this file may result in unpredictable --> -<!-- behavior or data corruption. It is strongly advised that --> -<!-- users do not edit the contents of this file. --> -<!-- --> -<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> - -<messages> -</messages> - +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated -->
+<!-- by the Xilinx ISE software. Any direct editing or -->
+<!-- changes made to this file may result in unpredictable -->
+<!-- behavior or data corruption. It is strongly advised that -->
+<!-- users do not edit the contents of this file. -->
+<!-- -->
+<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+
+<messages>
+</messages>
+
diff --git a/_xmsgs/trce.xmsgs b/_xmsgs/trce.xmsgs new file mode 100755 index 0000000..80cb2e4 --- /dev/null +++ b/_xmsgs/trce.xmsgs @@ -0,0 +1,15 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +<msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg>
+ +<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
+ +<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
+ +</messages> +
diff --git a/_xmsgs/xst.xmsgs b/_xmsgs/xst.xmsgs index 8233bd5..3e430a7 100755 --- a/_xmsgs/xst.xmsgs +++ b/_xmsgs/xst.xmsgs @@ -5,10 +5,13 @@ behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages> -<msg type="error" file="HDLCompiler" num="44" delta="new" >"\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 26: <arg fmt="%s" index="1">out3</arg> is not a constant
+<msg type="warning" file="HDLCompiler" num="751" delta="old" >"\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab2\ALU.v" Line 27: Redeclaration of ansi port <arg fmt="%s" index="1">o</arg> is not allowed
</msg>
-<msg type="error" file="HDLCompiler" num="598" delta="new" >"\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 21: Module <<arg fmt="%s" index="1">ALU</arg>> ignored due to previous errors.
+<msg type="warning" file="HDLCompiler" num="413" delta="old" >"\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab2\ALU.v" Line 33: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">4</arg>-bit target.
+</msg>
+ +<msg type="warning" file="HDLCompiler" num="413" delta="old" >"\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab2\ALU.v" Line 35: Result of <arg fmt="%d" index="1">32</arg>-bit expression is truncated to fit in <arg fmt="%d" index="2">4</arg>-bit target.
</msg>
</messages> |