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-rwxr-xr-xplanAhead_run_2/lab2.data/constrs_1/designprops.xml29
-rwxr-xr-x[-rw-r--r--]planAhead_run_2/lab2.data/constrs_1/fileset.xml70
-rwxr-xr-xplanAhead_run_2/lab2.data/constrs_1/usercols.xml4
-rwxr-xr-x[-rw-r--r--]planAhead_run_2/lab2.data/sources_1/fileset.xml112
-rwxr-xr-xplanAhead_run_2/lab2.data/sources_1/ports.xml28
5 files changed, 167 insertions, 76 deletions
diff --git a/planAhead_run_2/lab2.data/constrs_1/designprops.xml b/planAhead_run_2/lab2.data/constrs_1/designprops.xml
new file mode 100755
index 0000000..841b5cf
--- /dev/null
+++ b/planAhead_run_2/lab2.data/constrs_1/designprops.xml
@@ -0,0 +1,29 @@
+<?xml version="1.0"?>
+<Compat Version="1" Minor="4">
+ <CompatParts>
+ </CompatParts>
+ <ConfigModes>
+ <Mode Id="JTAG"/>
+ </ConfigModes>
+ <PortProps>
+ <Port Name="A[3]" OffChipTerm="NONE"/>
+ <Port Name="A[2]" OffChipTerm="NONE"/>
+ <Port Name="A[1]" OffChipTerm="NONE"/>
+ <Port Name="A[0]" OffChipTerm="NONE"/>
+ <Port Name="S[1]" OffChipTerm="NONE"/>
+ <Port Name="S[0]" OffChipTerm="NONE"/>
+ <Port Name="AN0" OffChipTerm="FP_VTT_50"/>
+ <Port Name="AN1" OffChipTerm="FP_VTT_50"/>
+ <Port Name="AN2" OffChipTerm="FP_VTT_50"/>
+ <Port Name="AN3" OffChipTerm="FP_VTT_50"/>
+ <Port Name="ao" OffChipTerm="FP_VTT_50"/>
+ <Port Name="bo" OffChipTerm="FP_VTT_50"/>
+ <Port Name="co" OffChipTerm="FP_VTT_50"/>
+ <Port Name="do" OffChipTerm="FP_VTT_50"/>
+ <Port Name="eo" OffChipTerm="FP_VTT_50"/>
+ <Port Name="fo" OffChipTerm="FP_VTT_50"/>
+ <Port Name="go" OffChipTerm="FP_VTT_50"/>
+ <Port Name="sign" OffChipTerm="FP_VTT_50"/>
+ </PortProps>
+</Compat>
+
diff --git a/planAhead_run_2/lab2.data/constrs_1/fileset.xml b/planAhead_run_2/lab2.data/constrs_1/fileset.xml
index 528719e..46533c8 100644..100755
--- a/planAhead_run_2/lab2.data/constrs_1/fileset.xml
+++ b/planAhead_run_2/lab2.data/constrs_1/fileset.xml
@@ -1,25 +1,45 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DARoots Version="1"
- Minor="19">
- <FileSet Name="constrs_1"
- Type="Constrs"
- RelSrcDir="$PSRCDIR/constrs_1">
- <Filter Type="Constrs"/>
- <File Path="$PPRDIR/../ALUSHOW.ucf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <Config>
- <Option Name="TargetConstrsFile"
- Val="$PPRDIR/../ALUSHOW.ucf"/>
- <Option Name="ConstrsType"
- Val="UCF"/>
- </Config>
- </FileSet>
-</DARoots>
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1"
+ Minor="19">
+ <FileSet Name="constrs_1"
+ Type="Constrs"
+ RelSrcDir="$PSRCDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../ALUSHOW.ucf">
+ <FileInfo>
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <File Path="$PDATADIR/constrs_1/designprops.xml">
+ <FileInfo SFType="CompatPartsDb">
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <File Path="$PDATADIR/constrs_1/usercols.xml">
+ <FileInfo SFType="UserColsDb">
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TargetConstrsFile"
+ Val="$PPRDIR/../ALUSHOW.ucf"/>
+ <Option Name="ConstrsType"
+ Val="UCF"/>
+ </Config>
+ </FileSet>
+</DARoots>
diff --git a/planAhead_run_2/lab2.data/constrs_1/usercols.xml b/planAhead_run_2/lab2.data/constrs_1/usercols.xml
new file mode 100755
index 0000000..b2e369a
--- /dev/null
+++ b/planAhead_run_2/lab2.data/constrs_1/usercols.xml
@@ -0,0 +1,4 @@
+<?xml version="1.0"?>
+<UserColInfo Version="1" Minor="0">
+</UserColInfo>
+
diff --git a/planAhead_run_2/lab2.data/sources_1/fileset.xml b/planAhead_run_2/lab2.data/sources_1/fileset.xml
index 3358a4c..81193a8 100644..100755
--- a/planAhead_run_2/lab2.data/sources_1/fileset.xml
+++ b/planAhead_run_2/lab2.data/sources_1/fileset.xml
@@ -1,51 +1,61 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DARoots Version="1"
- Minor="19">
- <FileSet Name="sources_1"
- Type="DesignSrcs"
- RelSrcDir="$PSRCDIR/sources_1">
- <Filter Type="Srcs"/>
- <File Path="$PPRDIR/../sev_seg_disp.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../ALU.v">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../ALUSHOW.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <Config>
- <Option Name="DesignMode"
- Val="RTL"/>
- <Option Name="TopModule"
- Val="ALUSHOW"/>
- <Option Name="TopLib"
- Val="work"/>
- <Option Name="TopRTLFile"
- Val="$PPRDIR/../ALUSHOW.vf"/>
- <Option Name="TopAutoSet"
- Val="TRUE"/>
- </Config>
- </FileSet>
-</DARoots>
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1"
+ Minor="19">
+ <FileSet Name="sources_1"
+ Type="DesignSrcs"
+ RelSrcDir="$PSRCDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../sev_seg_disp.vf">
+ <FileInfo>
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../ALU.v">
+ <FileInfo>
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../ALUSHOW.vf">
+ <FileInfo>
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <File Path="$PDATADIR/sources_1/ports.xml">
+ <FileInfo SFType="PortsDb">
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode"
+ Val="RTL"/>
+ <Option Name="TopModule"
+ Val="ALUSHOW"/>
+ <Option Name="TopLib"
+ Val="work"/>
+ <Option Name="TopRTLFile"
+ Val="$PPRDIR/../ALUSHOW.vf"/>
+ <Option Name="TopAutoSet"
+ Val="TRUE"/>
+ </Config>
+ </FileSet>
+</DARoots>
diff --git a/planAhead_run_2/lab2.data/sources_1/ports.xml b/planAhead_run_2/lab2.data/sources_1/ports.xml
new file mode 100755
index 0000000..1eae741
--- /dev/null
+++ b/planAhead_run_2/lab2.data/sources_1/ports.xml
@@ -0,0 +1,28 @@
+<?xml version="1.0"?>
+<Interface Version="1" Minor="1">
+ <Ifc Id="ROOT" Top="1">
+ <Bus Id="A">
+ <Port Id="3" Dir="IN"/>
+ <Port Id="2" Dir="IN"/>
+ <Port Id="1" Dir="IN"/>
+ <Port Id="0" Dir="IN"/>
+ </Bus>
+ <Bus Id="S">
+ <Port Id="1" Dir="IN"/>
+ <Port Id="0" Dir="IN"/>
+ </Bus>
+ <Port Id="AN0" Dir="OUT"/>
+ <Port Id="AN1" Dir="OUT"/>
+ <Port Id="AN2" Dir="OUT"/>
+ <Port Id="AN3" Dir="OUT"/>
+ <Port Id="ao" Dir="OUT"/>
+ <Port Id="bo" Dir="OUT"/>
+ <Port Id="co" Dir="OUT"/>
+ <Port Id="do" Dir="OUT"/>
+ <Port Id="eo" Dir="OUT"/>
+ <Port Id="fo" Dir="OUT"/>
+ <Port Id="go" Dir="OUT"/>
+ <Port Id="sign" Dir="OUT"/>
+ </Ifc>
+</Interface>
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-10 09:22:50 +0000