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-rw-r--r--CountdownController.v18
-rw-r--r--Test_ContdownController.v4
-rw-r--r--_xmsgs/pn_parser.xmsgs2
-rw-r--r--lab4.gise15
-rw-r--r--lab4.xise8
5 files changed, 33 insertions, 14 deletions
diff --git a/CountdownController.v b/CountdownController.v
index ac50bf0..35c84f9 100644
--- a/CountdownController.v
+++ b/CountdownController.v
@@ -50,9 +50,14 @@ wire [3:0] ado, bdo, cdo;
wire [7:0] init;
wire [7:0] tout;
-ClockDivider dbc(.count(1_000_000), .rst(rst), .clk_in(clk), .clk_out(dbclk));
-ClockDivider sec(.count(100_000_000), .rst(rst), .clk_in(clk), .clk_out(seconds));
-ClockDivider dcc(.count(7_500_000), .rst(rst), .clk_in(clk), .clk_out(dispclk));
+//ClockDivider dbc(.count(1_000_000), .rst(rst), .clk_in(clk), .clk_out(dbclk));
+//ClockDivider sec(.count(100_000_000), .rst(rst), .clk_in(clk), .clk_out(seconds));
+//ClockDivider dcc(.count(7_500_000), .rst(rst), .clk_in(clk), .clk_out(dispclk));
+
+ClockDivider dbc(.count(10), .rst(rst), .clk_in(clk), .clk_out(dbclk));
+ClockDivider sec(.count(100), .rst(rst), .clk_in(clk), .clk_out(seconds));
+ClockDivider dcc(.count(25), .rst(rst), .clk_in(clk), .clk_out(dispclk));
+
debouncer dbA(.dout(a), .din(btnA), .rst(rst), .clk_1M(dbclk));
debouncer dbB(.dout(b), .din(btnB), .rst(rst), .clk_1M(dbclk));
@@ -72,8 +77,7 @@ Bin2BCD b2bcb(.hun(cdo), .ten(ado), .one(bdo), .bin(tout));
DisplayController dispcont(.result(ssdo), .AN(ANo), .A(ado), .B(bdo), .clk_in(dispclk), .rst(rst));
-always @(posedge clk) begin
- ssd <= ssdo;
- AN <= ANo;
-end
+assign ssd = ssdo;
+assign AN = ANo;
+
endmodule
diff --git a/Test_ContdownController.v b/Test_ContdownController.v
index ba3b63c..7450761 100644
--- a/Test_ContdownController.v
+++ b/Test_ContdownController.v
@@ -64,13 +64,13 @@ module Test_ContdownController;
- while (11) begin
+ while (1) begin
clk = ~clk; #1;
if (i < 100) begin
i = i + 1;
if (i == 50) begin
for (j = 0; j < 5; j = j + 1) begin
- btnA = 1; #1
+ btnA = 1; #1;
clk = ~clk;
btnA = 0; #1;
clk = ~clk;
diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs
index 16c15fd..d1c52e5 100644
--- a/_xmsgs/pn_parser.xmsgs
+++ b/_xmsgs/pn_parser.xmsgs
@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages>
-<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;/home/michael/Documents/School/EC311/lab4/CountdownController.v&quot; into library work</arg>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;/home/michael/Documents/School/EC311/lab4/Test_ContdownController.v&quot; into library work</arg>
</msg>
</messages>
diff --git a/lab4.gise b/lab4.gise
index 06772a8..b088a16 100644
--- a/lab4.gise
+++ b/lab4.gise
@@ -57,6 +57,10 @@
<transform xil_pn:end_ts="1332349811" xil_pn:in_ck="-1165842576399624296" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1332349811">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="InputChanged"/>
+ <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="BCD2Bin.v"/>
<outfile xil_pn:name="Bin2BCD.v"/>
<outfile xil_pn:name="ClockDivider.v"/>
@@ -90,6 +94,11 @@
<transform xil_pn:end_ts="1332349811" xil_pn:in_ck="-1165842576399624296" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1332349811">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="InputChanged"/>
+ <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="BCD2Bin.v"/>
<outfile xil_pn:name="Bin2BCD.v"/>
<outfile xil_pn:name="ClockDivider.v"/>
@@ -111,7 +120,11 @@
<transform xil_pn:end_ts="1332349897" xil_pn:in_ck="-1165842576399624296" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-4271467981599954997" xil_pn:start_ts="1332349894">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="OutOfDateForProperties"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="Test_ContdownController_beh.prj"/>
<outfile xil_pn:name="Test_ContdownController_isim_beh.exe"/>
@@ -123,6 +136,8 @@
<transform xil_pn:end_ts="1332349979" xil_pn:in_ck="5762157264321675852" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5372246553278025746" xil_pn:start_ts="1332349978">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForProperties"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="Test_ContdownController_isim_beh.wdb"/>
diff --git a/lab4.xise b/lab4.xise
index ad74d59..1ebb86f 100644
--- a/lab4.xise
+++ b/lab4.xise
@@ -341,8 +341,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_ContdownController" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_ContdownController" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_ContdownController/uut/dbA" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.debouncer" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -353,14 +353,14 @@
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000ns" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="10000ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_ContdownController" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.debouncer" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
generated by cgit v1.2.3-54-g00ecf (git 2.45.2) at 2024-11-24 04:17:46 +0000