1 files changed, 65 insertions, 0 deletions
diff --git a/DisplayController.v b/DisplayController.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:52:48 03/27/2012 
+// Design Name: 
+// Module Name:    DisplayController 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module DisplayController(
+    input [3:0] A,
+    input [3:0] B,
+    input [3:0] C,
+    input [3:0] D,
+	 input clk,
+	 input rst,
+    output [6:0] ssd,
+    output [3:0] AN
+    );
+	 
+	 
+reg [6:0] ssd;
+reg [3:0] AN;
+
+wire clkdiv;
+reg [1:0] w = 2'd0;
+
+ClockDivider cdiv(.clk_out(clkdiv), .rst(rst), .clk_in(clk), .count(500_000));
+
+wire [6:0] o1, o2, o3, o4;
+
+SevSegDisp d1(.result(o1), .A(A));
+SevSegDisp d2(.result(o2), .A(B));
+SevSegDisp d3(.result(o3), .A(C));
+SevSegDisp d4(.result(o4), .A(D));
+
+always @(posedge clkdiv) begin
+	w <= w + 2'd1;
+	case (w) 
+		2'b00: AN <= 4'b1110;
+		2'b01: AN <= 4'b1101;
+		2'b10: AN <= 4'b1011;
+		2'b11: AN <= 4'b0111;
+	endcase
+	case (w) 
+		2'b00: ssd <= o1;
+		2'b01: ssd <= o2;
+		2'b10: ssd <= o3;
+		2'b11: ssd <= o4;
+	endcase
+end
+
+
+endmodule