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| author | Michael Abed <michaelabed@gmail.com> | 2012-04-05 15:53:47 -0400 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-04-05 15:53:47 -0400 |
| commit | c5c3101483a4c2facd67f514f0c320b4192f5844 (patch) | |
| tree | c21262d3e8fadcb21d15da484997b56798f05307 /_xmsgs | |
| download | ec311-lab6-c5c3101483a4c2facd67f514f0c320b4192f5844.tar.gz ec311-lab6-c5c3101483a4c2facd67f514f0c320b4192f5844.tar.bz2 ec311-lab6-c5c3101483a4c2facd67f514f0c320b4192f5844.zip | |
Diffstat (limited to '_xmsgs')
| -rw-r--r-- | _xmsgs/pn_parser.xmsgs | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..54b96d0 --- /dev/null +++ b/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated --> +<!-- by the Xilinx ISE software. Any direct editing or --> +<!-- changes made to this file may result in unpredictable --> +<!-- behavior or data corruption. It is strongly advised that --> +<!-- users do not edit the contents of this file. --> +<!-- --> +<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> + +<messages> +<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/michael/Documents/School/EC311/lab6/FSMController.v" into library work</arg> +</msg> + +</messages> + |