add verilog codeHEADmaster

1 files changed, 36 insertions, 0 deletions

diff --git a/adder_16bit.v b/adder_16bit.v
new file mode 100755
index 0000000..c805b4f
--- /dev/null
+++ b/adder_16bit.v
@@ -0,0 +1,36 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:34:30 09/26/2012 
+// Design Name: 
+// Module Name:    adder_16bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies:
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module adder_16bit(
+    input [15:0] A,
+    input [15:0] B,
+    input Carry_In,
+    output [15:0] Sum,
+    output Carry_Out
+    );
+
+wire c1, c2, c3;
+
+adder_4bit a0(.Carry_Out(c1), .Sum(Sum[3:0]), .A(A[3:0]), .B(B[3:0]), .Carry_In(Carry_In));
+adder_4bit a1(.Carry_Out(c2), .Sum(Sum[7:4]), .A(A[7:4]), .B(B[7:4]), .Carry_In(c1));
+adder_4bit a2(.Carry_Out(c3), .Sum(Sum[11:8]), .A(A[11:8]), .B(B[11:8]), .Carry_In(c2));
+adder_4bit a3(.Carry_Out(Carry_Out), .Sum(Sum[15:12]), .A(A[15:12]), .B(B[15:12]), .Carry_In(c3));
+
+endmodule