add verilog codeHEADmaster

1 files changed, 34 insertions, 0 deletions

diff --git a/adder_64bit.v b/adder_64bit.v
new file mode 100755
index 0000000..05b7934
--- /dev/null
+++ b/adder_64bit.v
@@ -0,0 +1,34 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:10:03 09/26/2012 
+// Design Name: 
+// Module Name:    adder_64bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module adder_64bit(
+    input [63:0] A,
+    input [63:0] B,
+    input Carry_In,
+    output [63:0] Sum,
+    output Carry_Out
+    );
+	 
+wire c1;
+
+adder_32bit a1(.Carry_Out(c1), .Sum(Sum[31:0]), .A(A[31:0]), .B(B[31:0]), .Carry_In(Carry_In));
+adder_32bit a2(.Carry_Out(Carry_Out), .Sum(Sum[63:32]), .A(A[63:32]), .B(B[63:32]), .Carry_In(c1));
+
+endmodule