add verilog codeHEADmaster

1 files changed, 96 insertions, 0 deletions

diff --git a/full_adder.v b/full_adder.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:19:23 09/26/2012 
+// Design Name: 
+// Module Name:    full_adder 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+/////////////////////////////////////////////////////////////////////////////////
+
+
+
+module fa(
+    input A,
+    input B,
+    input Carry_In,
+    output Sum,
+    output Carry_Out
+    );
+`define timed
+`ifdef timed
+
+wire s1, s2, s3, s4; // sum wires
+wire c1, c2, c3; // carry wires
+wire ia, ib, ic; // inverted wires
+
+// invert wires ad needed for the sum
+not n1(ia, A);
+not n2(ib, B);
+not n3(ic, Carry_In);
+
+// SUM CALCULATION
+
+// compute relevant minterms
+and #1 a1(s1, ia, ib, Carry_In);
+and #1 a2(s2, ia, B, ic);
+and #1 a3(s3, A, ib, ic);
+and #1 a4(s4, A, B, Carry_In);
+
+// or minterm results
+or #1 sum(Sum, s1, s2, s3, s4);
+
+// CARRY CALCULATION
+
+// compute minterms
+and #1 ca1(c1, A, B);
+and #1 ca2(c2, A, Carry_In);
+and #1 ca3(c3, B, Carry_In);
+
+// or results
+or #1 cout(Carry_Out, c1, c2, c3);
+
+
+`else
+wire s1, s2, s3, s4; // sum wires
+wire c1, c2, c3; // carry wires
+wire ia, ib, ic; // inverted wires
+
+// invert wires ad needed for the sum
+not n1(ia, A);
+not n2(ib, B);
+not n3(ic, Carry_In);
+
+// SUM CALCULATION
+
+// compute relevant minterms
+and a1(s1, ia, ib, Carry_In);
+and a2(s2, ia, B, ic);
+and a3(s3, A, ib, ic);
+and a4(s4, A, B, Carry_In);
+
+// or minterm results
+or sum(Sum, s1, s2, s3, s4);
+
+// CARRY CALCULATION
+
+// compute minterms
+and ca1(c1, A, B);
+and ca2(c2, A, Carry_In);
+and ca3(c3, B, Carry_In);
+
+// or results
+or cout(Carry_Out, c1, c2, c3); 
+`endif
+endmodule