add verilog codeHEADmaster

1 files changed, 33 insertions, 0 deletions

diff --git a/mux2_4bit.v b/mux2_4bit.v
new file mode 100755
index 0000000..5dd6dc7
--- /dev/null
+++ b/mux2_4bit.v
@@ -0,0 +1,33 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    11:37:54 09/27/2012 
+// Design Name: 
+// Module Name:    mux2_4bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mux2_4bit(
+    input [3:0] a,
+    input [3:0] b,
+    input sel,
+    input [3:0] o
+    );
+
+mux2_1bit m0(.a(a[0]), .b(b[0]), .sel(sel), .o(o[0]));
+mux2_1bit m1(.a(a[1]), .b(b[1]), .sel(sel), .o(o[1]));
+mux2_1bit m2(.a(a[2]), .b(b[2]), .sel(sel), .o(o[2]));
+mux2_1bit m3(.a(a[3]), .b(b[3]), .sel(sel), .o(o[3]));
+
+endmodule