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diff --git a/mux2_1bit.v b/mux2_1bit.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    11:34:03 09/27/2012 
+// Design Name: 
+// Module Name:    mux2_1bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mux2_1bit(
+    input a,
+    input b,
+    input sel,
+    output o
+    );
+
+wire i1; // inverted sel
+wire a1, a2; // ands
+not n1(i1, sel);
+
+and and1(a1, a, sel);
+and and2(a2, b, i1);
+
+or or1(o, a1, a2);
+
+endmodule