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diff --git a/verilog/alu_slice1bit.v b/verilog/alu_slice1bit.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    12:08:08 10/04/2012 
+// Design Name: 
+// Module Name:    alu_slice1bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module alu_slice1bit(
+    output r1,
+    output cout,
+    input r2,
+    input r3,
+    input cin,
+    input [2:0] op
+    );
+
+// wires for operation outputs and carries
+wire movw, notw, notw2, addw, addcw, subw, subcw, orw, andw, xorw, sltw, sltcw;
+
+not notg(notw, r2); // NOT: R1 = ~R2
+
+not nogt(notw2, r3);                  // for subtract; higher level sets cin to 1
+fa addg(addw, addcw, r2, r3, cin);    // ADD: R1 = R2 + R3
+fa subg(subw, subcw, r2, notw2, cin); // SUB: R1 = R2 - R3
+
+or org(orw, r2, r3);           // OR:  R1 = R2 | R3
+and andg(andw, r2, r3);        // AND: R1 = R2 & R3
+xor_custom xorg(xorw, r2, r3); // XOR: R1 = R2 ^ R3
+
+mux_8to1 opsel( .out(r1),
+					 .sel(op),
+					 .o0(r2),
+					 .o1(notw),
+					 .o2(addw),
+					 .o3(subw),
+					 .o4(orw),
+					 .o5(andw),
+					 .o6(xorw),
+					 .o7(subw)
+				);
+				
+mux_8to1 csel( .out(cout),
+					.sel(op),
+					.o0(1'b0), .o1(1'b0),
+					.o2(addcw),
+					.o3(subcw),
+					.o4(1'b0), .o5(1'b0),
+					.o6(1'b0),
+					.o7(subcw) 
+				);
+
+endmodule