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diff --git a/verilog/S1.v b/verilog/S1.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    20:03:20 10/21/2012 
+// Design Name: 
+// Module Name:    Stage1 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Stage1(
+	type, // R or I type
+	alu_op, // which aluoption to take
+	r1sel, // which register to write to
+	r2sel, // the value of a selected register
+	r3sel, // the value of another seclected register
+	imm, // the value if it's an immediate
+	
+	instr, // the instruction to run
+	clk, // clock input
+	reset // rest everything
+);
+parameter BITS = 32; // width of reg select
+parameter RSELW = 5; // N-BIT Values
+parameter DEPTH = 3; // pipeline depth
+
+output type;
+output [2:0] alu_op; // always 3 bits
+output [RSELW-1:0] r1sel;
+output [RSELW-1:0] r2sel, r3sel;
+output [15:0] imm; // 32 bit opcode -> 16 bit immediate
+input [31:0] instr; // 32 bit opcode
+input clk;
+input reset;
+
+
+wire [31:0] iw;
+nbit_reg #(32) ireg(
+	.nD(instr),
+	.nQ(iw),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+instruction_decode dec(
+	.op_type(type),
+	.alu_op(alu_op),
+	.r1sel(r1sel),
+	.r2sel(r2sel),
+	.r3sel(r3sel),
+	.immediate(imm),
+	.instruction(iw)
+);
+
+
+endmodule