1 files changed, 116 insertions, 0 deletions
diff --git a/verilog/S2.v b/verilog/S2.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    23:49:19 10/21/2012 
+// Design Name: 
+// Module Name:    Stage2 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Stage2(
+	operand1,
+	operand2,
+	wout,
+	alu_op_out,
+	op_type, // R or I instruction
+	alu_op_in,
+	data1,
+	data2,
+	immediate,
+	win,
+	clk,
+	reset
+);
+
+parameter BITS=32;
+parameter RSELW=5;
+
+output [BITS-1:0] operand1, operand2;
+output [2:0] alu_op_out;
+output [RSELW-1:0] wout;
+input op_type;
+input [2:0] alu_op_in;
+input [BITS-1:0] data1, data2;
+input [15:0] immediate;
+input [RSELW-1:0] win;
+input clk, reset;
+
+
+wire [BITS-1:16] sign_extend = immediate[15] ? ~0 : 0;
+wire [BITS-1:0] immw;
+assign immw = {sign_extend,immediate};
+
+wire [BITS-1:0] op2w;
+
+nbit_reg #(BITS) o1reg(
+	.nD(data1),
+	.nQ(operand1),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+wire [BITS-1:0] d2wo, imw0;
+nbit_reg #(BITS) o2reg(
+	.nD(data2),
+	.nQ(d2wo),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+nbit_reg #(BITS) imreg(
+	.nD(immw),
+	.nQ(imw0),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+nbit_reg #(3) opreg(
+	.nD(alu_op_in),
+	.nQ(alu_op_out),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+nbit_reg #(RSELW) wreg(
+	.nD(win),
+	.nQ(wout),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+nbit_reg #(1) treg(
+	.nD(op_type),
+	.nQ(op_typew),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+generate 
+genvar i;
+for (i = 0; i < BITS; i = i + 1) begin:mux
+	nbit_mux#(1) mux(
+		.MuxIn({imw0[i],d2wo[i]}),
+		.MuxOut(operand2[i]),
+		.MuxSel(op_typew)
+	);
+end
+endgenerate
+
+endmodule