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diff --git a/verilog/alu.v b/verilog/alu.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    19:56:04 10/03/2012 
+// Design Name: 
+// Module Name:    alu 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module alu( r1, r2, r3, aluop);
+
+parameter BITS = 32;
+
+input [BITS-1:0] r2, r3;
+input [2:0] aluop;
+output [BITS-1:0] r1;
+
+wire cinw;
+wire carries [0:BITS-1];
+wire [BITS-1:0] r1out;
+cin_choice cin(cinw, aluop);
+
+alu_slice1bit alu_slice_init(
+				.r1(r1out[0]), 
+				.cout(carries[0]),
+				.r2(r2[0]),
+				.r3(r3[0]),
+				.cin(cinw),
+				.op(aluop)
+			);
+
+generate
+	genvar i;
+	for (i = 1; i < BITS; i = i + 1) begin:aluslice
+		alu_slice1bit alu_slice(
+					.r1(r1out[i]), 
+					.cout(carries[i]),
+					.r2(r2[i]),
+					.r3(r3[i]),
+					.cin(carries[i-1]),
+					.op(aluop)
+				);
+	end
+endgenerate
+
+wire sltw;
+slt sltg(sltw, r2[BITS-1], r3[BITS-1], r1out[BITS-1], carries[BITS-1]);
+
+
+wire doslt;
+wire [BITS-2:0] s;
+assign s = 0;
+and a(doslt, aluop[2], aluop[1], aluop[0]);
+mux_2to1_nbit #(BITS) m(r1, doslt, r1out, {s,sltw});
+
+endmodule