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Diffstat (limited to 'verilog/cin_choice.v')
-rwxr-xr-x | verilog/cin_choice.v | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/verilog/cin_choice.v b/verilog/cin_choice.v new file mode 100755 index 0000000..e6ab92b --- /dev/null +++ b/verilog/cin_choice.v @@ -0,0 +1,39 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12:44:24 10/04/2012 +// Design Name: +// Module Name: cin_choice +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module cin_choice( + output cin, + input [2:0] op + ); + +// we only want non-zero cin if we're subtracting. +// Subtraction is used in both sub and slt, so we have two cases +// 011 and 111. output is 1 for these and 0 for others + +// This is equivalent to a'bc + abc (where a, b, c are bits in op) + +wire notw, subw, sltw; +not n1(notw, op[2]); + +and sub_choose(subw, notw, op[1], op[0]); +and slt_choose(sltw, op[2], op[1], op[0]); +or choose(cin, sltw, subw); + +endmodule |