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diff --git a/verilog/mux_8to1.v b/verilog/mux_8to1.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    22:40:54 10/04/2012 
+// Design Name: 
+// Module Name:    mux_8to1 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mux_8to1(
+			output out,
+			input [2:0] sel,
+			input o0,
+			input o1,
+			input o2,
+			input o3,
+			input o4,
+			input o5,
+			input o6,
+			input o7
+    );
+
+wire sn0, sn1, sn2;
+not n1(sn0, sel[0]);
+not n2(sn1, sel[1]);
+not n3(sn2, sel[2]);
+wire a0, a1, a2, a3, a4, a5, a6, a7;
+
+// 111 corresponds to ag0
+
+and ag0(a0, sn2, sn1, sn0, o0);
+and ag1(a1, sn2, sn1, sel[0], o1);
+and ag2(a2, sn2, sel[1], sn0, o2);
+and ag3(a3, sn2, sel[1], sel[0], o3);
+
+and ag4(a4, sel[2], sn1, sn0, o4);
+and ag5(a5, sel[2], sn1, sel[0], o5);
+and ag6(a6, sel[2], sel[1], sn0, o6);
+and ag7(a7, sel[2], sel[1], sel[0], o7);
+
+or(out, a0, a1, a2, a3, a4, a5, a6, a7);
+
+
+endmodule