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diff --git a/verilog/overflow.v b/verilog/overflow.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    22:17:44 10/04/2012 
+// Design Name: 
+// Module Name:    overflow 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module overflow(
+    output ovf,
+    input r2,
+    input r3,
+	 input r1,
+    input carry
+    );
+
+// overflow occurs (in subtraction) only when the signs are different
+// for r2 - r3
+// if r2 is negative, and r3 is potitive, will overflow to positive
+// so cout would be 0
+// if r2 is positive and r3 is negative, will overflow to negative
+// so cout would be 1
+
+
+wire r2pos, r3pos, r1pos, nsout;
+wire aw1, aw2;
+
+not n1(r2pos, r2); // positive if not r2
+not n2(r3pos, r3); // "" "" "" r3
+not n3(r1pos, r1);
+not n4(nsout, carry); 
+
+and a1(aw1, r2, r3pos, r1pos,carry); // negative - positive = bigger negative and can overflow
+and a2(aw2, r2pos, r3, r1, nsout); // pos - neg = pos
+
+or o1(ovf, aw1, aw2);
+
+endmodule