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-rw-r--r--.gitignore2
-rw-r--r--ec413-lab6.pdfbin0 -> 124388 bytes
-rw-r--r--fsm.v51
-rw-r--r--params.v22
-rw-r--r--test_fsm.v42
5 files changed, 117 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore
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--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+*.swp
+.DS_Store
diff --git a/ec413-lab6.pdf b/ec413-lab6.pdf
new file mode 100644
index 0000000..d791ddf
--- /dev/null
+++ b/ec413-lab6.pdf
Binary files differ
diff --git a/fsm.v b/fsm.v
new file mode 100644
index 0000000..be94fc7
--- /dev/null
+++ b/fsm.v
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+`timescale 1ns / 1ps
+// FSM module
+//
+// drives the data path through multiple cycles
+
+module fsm(
+ output [3:0] state,
+ input [2:0] instrtype,
+ input rst,
+ input clk
+);
+
+`include "params.v"
+
+reg [3:0] state, nextstate;
+
+always @(*) begin
+ if (rst) begin
+ nextstate = FETCH;
+ end else begin
+ case (state)
+ FETCH: nextstate = DECODE;
+ DECODE: if (instrtype == IINSTR || instrtype == RINSTR)
+ nextstate = ALUOP;
+ else if (instrtype == MEMRINSTR || instrtype == MEMWINSTR)
+ nextstate = MEMCALC;
+ else if (instrtype == BRINSTR)
+ nextstate = BRANCH;
+ else if (instrtype == JINSTR)
+ nextstate = JUMP;
+ MEMCALC: if (instrtype == MEMWINSTR)
+ nextstate = MEMWRITE;
+ else if (instrtype == MEMRINSTR)
+ nextstate = MEMREAD;
+ MEMWRITE: nextstate = FETCH;
+ MEMREAD: nextstate = MEMSTORE;
+ MEMSTORE: nextstate <= FETCH;
+ ALUOP: nextstate = ALUSTORE;
+ ALUSTORE: nextstate = FETCH;
+ BRANCH: nextstate = FETCH;
+ JUMP: nextstate = FETCH;
+ endcase
+ end
+end
+
+always @(posedge clk or posedge rst) begin
+ state <= rst ? FETCH : nextstate;
+end
+
+endmodule
+
diff --git a/params.v b/params.v
new file mode 100644
index 0000000..1ae2339
--- /dev/null
+++ b/params.v
@@ -0,0 +1,22 @@
+
+// These are all the types of instructions we have,
+// each represents a path through the FSM
+parameter RINSTR = 3'd0; // R-type ALU instruction
+parameter IINSTR = 3'd1; // I-type ALU instruction
+parameter MEMRINSTR = 3'd2; // memory read
+parameter MEMWINSTR = 3'd3; // memory write
+parameter BRINSTR = 3'd4; // branch
+parameter JINSTR = 3'd5; //jump
+
+// and these are nice names for the various states
+parameter FETCH = 4'd0;
+parameter DECODE = 4'd1;
+parameter MEMCALC = 4'd2;
+parameter MEMWRITE = 4'd3;
+parameter MEMREAD = 4'd4;
+parameter MEMSTORE = 4'd5;
+parameter ALUOP = 4'd6;
+parameter ALUSTORE = 4'd7;
+parameter BRANCH = 4'd8;
+parameter JUMP = 4'd9;
+
diff --git a/test_fsm.v b/test_fsm.v
new file mode 100644
index 0000000..0f86ef4
--- /dev/null
+++ b/test_fsm.v
@@ -0,0 +1,42 @@
+`timescale 1ns / 1ps
+
+module test_fsm;
+
+`include "params.v"
+
+reg clk, rst;
+reg [2:0] itype;
+wire [3:0] state;
+
+fsm uut(
+ .state(state),
+ .instrtype(itype),
+ .clk(clk),
+ .rst(rst)
+);
+
+initial begin
+ //$dumpfile("test_fsm.vcd");
+ //$dumpvars(0, uut);
+ clk = 0; rst = 0; itype = RINSTR;
+ #100;
+ #19; rst = 1; #1; rst = 0;
+ itype = RINSTR;
+ #19; rst = 1; #1; rst = 0;
+ itype = MEMRINSTR;
+ #19; rst = 1; #1; rst = 0;
+ itype = MEMWINSTR;
+ #19; rst = 1; #1; rst = 0;
+ itype = BRINSTR;
+ #19; rst = 1; #1; rst = 0;
+ itype = JINSTR;
+ #19; rst = 1; #1; rst = 0;
+ #100;
+ //$finish;
+end
+
+always begin
+ clk = ~clk; #1;
+end
+
+endmodule