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authorMichael Abed <michaelabed@gmail.com>2012-02-17 12:08:05 -0500
committerMichael Abed <michaelabed@gmail.com>2012-02-17 12:08:05 -0500
commit70b77304f37d9681aa3bfa0eb57df0bcfd1aef81 (patch)
tree48ab397b4072275dbc5a6b2f92a54d3c79e1fdea
parent57738e75e221fe61a8f87270b430c0f1c0b8ead5 (diff)
downloadec311-lab1-70b77304f37d9681aa3bfa0eb57df0bcfd1aef81.tar.gz
ec311-lab1-70b77304f37d9681aa3bfa0eb57df0bcfd1aef81.tar.bz2
ec311-lab1-70b77304f37d9681aa3bfa0eb57df0bcfd1aef81.zip
make it workHEADmaster
Diffstat
-rwxr-xr-xALU.bld4
-rwxr-xr-xALU.cmd_log67
-rwxr-xr-xALU.jhd18
-rwxr-xr-xALU.ncd2
-rwxr-xr-xALU.ngc2
-rwxr-xr-xALU.ngd2
-rwxr-xr-xALU.ngr2
-rwxr-xr-xALU.pad10
-rwxr-xr-xALU.par12
-rwxr-xr-xALU.pcf8
-rwxr-xr-xALU.sch930
-rwxr-xr-xALU.schlog0
-rwxr-xr-xALU.sym63
-rwxr-xr-xALU.syr169
-rwxr-xr-xALU.twr100
-rwxr-xr-xALU.twx4
-rwxr-xr-xALU.ucf7
-rwxr-xr-xALU.unroutes2
-rwxr-xr-xALU.vf258
-rwxr-xr-xALU_bitgen.xwbt6
-rw-r--r--ALU_envsettings.html100
-rwxr-xr-xALU_guide.ncd2
-rwxr-xr-xALU_map.map40
-rwxr-xr-xALU_map.mrp8
-rwxr-xr-xALU_map.ncd2
-rwxr-xr-xALU_map.ngm2
-rwxr-xr-xALU_map.xrpt14
-rwxr-xr-xALU_ngdbuild.xrpt46
-rwxr-xr-xALU_pad.csv10
-rwxr-xr-xALU_pad.txt10
-rwxr-xr-xALU_par.xrpt42
-rwxr-xr-xALU_summary.html62
-rwxr-xr-xALU_summary.xml2
-rwxr-xr-xALU_usage.xml256
-rwxr-xr-xALU_xst.xrpt32
-rwxr-xr-xDivide.cmd_log9
-rwxr-xr-xDivide.jhd18
-rwxr-xr-xDivide.sch339
-rwxr-xr-xDivide.schlog0
-rwxr-xr-xDivide.sym66
-rwxr-xr-xDivide.vf72
-rwxr-xr-xDivide_0.cmd_log7
-rwxr-xr-xDivide_0.jhd2
-rwxr-xr-xDivide_0.sch337
-rwxr-xr-xDivide_0.sym48
-rwxr-xr-xDivide_0.vf14
-rwxr-xr-xDivide_1.cmd_log1
-rwxr-xr-xDivide_1.jhd2
-rwxr-xr-xDivide_1.sch416
-rwxr-xr-xDivide_1.sym48
-rwxr-xr-xDivide_1.vf4
-rwxr-xr-xDivide_2.cmd_log2
-rwxr-xr-xDivide_2.jhd2
-rwxr-xr-xDivide_2.sch202
-rwxr-xr-xDivide_2.sym48
-rwxr-xr-xDivide_2.vf39
-rwxr-xr-xDivide_3.cmd_log2
-rwxr-xr-xDivide_3.sch79
-rwxr-xr-xDivide_3.sym48
-rwxr-xr-xDivide_3.vf21
-rwxr-xr-xModulo.cmd_log5
-rwxr-xr-xModulo.sch6
-rwxr-xr-xModulo.schlog0
-rwxr-xr-xModulo.sym66
-rwxr-xr-xModulo.vf91
-rwxr-xr-xModulo_0.cmd_log4
-rwxr-xr-xModulo_0.sch174
-rwxr-xr-xModulo_0.sym48
-rwxr-xr-xModulo_0.vf41
-rwxr-xr-xModulo_1.cmd_log3
-rwxr-xr-xModulo_1.jhd2
-rwxr-xr-xModulo_1.sch593
-rwxr-xr-xModulo_1.sym48
-rwxr-xr-xModulo_1.vf54
-rwxr-xr-xModulo_3.cmd_log2
-rwxr-xr-xModulo_3.schlog2
-rwxr-xr-xModulo_3.sym48
-rwxr-xr-xModulo_3.vf4
-rwxr-xr-xNegate.cmd_log4
-rwxr-xr-xNegate.jhd18
-rwxr-xr-xNegate.sch338
-rwxr-xr-xNegate.schlog0
-rwxr-xr-xNegate.sym66
-rwxr-xr-xNegate.vf77
-rwxr-xr-xNegate_0.cmd_log2
-rwxr-xr-xNegate_0.sym48
-rwxr-xr-xNegate_0.vf4
-rwxr-xr-xNegate_1.cmd_log2
-rwxr-xr-xNegate_1.sym48
-rwxr-xr-xNegate_1.vf4
-rwxr-xr-xNegate_2.cmd_log4
-rwxr-xr-xNegate_2.jhd2
-rwxr-xr-xNegate_2.sch369
-rwxr-xr-xNegate_2.sym48
-rwxr-xr-xNegate_2.vf59
-rwxr-xr-xNegate_3.cmd_log2
-rwxr-xr-xNegate_3.jhd2
-rwxr-xr-xNegate_3.sch192
-rwxr-xr-xNegate_3.sym48
-rwxr-xr-xNegate_3.vf22
-rwxr-xr-x_ngo/netlist.lst2
-rwxr-xr-x_xmsgs/bitgen.xmsgs2
-rwxr-xr-x_xmsgs/map.xmsgs12
-rwxr-xr-x_xmsgs/par.xmsgs4
-rwxr-xr-x_xmsgs/pn_parser.xmsgs24
-rwxr-xr-x_xmsgs/trce.xmsgs6
-rwxr-xr-xalu.bgn2
-rwxr-xr-xalu.bitbin464285 -> 464285 bytes
-rwxr-xr-xalu.drc2
-rwxr-xr-xalu.msd2
-rwxr-xr-xalu.mskbin464285 -> 464285 bytes
-rwxr-xr-xalu.rbbbin464117 -> 464117 bytes
-rwxr-xr-xalu.rbd636
-rwxr-xr-ximpact_impact.xwbt6
-rwxr-xr-xiseconfig/ALU.xreport8
-rwxr-xr-xiseconfig/lab1.projectmgr156
-rwxr-xr-xlab1.gise43
-rwxr-xr-xlab1.xise5
-rwxr-xr-xpa.fromHdl.tcl2
-rwxr-xr-xpa.fromNetlist.tcl6
-rwxr-xr-xpar_usage_statistics.html18
-rwxr-xr-xplanAhead.ngc2edif.log88
-rwxr-xr-xplanAhead_run_1/lab1.data/cache/ALU_ngc_c04f956c.edif2404
-rwxr-xr-xplanAhead_run_1/lab1.data/constrs_1/designprops.xml29
-rwxr-xr-xplanAhead_run_1/lab1.data/constrs_1/fileset.xml20
-rwxr-xr-xplanAhead_run_1/lab1.data/constrs_1/usercols.xml4
-rwxr-xr-xplanAhead_run_1/lab1.data/runs/impl_1.psg18
-rwxr-xr-xplanAhead_run_1/lab1.data/runs/runs.xml5
-rwxr-xr-xplanAhead_run_1/lab1.data/sources_1/chipscope.xml6
-rwxr-xr-xplanAhead_run_1/lab1.data/sources_1/fileset.xml156
-rwxr-xr-xplanAhead_run_1/lab1.data/sources_1/ports.xml24
-rwxr-xr-xplanAhead_run_1/lab1.ppr1
-rwxr-xr-xplanAhead_run_1/planAhead.jou22
-rwxr-xr-xplanAhead_run_1/planAhead.log139
-rwxr-xr-xplanAhead_run_1/planAhead_run.log112
-rwxr-xr-xplanAhead_run_2/lab1.data/cache/ALU_ngc_c04f956c.edif2476
-rwxr-xr-xplanAhead_run_2/lab1.data/constrs_1/fileset.xml25
-rwxr-xr-xplanAhead_run_2/lab1.data/runs/impl_1.psg18
-rwxr-xr-xplanAhead_run_2/lab1.data/runs/runs.xml5
-rwxr-xr-xplanAhead_run_2/lab1.data/sources_1/fileset.xml29
-rwxr-xr-xplanAhead_run_2/lab1.data/wt/webtalk_pa.xml26
-rwxr-xr-xplanAhead_run_2/lab1.ppr14
-rwxr-xr-xplanAhead_run_2/planAhead.jou18
-rwxr-xr-xplanAhead_run_2/planAhead.log198
-rwxr-xr-xplanAhead_run_2/planAhead_run.log196
-rwxr-xr-xsch2HdlBatchFile3
-rwxr-xr-xsev_seg_disp.vf4
-rwxr-xr-xusage_statistics_webtalk.html18
-rwxr-xr-xwebtalk.log4
-rwxr-xr-xwebtalk_impact.xml26
-rwxr-xr-xwebtalk_pn.xml9
-rwxr-xr-xxlnx_auto_0_xdb/cst.xbcdbin1631 -> 1549 bytes
-rwxr-xr-xxst/work/work.sdblbin131898 -> 139419 bytes
-rwxr-xr-xxst/work/work.sdbxbin1035 -> 1035 bytes
154 files changed, 9769 insertions, 3934 deletions
diff --git a/ALU.bld b/ALU.bld
index 6186a2d..2e3d732 100755
--- a/ALU.bld
+++ b/ALU.bld
@@ -5,7 +5,7 @@ Command Line: C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 ALU.ngc
ALU.ngd
-Reading NGO file "X:/My Documents/ec311/lab1/ALU.ngc" ...
+Reading NGO file "X:/My Documents/ec311/ec311-lab1/ALU.ngc" ...
Gathering constraint information from source properties...
Done.
@@ -27,7 +27,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
-Total memory usage is 156564 kilobytes
+Total memory usage is 154784 kilobytes
Writing NGD file "ALU.ngd" ...
Total REAL time to NGDBUILD completion: 4 sec
diff --git a/ALU.cmd_log b/ALU.cmd_log
index de0ed5a..4963564 100755
--- a/ALU.cmd_log
+++ b/ALU.cmd_log
@@ -8,3 +8,70 @@ map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -re
par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf
bitgen -intstyle ise -f ALU.ut ALU.ncd
+sch2sym -intstyle ise -family spartan6 -w -refsym ALU {X:/My Documents/ec311/ec311-lab1/ALU.sch} {X:/My Documents/ec311/ec311-lab1/ALU.sym}
+xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd
+map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf
+par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf
+bitgen -intstyle ise -f ALU.ut ALU.ncd
+sch2sym -intstyle ise -family spartan6 -w -refsym ALU {X:/My Documents/ec311/ec311-lab1/ALU.sch} {X:/My Documents/ec311/ec311-lab1/ALU.sym}
+xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd
+map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf
+sch2sym -intstyle ise -family spartan6 -w -refsym ALU {X:/My Documents/ec311/ec311-lab1/ALU.sch} {X:/My Documents/ec311/ec311-lab1/ALU.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym ALU {X:/My Documents/ec311/ec311-lab1/ALU.sch} {X:/My Documents/ec311/ec311-lab1/ALU.sym}
+xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd
+map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf
+par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf
+bitgen -intstyle ise -f ALU.ut ALU.ncd
+xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd
+map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf
+par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf
+bitgen -intstyle ise -f ALU.ut ALU.ncd
+xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd
+map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf
+par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf
+bitgen -intstyle ise -f ALU.ut ALU.ncd
+xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd
+map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf
+par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf
+bitgen -intstyle ise -f ALU.ut ALU.ncd
+xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd
+map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf
+par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf
+bitgen -intstyle ise -f ALU.ut ALU.ncd
+xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd
+map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf
+par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf
+bitgen -intstyle ise -f ALU.ut ALU.ncd
+xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd
+map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf
+par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf
+bitgen -intstyle ise -f ALU.ut ALU.ncd
+xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd
+map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf
+par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf
+bitgen -intstyle ise -f ALU.ut ALU.ncd
+xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd
+map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf
+par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf
+bitgen -intstyle ise -f ALU.ut ALU.ncd
diff --git a/ALU.jhd b/ALU.jhd
index 7beadb5..1b290b6 100755
--- a/ALU.jhd
+++ b/ALU.jhd
@@ -1,9 +1,9 @@
-MODULE ALU
- SUBMODULE Divide
- INSTANCE XLXI_1
- SUBMODULE Modulo
- INSTANCE XLXI_2
- SUBMODULE Negate
- INSTANCE XLXI_3
- SUBMODULE sev_seg_disp
- INSTANCE XLXI_9
+MODULE ALU
+ SUBMODULE Divide
+ INSTANCE XLXI_1
+ SUBMODULE Modulo
+ INSTANCE XLXI_2
+ SUBMODULE Negate
+ INSTANCE XLXI_3
+ SUBMODULE sev_seg_disp
+ INSTANCE XLXI_9
diff --git a/ALU.ncd b/ALU.ncd
index be0b713..ca10a31 100755
--- a/ALU.ncd
+++ b/ALU.ncd
@@ -1,3 +1,3 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
-###6396:XlxV32DM 3fff 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\ No newline at end of file
diff --git a/ALU.ngc b/ALU.ngc
index 3c55a01..294b6ac 100755
--- a/ALU.ngc
+++ b/ALU.ngc
@@ -1,3 +1,3 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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diff --git a/ALU.ngd b/ALU.ngd
index 169b26d..1147e66 100755
--- a/ALU.ngd
+++ b/ALU.ngd
@@ -1,3 +1,3 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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diff --git a/ALU.ngr b/ALU.ngr
index 6cf27d1..f271a7a 100755
--- a/ALU.ngr
+++ b/ALU.ngr
@@ -1,3 +1,3 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/ALU.pad b/ALU.pad
index 5481d6b..04e328a 100755
--- a/ALU.pad
+++ b/ALU.pad
@@ -1,7 +1,7 @@
Release 13.3 - par O.76xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
-Wed Feb 15 15:16:15 2012
+Thu Feb 16 19:53:19 2012
# NOTE: This file is designed to be imported into a spreadsheet program
@@ -26,7 +26,7 @@ A4||IOBS|IO_L5N_0|UNUSED||0|||||||||
A5||IOBS|IO_L6N_0|UNUSED||0|||||||||
A6||IOBS|IO_L8N_VREF_0|UNUSED||0|||||||||
A7||IOBS|IO_L10N_0|UNUSED||0|||||||||
-A8|C|IOB|IO_L33N_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE|
+A8||IOBS|IO_L33N_0|UNUSED||0|||||||||
A9||IOBS|IO_L35N_GCLK16_0|UNUSED||0|||||||||
A10||IOBS|IO_L37N_GCLK12_0|UNUSED||0|||||||||
A11||IOBS|IO_L39N_0|UNUSED||0|||||||||
@@ -58,12 +58,12 @@ B18|||TMS||||||||||||
C1||IOBS|IO_L83N_VREF_3|UNUSED||3|||||||||
C2||IOBM|IO_L83P_3|UNUSED||3|||||||||
C3|||GND||||||||||||
-C4||IOBS|IO_L1N_VREF_0|UNUSED||0|||||||||
+C4|A|IOB|IO_L1N_VREF_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE|
C5||IOBM|IO_L6P_0|UNUSED||0|||||||||
C6||IOBS|IO_L3N_0|UNUSED||0|||||||||
C7||IOBM|IO_L10P_0|UNUSED||0|||||||||
C8||IOBS|IO_L11N_0|UNUSED||0|||||||||
-C9|A|IOB|IO_L34N_GCLK18_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE|
+C9|D|IOB|IO_L34N_GCLK18_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE|
C10||IOBM|IO_L37P_GCLK13_0|UNUSED||0|||||||||
C11||IOBS|IO_L36N_GCLK14_0|UNUSED||0|||||||||
C12||IOBS|IO_L47N_0|UNUSED||0|||||||||
@@ -81,7 +81,7 @@ D5|||GND||||||||||||
D6||IOBM|IO_L3P_0|UNUSED||0|||||||||
D7|||VCCO_0|||0|||||any******||||
D8||IOBM|IO_L11P_0|UNUSED||0|||||||||
-D9|D|IOB|IO_L34P_GCLK19_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE|
+D9|C|IOB|IO_L34P_GCLK19_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE|
D10|||GND||||||||||||
D11||IOBM|IO_L36P_GCLK15_0|UNUSED||0|||||||||
D12||IOBM|IO_L47P_0|UNUSED||0|||||||||
diff --git a/ALU.par b/ALU.par
index 4b07d80..3adecd5 100755
--- a/ALU.par
+++ b/ALU.par
@@ -1,7 +1,7 @@
Release 13.3 par O.76xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
-ECE-PHO115-09:: Wed Feb 15 15:16:04 2012
+ECE-PHO115-08:: Thu Feb 16 19:53:08 2012
par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf
@@ -36,7 +36,7 @@ Slice Logic Utilization:
Number used as Memory: 0 out of 2,176 0%
Slice Logic Distribution:
- Number of occupied Slices: 5 out of 2,278 1%
+ Number of occupied Slices: 6 out of 2,278 1%
Nummber of MUXCYs used: 0 out of 4,556 0%
Number of LUT Flip Flop pairs used: 13
Number with an unused Flip Flop: 13 out of 13 100%
@@ -92,9 +92,9 @@ Phase 1 : 67 unrouted; REAL time: 5 secs
Phase 2 : 67 unrouted; REAL time: 5 secs
-Phase 3 : 49 unrouted; REAL time: 6 secs
+Phase 3 : 25 unrouted; REAL time: 6 secs
-Phase 4 : 49 unrouted; (Par is working to improve performance) REAL time: 7 secs
+Phase 4 : 25 unrouted; (Par is working to improve performance) REAL time: 7 secs
Updating file: ALU.ncd with current fully routed design.
@@ -129,10 +129,10 @@ Generating Pad Report.
All signals are completely routed.
-Total REAL time to PAR completion: 19 secs
+Total REAL time to PAR completion: 16 secs
Total CPU time to PAR completion: 7 secs
-Peak Memory Usage: 307 MB
+Peak Memory Usage: 308 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
diff --git a/ALU.pcf b/ALU.pcf
index 174c14a..4c41ef8 100755
--- a/ALU.pcf
+++ b/ALU.pcf
@@ -1,5 +1,5 @@
//! **************************************************************************
-// Written by: Map O.76xd on Wed Feb 15 15:15:59 2012
+// Written by: Map O.76xd on Thu Feb 16 19:53:03 2012
//! **************************************************************************
SCHEMATIC START;
@@ -14,10 +14,10 @@ COMP "AN0" LOCATE = SITE "N16" LEVEL 1;
COMP "AN1" LOCATE = SITE "N15" LEVEL 1;
COMP "AN2" LOCATE = SITE "P18" LEVEL 1;
COMP "AN3" LOCATE = SITE "P17" LEVEL 1;
-COMP "A" LOCATE = SITE "C9" LEVEL 1;
+COMP "A" LOCATE = SITE "C4" LEVEL 1;
COMP "B" LOCATE = SITE "B8" LEVEL 1;
-COMP "C" LOCATE = SITE "A8" LEVEL 1;
-COMP "D" LOCATE = SITE "D9" LEVEL 1;
+COMP "C" LOCATE = SITE "D9" LEVEL 1;
+COMP "D" LOCATE = SITE "C9" LEVEL 1;
COMP "g_out" LOCATE = SITE "L14" LEVEL 1;
COMP "a_out" LOCATE = SITE "T17" LEVEL 1;
COMP "b_out" LOCATE = SITE "T18" LEVEL 1;
diff --git a/ALU.sch b/ALU.sch
index 78bc8e1..abd63bb 100755
--- a/ALU.sch
+++ b/ALU.sch
@@ -1,466 +1,466 @@
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+<drawing version="7">
+ <attr value="spartan6" name="DeviceFamilyName">
+ <trait delete="all:0" />
+ <trait editname="all:0" />
+ <trait edittrait="all:0" />
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+ <signal name="A" />
+ <signal name="B" />
+ <signal name="C" />
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+ <signal name="S1" />
+ <signal name="S0" />
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+ <signal name="XLXN_23" />
+ <signal name="XLXN_24" />
+ <signal name="XLXN_25" />
+ <signal name="XLXN_33" />
+ <signal name="XLXN_34" />
+ <signal name="XLXN_35" />
+ <signal name="XLXN_36" />
+ <signal name="XLXN_37" />
+ <signal name="XLXN_38" />
+ <signal name="XLXN_39" />
+ <signal name="XLXN_41" />
+ <signal name="a_out" />
+ <signal name="b_out" />
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+ <signal name="d_out" />
+ <signal name="e_out" />
+ <signal name="f_out" />
+ <signal name="g_out" />
+ <signal name="sign" />
+ <signal name="AN0" />
+ <signal name="AN1" />
+ <signal name="AN2" />
+ <signal name="AN3" />
+ <signal name="D" />
+ <signal name="XLXN_42" />
+ <signal name="XLXN_43" />
+ <signal name="XLXN_44" />
+ <signal name="XLXN_45" />
+ <port polarity="Input" name="A" />
+ <port polarity="Input" name="B" />
+ <port polarity="Input" name="C" />
+ <port polarity="Input" name="S1" />
+ <port polarity="Input" name="S0" />
+ <port polarity="Output" name="a_out" />
+ <port polarity="Output" name="b_out" />
+ <port polarity="Output" name="c_out" />
+ <port polarity="Output" name="d_out" />
+ <port polarity="Output" name="e_out" />
+ <port polarity="Output" name="f_out" />
+ <port polarity="Output" name="g_out" />
+ <port polarity="Output" name="sign" />
+ <port polarity="Output" name="AN0" />
+ <port polarity="Output" name="AN1" />
+ <port polarity="Output" name="AN2" />
+ <port polarity="Output" name="AN3" />
+ <port polarity="Input" name="D" />
+ <blockdef name="Divide">
+ <timestamp>2012-2-17T0:27:58</timestamp>
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+ </blockdef>
+ <blockdef name="Modulo">
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+ <rect width="256" x="64" y="-256" height="256" />
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+ <line x2="384" y1="-32" y2="-32" x1="320" />
+ </blockdef>
+ <blockdef name="Negate">
+ <timestamp>2012-2-16T23:54:10</timestamp>
+ <rect width="256" x="64" y="-256" height="256" />
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+ </blockdef>
+ <blockdef name="m4_1e">
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+ <blockdef name="vcc">
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+ </blockdef>
+ <blockdef name="sev_seg_disp">
+ <timestamp>2012-2-14T0:35:26</timestamp>
+ <rect width="256" x="64" y="-768" height="768" />
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+ <block symbolname="Divide" name="XLXI_1">
+ <blockpin signalname="A" name="b3" />
+ <blockpin signalname="D" name="b0" />
+ <blockpin signalname="C" name="b1" />
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+ <blockpin signalname="XLXN_34" name="out2" />
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+ <blockpin signalname="C" name="b1" />
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+ <blockpin signalname="XLXN_38" name="out1" />
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+ <blockpin signalname="S1" name="S1" />
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+ <blockpin signalname="S1" name="S1" />
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+ <blockpin signalname="S1" name="S1" />
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+ <blockpin signalname="S1" name="S1" />
+ <blockpin signalname="XLXN_25" name="O" />
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+ <blockpin signalname="XLXN_12" name="P" />
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+ <blockpin signalname="AN3" name="AN3" />
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+ </branch>
+ <branch name="XLXN_25">
+ <wire x2="2432" y1="1840" y2="1840" x1="2176" />
+ <wire x2="2432" y1="1328" y2="1840" x1="2432" />
+ <wire x2="2656" y1="1328" y2="1328" x1="2432" />
+ </branch>
+ <branch name="XLXN_33">
+ <wire x2="1520" y1="832" y2="832" x1="1200" />
+ <wire x2="1520" y1="432" y2="832" x1="1520" />
+ <wire x2="1888" y1="432" y2="432" x1="1520" />
+ </branch>
+ <branch name="XLXN_34">
+ <wire x2="1504" y1="768" y2="768" x1="1200" />
+ <wire x2="1504" y1="768" y2="912" x1="1504" />
+ <wire x2="1888" y1="912" y2="912" x1="1504" />
+ </branch>
+ <branch name="XLXN_35">
+ <wire x2="1488" y1="704" y2="704" x1="1200" />
+ <wire x2="1488" y1="704" y2="1376" x1="1488" />
+ <wire x2="1872" y1="1376" y2="1376" x1="1488" />
+ </branch>
+ <branch name="XLXN_36">
+ <wire x2="1472" y1="640" y2="640" x1="1200" />
+ <wire x2="1472" y1="640" y2="1872" x1="1472" />
+ <wire x2="1856" y1="1872" y2="1872" x1="1472" />
+ </branch>
+ <branch name="XLXN_37">
+ <wire x2="1504" y1="1312" y2="1312" x1="1184" />
+ <wire x2="1504" y1="1312" y2="1936" x1="1504" />
+ <wire x2="1856" y1="1936" y2="1936" x1="1504" />
+ </branch>
+ <branch name="XLXN_38">
+ <wire x2="1200" y1="1248" y2="1248" x1="1184" />
+ <wire x2="1200" y1="1248" y2="1440" x1="1200" />
+ <wire x2="1872" y1="1440" y2="1440" x1="1200" />
+ </branch>
+ <branch name="XLXN_39">
+ <wire x2="1504" y1="1184" y2="1184" x1="1184" />
+ <wire x2="1504" y1="976" y2="1184" x1="1504" />
+ <wire x2="1888" y1="976" y2="976" x1="1504" />
+ </branch>
+ <branch name="XLXN_41">
+ <wire x2="1552" y1="1120" y2="1120" x1="1184" />
+ <wire x2="1552" y1="496" y2="1120" x1="1552" />
+ <wire x2="1888" y1="496" y2="496" x1="1552" />
+ </branch>
+ <branch name="a_out">
+ <wire x2="3072" y1="656" y2="656" x1="3040" />
+ </branch>
+ <iomarker fontsize="28" x="3072" y="656" name="a_out" orien="R0" />
+ <branch name="b_out">
+ <wire x2="3072" y1="720" y2="720" x1="3040" />
+ </branch>
+ <iomarker fontsize="28" x="3072" y="720" name="b_out" orien="R0" />
+ <branch name="c_out">
+ <wire x2="3072" y1="784" y2="784" x1="3040" />
+ </branch>
+ <iomarker fontsize="28" x="3072" y="784" name="c_out" orien="R0" />
+ <branch name="d_out">
+ <wire x2="3072" y1="848" y2="848" x1="3040" />
+ </branch>
+ <iomarker fontsize="28" x="3072" y="848" name="d_out" orien="R0" />
+ <branch name="e_out">
+ <wire x2="3072" y1="912" y2="912" x1="3040" />
+ </branch>
+ <iomarker fontsize="28" x="3072" y="912" name="e_out" orien="R0" />
+ <branch name="f_out">
+ <wire x2="3072" y1="976" y2="976" x1="3040" />
+ </branch>
+ <iomarker fontsize="28" x="3072" y="976" name="f_out" orien="R0" />
+ <branch name="g_out">
+ <wire x2="3072" y1="1040" y2="1040" x1="3040" />
+ </branch>
+ <iomarker fontsize="28" x="3072" y="1040" name="g_out" orien="R0" />
+ <branch name="sign">
+ <wire x2="3072" y1="1104" y2="1104" x1="3040" />
+ </branch>
+ <iomarker fontsize="28" x="3072" y="1104" name="sign" orien="R0" />
+ <branch name="AN0">
+ <wire x2="3072" y1="1168" y2="1168" x1="3040" />
+ </branch>
+ <iomarker fontsize="28" x="3072" y="1168" name="AN0" orien="R0" />
+ <branch name="AN1">
+ <wire x2="3072" y1="1232" y2="1232" x1="3040" />
+ </branch>
+ <iomarker fontsize="28" x="3072" y="1232" name="AN1" orien="R0" />
+ <branch name="AN2">
+ <wire x2="3072" y1="1296" y2="1296" x1="3040" />
+ </branch>
+ <iomarker fontsize="28" x="3072" y="1296" name="AN2" orien="R0" />
+ <branch name="AN3">
+ <wire x2="3072" y1="1360" y2="1360" x1="3040" />
+ </branch>
+ <iomarker fontsize="28" x="3072" y="1360" name="AN3" orien="R0" />
+ <branch name="D">
+ <wire x2="480" y1="480" y2="480" x1="240" />
+ <wire x2="480" y1="480" y2="704" x1="480" />
+ <wire x2="480" y1="704" y2="1120" x1="480" />
+ <wire x2="480" y1="1120" y2="1552" x1="480" />
+ <wire x2="800" y1="1552" y2="1552" x1="480" />
+ <wire x2="800" y1="1120" y2="1120" x1="480" />
+ <wire x2="816" y1="704" y2="704" x1="480" />
+ <wire x2="1216" y1="480" y2="480" x1="480" />
+ <wire x2="1216" y1="480" y2="1744" x1="1216" />
+ <wire x2="1856" y1="1744" y2="1744" x1="1216" />
+ </branch>
+ <branch name="XLXN_42">
+ <wire x2="1520" y1="1680" y2="1680" x1="1184" />
+ <wire x2="1520" y1="1680" y2="1808" x1="1520" />
+ <wire x2="1856" y1="1808" y2="1808" x1="1520" />
+ </branch>
+ <branch name="XLXN_43">
+ <wire x2="1520" y1="1616" y2="1616" x1="1184" />
+ <wire x2="1520" y1="1312" y2="1616" x1="1520" />
+ <wire x2="1872" y1="1312" y2="1312" x1="1520" />
+ </branch>
+ <branch name="XLXN_44">
+ <wire x2="1536" y1="1552" y2="1552" x1="1184" />
+ <wire x2="1536" y1="848" y2="1552" x1="1536" />
+ <wire x2="1888" y1="848" y2="848" x1="1536" />
+ </branch>
+ <branch name="XLXN_45">
+ <wire x2="1200" y1="1744" y2="1744" x1="1184" />
+ <wire x2="1200" y1="1696" y2="1744" x1="1200" />
+ <wire x2="1344" y1="1696" y2="1696" x1="1200" />
+ <wire x2="1344" y1="368" y2="1696" x1="1344" />
+ <wire x2="1888" y1="368" y2="368" x1="1344" />
+ </branch>
+ </sheet>
</drawing> \ No newline at end of file
diff --git a/ALU.schlog b/ALU.schlog
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/ALU.schlog
diff --git a/ALU.sym b/ALU.sym
new file mode 100755
index 0000000..3887c25
--- /dev/null
+++ b/ALU.sym
@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="ALU">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-16T23:42:30</timestamp>
+ <pin polarity="Input" x="0" y="-736" name="A" />
+ <pin polarity="Input" x="0" y="-608" name="B" />
+ <pin polarity="Input" x="0" y="-480" name="C" />
+ <pin polarity="Input" x="0" y="-352" name="D" />
+ <pin polarity="Input" x="0" y="-224" name="S1" />
+ <pin polarity="Input" x="0" y="-96" name="S0" />
+ <pin polarity="Output" x="384" y="-736" name="a_out" />
+ <pin polarity="Output" x="384" y="-672" name="b_out" />
+ <pin polarity="Output" x="384" y="-608" name="c_out" />
+ <pin polarity="Output" x="384" y="-544" name="d_out" />
+ <pin polarity="Output" x="384" y="-480" name="e_out" />
+ <pin polarity="Output" x="384" y="-416" name="f_out" />
+ <pin polarity="Output" x="384" y="-352" name="g_out" />
+ <pin polarity="Output" x="384" y="-288" name="sign" />
+ <pin polarity="Output" x="384" y="-224" name="AN0" />
+ <pin polarity="Output" x="384" y="-160" name="AN1" />
+ <pin polarity="Output" x="384" y="-96" name="AN2" />
+ <pin polarity="Output" x="384" y="-32" name="AN3" />
+ <graph>
+ <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-776" type="symbol" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-736" type="pin A" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-608" type="pin B" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-480" type="pin C" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin D" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin S1" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin S0" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-736" type="pin a_out" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-672" type="pin b_out" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-608" type="pin c_out" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-544" type="pin d_out" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-480" type="pin e_out" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-416" type="pin f_out" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-352" type="pin g_out" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-288" type="pin sign" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin AN0" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin AN1" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin AN2" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin AN3" />
+ <rect width="256" x="64" y="-768" height="768" />
+ <line x2="0" y1="-736" y2="-736" x1="64" />
+ <line x2="0" y1="-608" y2="-608" x1="64" />
+ <line x2="0" y1="-480" y2="-480" x1="64" />
+ <line x2="0" y1="-352" y2="-352" x1="64" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="384" y1="-736" y2="-736" x1="320" />
+ <line x2="384" y1="-672" y2="-672" x1="320" />
+ <line x2="384" y1="-608" y2="-608" x1="320" />
+ <line x2="384" y1="-544" y2="-544" x1="320" />
+ <line x2="384" y1="-480" y2="-480" x1="320" />
+ <line x2="384" y1="-416" y2="-416" x1="320" />
+ <line x2="384" y1="-352" y2="-352" x1="320" />
+ <line x2="384" y1="-288" y2="-288" x1="320" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ <line x2="384" y1="-160" y2="-160" x1="320" />
+ <line x2="384" y1="-96" y2="-96" x1="320" />
+ <line x2="384" y1="-32" y2="-32" x1="320" />
+ </graph>
+</symbol>
diff --git a/ALU.syr b/ALU.syr
index 35acf74..c498b8a 100755
--- a/ALU.syr
+++ b/ALU.syr
@@ -4,13 +4,13 @@ Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.12 secs
+Total CPU time to Xst completion: 0.11 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.13 secs
+Total CPU time to Xst completion: 0.11 secs
--> Reading design: ALU.prj
@@ -105,48 +105,48 @@ Slice Utilization Ratio Delta : 5
=========================================================================
* HDL Parsing *
=========================================================================
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_3.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_3.vf" into library work
Parsing module <Negate_3>.
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_2.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_2.vf" into library work
Parsing module <Negate_2>.
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_1.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_1.vf" into library work
Parsing module <Negate_1>.
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_0.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_0.vf" into library work
Parsing module <Negate_0>.
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo_3.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo_3.vf" into library work
Parsing module <Modulo_3>.
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo_1.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo_1.vf" into library work
Parsing module <Modulo_1>.
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo_0.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo_0.vf" into library work
Parsing module <Modulo_0>.
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_3.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_3.vf" into library work
Parsing module <Divide_3>.
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_2.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_2.vf" into library work
Parsing module <Divide_2>.
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_1.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_1.vf" into library work
Parsing module <Divide_1>.
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_0.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_0.vf" into library work
Parsing module <Divide_0>.
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\sev_seg_disp.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\sev_seg_disp.vf" into library work
Parsing module <sev_seg_disp>.
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate.vf" into library work
Parsing module <Negate_3_MUSER_Negate>.
Parsing module <Negate_1_MUSER_Negate>.
Parsing module <Negate_2_MUSER_Negate>.
Parsing module <Negate_0_MUSER_Negate>.
Parsing module <Negate>.
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo.vf" into library work
Parsing module <Modulo_0_MUSER_Modulo>.
Parsing module <Modulo_1_MUSER_Modulo>.
Parsing module <Modulo_3_MUSER_Modulo>.
Parsing module <Modulo>.
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide.vf" into library work
Parsing module <Divide_1_MUSER_Divide>.
Parsing module <Divide_2_MUSER_Divide>.
Parsing module <Divide_3_MUSER_Divide>.
Parsing module <Divide_0_MUSER_Divide>.
Parsing module <Divide>.
-Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\ALU.vf" into library work
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\ALU.vf" into library work
Parsing module <M4_1E_HXILINX_ALU>.
Parsing module <sev_seg_disp_MUSER_ALU>.
Parsing module <Negate_3_MUSER_ALU>.
@@ -187,28 +187,22 @@ Elaborating module <INV>.
Elaborating module <Divide_2_MUSER_ALU>.
-Elaborating module <AND3>.
-
Elaborating module <Divide_3_MUSER_ALU>.
-Elaborating module <NOR3>.
-
Elaborating module <Divide_0_MUSER_ALU>.
+Elaborating module <AND3>.
+
Elaborating module <Modulo_MUSER_ALU>.
Elaborating module <Modulo_3_MUSER_ALU>.
Elaborating module <Modulo_1_MUSER_ALU>.
-Elaborating module <NAND4>.
+Elaborating module <OR5>.
Elaborating module <Modulo_0_MUSER_ALU>.
-Elaborating module <XNOR2>.
-
-Elaborating module <NAND3>.
-
Elaborating module <Negate_MUSER_ALU>.
Elaborating module <Negate_0_MUSER_ALU>.
@@ -217,9 +211,9 @@ Elaborating module <Negate_1_MUSER_ALU>.
Elaborating module <Negate_2_MUSER_ALU>.
-Elaborating module <Negate_3_MUSER_ALU>.
+Elaborating module <OR4>.
-Elaborating module <NAND2>.
+Elaborating module <Negate_3_MUSER_ALU>.
Elaborating module <M4_1E_HXILINX_ALU>.
@@ -231,9 +225,7 @@ Elaborating module <BUF>.
Elaborating module <GND>.
-Elaborating module <OR5>.
-
-Elaborating module <OR4>.
+Elaborating module <XNOR2>.
Elaborating module <XOR2>.
@@ -242,7 +234,7 @@ Elaborating module <XOR2>.
=========================================================================
Synthesizing Unit <ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
Set property "HU_SET = XLXI_4_0" for instance <XLXI_4>.
Set property "HU_SET = XLXI_5_1" for instance <XLXI_5>.
Set property "HU_SET = XLXI_6_2" for instance <XLXI_6>.
@@ -252,100 +244,100 @@ Synthesizing Unit <ALU>.
Unit <ALU> synthesized.
Synthesizing Unit <Divide_MUSER_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
Summary:
no macro.
Unit <Divide_MUSER_ALU> synthesized.
Synthesizing Unit <Divide_1_MUSER_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
Summary:
no macro.
Unit <Divide_1_MUSER_ALU> synthesized.
Synthesizing Unit <Divide_2_MUSER_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
Summary:
no macro.
Unit <Divide_2_MUSER_ALU> synthesized.
Synthesizing Unit <Divide_3_MUSER_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
Summary:
no macro.
Unit <Divide_3_MUSER_ALU> synthesized.
Synthesizing Unit <Divide_0_MUSER_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
WARNING:Xst:647 - Input <b2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Summary:
no macro.
Unit <Divide_0_MUSER_ALU> synthesized.
Synthesizing Unit <Modulo_MUSER_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
Summary:
no macro.
Unit <Modulo_MUSER_ALU> synthesized.
Synthesizing Unit <Modulo_3_MUSER_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
Summary:
no macro.
Unit <Modulo_3_MUSER_ALU> synthesized.
Synthesizing Unit <Modulo_1_MUSER_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
Summary:
no macro.
Unit <Modulo_1_MUSER_ALU> synthesized.
Synthesizing Unit <Modulo_0_MUSER_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
WARNING:Xst:647 - Input <b3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Summary:
no macro.
Unit <Modulo_0_MUSER_ALU> synthesized.
Synthesizing Unit <Negate_MUSER_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
Summary:
no macro.
Unit <Negate_MUSER_ALU> synthesized.
Synthesizing Unit <Negate_0_MUSER_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
Summary:
no macro.
Unit <Negate_0_MUSER_ALU> synthesized.
Synthesizing Unit <Negate_1_MUSER_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
Summary:
no macro.
Unit <Negate_1_MUSER_ALU> synthesized.
Synthesizing Unit <Negate_2_MUSER_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
Summary:
no macro.
Unit <Negate_2_MUSER_ALU> synthesized.
Synthesizing Unit <Negate_3_MUSER_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
Summary:
no macro.
Unit <Negate_3_MUSER_ALU> synthesized.
Synthesizing Unit <M4_1E_HXILINX_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
Found 1-bit 4-to-1 multiplexer for signal <S1_D3_Mux_0_o> created at line 44.
Summary:
inferred 2 Multiplexer(s).
Unit <M4_1E_HXILINX_ALU> synthesized.
Synthesizing Unit <sev_seg_disp_MUSER_ALU>.
- Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+ Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf".
Summary:
no macro.
Unit <sev_seg_disp_MUSER_ALU> synthesized.
@@ -381,6 +373,8 @@ Macro Statistics
Optimizing unit <ALU> ...
+Optimizing unit <Modulo_0_MUSER_ALU> ...
+
Optimizing unit <sev_seg_disp_MUSER_ALU> ...
Optimizing unit <M4_1E_HXILINX_ALU> ...
@@ -416,29 +410,24 @@ Top Level Output File Name : ALU.ngc
Primitive and Black Box Usage:
------------------------------
-# BELS : 125
-# AND2 : 22
+# BELS : 138
+# AND2 : 28
# AND3 : 21
-# AND4 : 2
+# AND4 : 3
# BUF : 4
# GND : 1
-# INV : 45
+# INV : 53
# LUT6 : 4
-# OR2 : 7
-# OR3 : 10
-# OR4 : 4
-# OR5 : 1
+# OR2 : 5
+# OR3 : 9
+# OR4 : 5
+# OR5 : 2
# VCC : 1
-# XNOR2 : 2
+# XNOR2 : 1
# XOR2 : 1
# IO Buffers : 18
# IBUF : 6
# OBUF : 12
-# Logical : 4
-# NAND2 : 1
-# NAND3 : 1
-# NAND4 : 1
-# NOR3 : 1
Device utilization summary:
---------------------------
@@ -447,14 +436,14 @@ Selected Device : 6slx16csg324-3
Slice Logic Utilization:
- Number of Slice LUTs: 49 out of 9112 0%
- Number used as Logic: 49 out of 9112 0%
+ Number of Slice LUTs: 57 out of 9112 0%
+ Number used as Logic: 57 out of 9112 0%
Slice Logic Distribution:
- Number of LUT Flip Flop pairs used: 49
- Number with an unused Flip Flop: 49 out of 49 100%
- Number with an unused LUT: 0 out of 49 0%
- Number of fully used LUT-FF pairs: 0 out of 49 0%
+ Number of LUT Flip Flop pairs used: 57
+ Number with an unused Flip Flop: 57 out of 57 100%
+ Number with an unused LUT: 0 out of 57 0%
+ Number of fully used LUT-FF pairs: 0 out of 57 0%
Number of unique control sets: 0
IO Utilization:
@@ -494,7 +483,7 @@ Speed Grade: -3
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
- Maximum combinational path delay: 16.544ns
+ Maximum combinational path delay: 16.900ns
Timing Details:
---------------
@@ -502,33 +491,33 @@ All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
- Total number of paths / destination ports: 1495 / 8
+ Total number of paths / destination ports: 1539 / 8
-------------------------------------------------------------------------
-Delay: 16.544ns (Levels of Logic = 13)
- Source: D (PAD)
+Delay: 16.900ns (Levels of Logic = 13)
+ Source: C (PAD)
Destination: d_out (PAD)
- Data Path: D to d_out
+ Data Path: C to d_out
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
- IBUF:I->O 24 1.222 1.172 D_IBUF (D_IBUF)
- INV:I->O 1 0.568 0.944 XLXI_1/XLXI_8/XLXI_9 (XLXI_1/XLXI_8/XLXN_17)
- AND2:I0->O 1 0.203 0.924 XLXI_1/XLXI_8/XLXI_3 (XLXI_1/XLXI_8/XLXN_1)
- OR3:I1->O 1 0.223 0.944 XLXI_1/XLXI_8/XLXI_2 (XLXI_1/XLXI_8/XLXN_2)
- AND2:I0->O 1 0.203 0.924 XLXI_1/XLXI_8/XLXI_4 (XLXI_1/XLXI_8/XLXN_4)
- OR2:I1->O 1 0.223 0.580 XLXI_1/XLXI_8/XLXI_5 (XLXN_35)
- begin scope: 'XLXI_6:D2'
- LUT6:I5->O 9 0.205 0.829 Mmux_O11 (O)
- end scope: 'XLXI_6:O'
- INV:I->O 8 0.568 1.167 XLXI_9/XLXI_39 (XLXI_9/C_BAR)
- AND3:I0->O 1 0.203 0.944 XLXI_9/XLXI_51 (XLXI_9/XLXN_114)
- OR4:I0->O 1 0.203 0.579 XLXI_9/XLXI_52 (XLXI_9/XLXN_156)
+ IBUF:I->O 26 1.222 1.206 C_IBUF (C_IBUF)
+ INV:I->O 1 0.568 0.924 XLXI_2/XLXI_4/XLXI_9 (XLXI_2/XLXI_4/XLXN_15)
+ AND2:I1->O 1 0.223 0.944 XLXI_2/XLXI_4/XLXI_16 (XLXI_2/XLXI_4/XLXN_14)
+ OR2:I0->O 1 0.203 0.944 XLXI_2/XLXI_4/XLXI_14 (XLXI_2/XLXI_4/XLXN_1)
+ AND2:I0->O 1 0.203 0.944 XLXI_2/XLXI_4/XLXI_2 (XLXI_2/XLXI_4/XLXN_4)
+ OR2:I0->O 1 0.203 0.924 XLXI_2/XLXI_4/XLXI_4 (XLXN_37)
+ begin scope: 'XLXI_7:D3'
+ LUT6:I1->O 6 0.203 0.744 Mmux_O11 (O)
+ end scope: 'XLXI_7:O'
+ INV:I->O 9 0.568 1.194 XLXI_9/XLXI_40 (XLXI_9/D_BAR)
+ AND2:I0->O 2 0.203 0.845 XLXI_9/XLXI_48 (XLXI_9/XLXN_125)
+ OR4:I3->O 1 0.339 0.579 XLXI_9/XLXI_52 (XLXI_9/XLXN_156)
INV:I->O 1 0.568 0.579 XLXI_9/XLXI_69 (d_out_OBUF)
OBUF:I->O 2.571 d_out_OBUF (d_out)
----------------------------------------
- Total 16.544ns (6.960ns logic, 9.584ns route)
- (42.1% logic, 57.9% route)
+ Total 16.900ns (7.074ns logic, 9.826ns route)
+ (41.9% logic, 58.1% route)
=========================================================================
@@ -539,11 +528,11 @@ Cross Clock Domains Report:
Total REAL time to Xst completion: 8.00 secs
-Total CPU time to Xst completion: 7.97 secs
+Total CPU time to Xst completion: 7.36 secs
-->
-Total memory usage is 253940 kilobytes
+Total memory usage is 252544 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 2 ( 0 filtered)
diff --git a/ALU.twr b/ALU.twr
index 75bdc43..8a0ecd1 100755
--- a/ALU.twr
+++ b/ALU.twr
@@ -34,65 +34,65 @@ Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
-A |a_out | 11.660|
-A |b_out | 11.371|
-A |c_out | 11.727|
-A |d_out | 11.840|
-A |e_out | 11.906|
-A |f_out | 11.587|
-A |g_out | 11.574|
-A |sign | 11.406|
-B |a_out | 11.326|
-B |b_out | 10.895|
-B |c_out | 11.387|
-B |d_out | 11.931|
-B |e_out | 11.927|
-B |f_out | 11.342|
-B |g_out | 11.489|
-B |sign | 11.072|
-C |a_out | 11.426|
-C |b_out | 11.174|
-C |c_out | 11.560|
-C |d_out | 11.886|
-C |e_out | 11.818|
-C |f_out | 11.515|
-C |g_out | 11.620|
-C |sign | 10.949|
-D |a_out | 11.570|
-D |b_out | 11.214|
-D |c_out | 11.759|
-D |d_out | 12.390|
-D |e_out | 12.386|
-D |f_out | 11.767|
-D |g_out | 11.948|
-D |sign | 11.316|
-S0 |a_out | 11.110|
-S0 |b_out | 10.858|
-S0 |c_out | 11.214|
-S0 |d_out | 11.410|
-S0 |e_out | 11.406|
-S0 |f_out | 11.074|
-S0 |g_out | 11.014|
-S0 |sign | 10.662|
-S1 |a_out | 10.677|
-S1 |b_out | 10.260|
-S1 |c_out | 10.664|
-S1 |d_out | 11.023|
-S1 |e_out | 11.019|
-S1 |f_out | 10.545|
-S1 |g_out | 10.581|
-S1 |sign | 10.423|
+A |a_out | 12.121|
+A |b_out | 12.114|
+A |c_out | 12.193|
+A |d_out | 12.977|
+A |e_out | 12.603|
+A |f_out | 12.193|
+A |g_out | 12.222|
+A |sign | 11.976|
+B |a_out | 11.205|
+B |b_out | 11.242|
+B |c_out | 11.297|
+B |d_out | 11.960|
+B |e_out | 11.586|
+B |f_out | 11.229|
+B |g_out | 11.350|
+B |sign | 11.012|
+C |a_out | 11.203|
+C |b_out | 10.960|
+C |c_out | 11.269|
+C |d_out | 12.059|
+C |e_out | 11.685|
+C |f_out | 10.983|
+C |g_out | 11.068|
+C |sign | 10.766|
+D |a_out | 11.544|
+D |b_out | 11.218|
+D |c_out | 11.615|
+D |d_out | 12.400|
+D |e_out | 12.026|
+D |f_out | 11.410|
+D |g_out | 11.394|
+D |sign | 11.193|
+S0 |a_out | 10.816|
+S0 |b_out | 10.961|
+S0 |c_out | 10.908|
+S0 |d_out | 11.499|
+S0 |e_out | 11.125|
+S0 |f_out | 10.838|
+S0 |g_out | 11.069|
+S0 |sign | 10.498|
+S1 |a_out | 10.737|
+S1 |b_out | 10.588|
+S1 |c_out | 10.829|
+S1 |d_out | 11.247|
+S1 |e_out | 10.873|
+S1 |f_out | 10.465|
+S1 |g_out | 10.696|
+S1 |sign | 10.233|
---------------+---------------+---------+
-Analysis completed Wed Feb 15 15:16:31 2012
+Analysis completed Thu Feb 16 19:53:32 2012
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
-Peak Memory Usage: 217 MB
+Peak Memory Usage: 230 MB
diff --git a/ALU.twx b/ALU.twx
index b395950..b90cdc4 100755
--- a/ALU.twx
+++ b/ALU.twx
@@ -332,7 +332,7 @@
<twReport><twHead anchorID="1"><twExecVer>Release 13.3 Trace (nt64)</twExecVer><twCopyright>Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
-n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf
-</twCmdLine><twDesign>ALU.ncd</twDesign><twDesignPath>ALU.ncd</twDesignPath><twPCF>ALU.pcf</twPCF><twPcfPath>ALU.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="csg324"><twDevName>xc6slx16</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRODUCTION 1.20 2011-10-03</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="5" twNameLen="15"><twPad2PadList anchorID="6" twSrcWidth="2" twDestWidth="5"><twPad2Pad><twSrc>A</twSrc><twDest>a_out</twDest><twDel>11.660</twDel></twPad2Pad><twPad2Pad><twSrc>A</twSrc><twDest>b_out</twDest><twDel>11.371</twDel></twPad2Pad><twPad2Pad><twSrc>A</twSrc><twDest>c_out</twDest><twDel>11.727</twDel></twPad2Pad><twPad2Pad><twSrc>A</twSrc><twDest>d_out</twDest><twDel>11.840</twDel></twPad2Pad><twPad2Pad><twSrc>A</twSrc><twDest>e_out</twDest><twDel>11.906</twDel></twPad2Pad><twPad2Pad><twSrc>A</twSrc><twDest>f_out</twDest><twDel>11.587</twDel></twPad2Pad><twPad2Pad><twSrc>A</twSrc><twDest>g_out</twDest><twDel>11.574</twDel></twPad2Pad><twPad2Pad><twSrc>A</twSrc><twDest>sign</twDest><twDel>11.406</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>a_out</twDest><twDel>11.326</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>b_out</twDest><twDel>10.895</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>c_out</twDest><twDel>11.387</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>d_out</twDest><twDel>11.931</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>e_out</twDest><twDel>11.927</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>f_out</twDest><twDel>11.342</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>g_out</twDest><twDel>11.489</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>sign</twDest><twDel>11.072</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>a_out</twDest><twDel>11.426</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>b_out</twDest><twDel>11.174</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>c_out</twDest><twDel>11.560</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>d_out</twDest><twDel>11.886</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>e_out</twDest><twDel>11.818</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>f_out</twDest><twDel>11.515</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>g_out</twDest><twDel>11.620</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>sign</twDest><twDel>10.949</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>a_out</twDest><twDel>11.570</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>b_out</twDest><twDel>11.214</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>c_out</twDest><twDel>11.759</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>d_out</twDest><twDel>12.390</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>e_out</twDest><twDel>12.386</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>f_out</twDest><twDel>11.767</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>g_out</twDest><twDel>11.948</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>sign</twDest><twDel>11.316</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>a_out</twDest><twDel>11.110</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>b_out</twDest><twDel>10.858</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>c_out</twDest><twDel>11.214</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>d_out</twDest><twDel>11.410</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>e_out</twDest><twDel>11.406</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>f_out</twDest><twDel>11.074</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>g_out</twDest><twDel>11.014</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>sign</twDest><twDel>10.662</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>a_out</twDest><twDel>10.677</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>b_out</twDest><twDel>10.260</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>c_out</twDest><twDel>10.664</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>d_out</twDest><twDel>11.023</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>e_out</twDest><twDel>11.019</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>f_out</twDest><twDel>10.545</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>g_out</twDest><twDel>10.581</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>sign</twDest><twDel>10.423</twDel></twPad2Pad></twPad2PadList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Wed Feb 15 15:16:31 2012 </twTimestamp></twFoot><twClientInfo anchorID="7"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
+</twCmdLine><twDesign>ALU.ncd</twDesign><twDesignPath>ALU.ncd</twDesignPath><twPCF>ALU.pcf</twPCF><twPcfPath>ALU.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="csg324"><twDevName>xc6slx16</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRODUCTION 1.20 2011-10-03</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="5" twNameLen="15"><twPad2PadList anchorID="6" twSrcWidth="2" twDestWidth="5"><twPad2Pad><twSrc>A</twSrc><twDest>a_out</twDest><twDel>12.121</twDel></twPad2Pad><twPad2Pad><twSrc>A</twSrc><twDest>b_out</twDest><twDel>12.114</twDel></twPad2Pad><twPad2Pad><twSrc>A</twSrc><twDest>c_out</twDest><twDel>12.193</twDel></twPad2Pad><twPad2Pad><twSrc>A</twSrc><twDest>d_out</twDest><twDel>12.977</twDel></twPad2Pad><twPad2Pad><twSrc>A</twSrc><twDest>e_out</twDest><twDel>12.603</twDel></twPad2Pad><twPad2Pad><twSrc>A</twSrc><twDest>f_out</twDest><twDel>12.193</twDel></twPad2Pad><twPad2Pad><twSrc>A</twSrc><twDest>g_out</twDest><twDel>12.222</twDel></twPad2Pad><twPad2Pad><twSrc>A</twSrc><twDest>sign</twDest><twDel>11.976</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>a_out</twDest><twDel>11.205</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>b_out</twDest><twDel>11.242</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>c_out</twDest><twDel>11.297</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>d_out</twDest><twDel>11.960</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>e_out</twDest><twDel>11.586</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>f_out</twDest><twDel>11.229</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>g_out</twDest><twDel>11.350</twDel></twPad2Pad><twPad2Pad><twSrc>B</twSrc><twDest>sign</twDest><twDel>11.012</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>a_out</twDest><twDel>11.203</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>b_out</twDest><twDel>10.960</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>c_out</twDest><twDel>11.269</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>d_out</twDest><twDel>12.059</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>e_out</twDest><twDel>11.685</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>f_out</twDest><twDel>10.983</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>g_out</twDest><twDel>11.068</twDel></twPad2Pad><twPad2Pad><twSrc>C</twSrc><twDest>sign</twDest><twDel>10.766</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>a_out</twDest><twDel>11.544</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>b_out</twDest><twDel>11.218</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>c_out</twDest><twDel>11.615</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>d_out</twDest><twDel>12.400</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>e_out</twDest><twDel>12.026</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>f_out</twDest><twDel>11.410</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>g_out</twDest><twDel>11.394</twDel></twPad2Pad><twPad2Pad><twSrc>D</twSrc><twDest>sign</twDest><twDel>11.193</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>a_out</twDest><twDel>10.816</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>b_out</twDest><twDel>10.961</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>c_out</twDest><twDel>10.908</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>d_out</twDest><twDel>11.499</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>e_out</twDest><twDel>11.125</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>f_out</twDest><twDel>10.838</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>g_out</twDest><twDel>11.069</twDel></twPad2Pad><twPad2Pad><twSrc>S0</twSrc><twDest>sign</twDest><twDel>10.498</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>a_out</twDest><twDel>10.737</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>b_out</twDest><twDel>10.588</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>c_out</twDest><twDel>10.829</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>d_out</twDest><twDel>11.247</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>e_out</twDest><twDel>10.873</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>f_out</twDest><twDel>10.465</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>g_out</twDest><twDel>10.696</twDel></twPad2Pad><twPad2Pad><twSrc>S1</twSrc><twDest>sign</twDest><twDel>10.233</twDel></twPad2Pad></twPad2PadList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Thu Feb 16 19:53:32 2012 </twTimestamp></twFoot><twClientInfo anchorID="7"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
-Peak Memory Usage: 217 MB
+Peak Memory Usage: 230 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
diff --git a/ALU.ucf b/ALU.ucf
index 20b494d..0393728 100755
--- a/ALU.ucf
+++ b/ALU.ucf
@@ -1,14 +1,13 @@
-# PlanAhead Generated physical constraints
-NET "A" LOC = C9;
+NET "A" LOC = C4;
NET "AN0" LOC = N16;
NET "AN1" LOC = N15;
NET "AN2" LOC = P18;
NET "AN3" LOC = P17;
NET "B" LOC = B8;
-NET "C" LOC = A8;
-NET "D" LOC = D9;
+NET "C" LOC = D9;
+NET "D" LOC = C9;
NET "S0" LOC = T9;
NET "S1" LOC = T10;
NET "a_out" LOC = T17;
diff --git a/ALU.unroutes b/ALU.unroutes
index 404a047..6cfcf65 100755
--- a/ALU.unroutes
+++ b/ALU.unroutes
@@ -1,7 +1,7 @@
Release 13.3 - par O.76xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
-Wed Feb 15 15:16:23 2012
+Thu Feb 16 19:53:25 2012
All signals are completely routed.
diff --git a/ALU.vf b/ALU.vf
index a99f305..d4c14ec 100755
--- a/ALU.vf
+++ b/ALU.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : ALU.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:05
+// /___/ /\ Timestamp : 02/16/2012 19:52:33
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/ALU.vf" -w "X:/My Documents/ec311/lab1/ALU.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/ALU.vf" -w "X:/My Documents/ec311/ec311-lab1/ALU.sch"
//Design Name: ALU
//Device: spartan6
//Purpose:
@@ -282,17 +282,17 @@ module Negate_3_MUSER_ALU(b0,
output result;
wire XLXN_8;
- wire XLXN_9;
+ wire XLXN_10;
- OR3 XLXI_5 (.I0(b2),
- .I1(b1),
- .I2(b0),
- .O(XLXN_9));
- NAND2 XLXI_9 (.I0(XLXN_8),
- .I1(b3),
- .O(result));
- INV XLXI_12 (.I(XLXN_9),
+ OR3 XLXI_14 (.I0(b2),
+ .I1(b1),
+ .I2(b0),
.O(XLXN_8));
+ INV XLXI_15 (.I(b3),
+ .O(XLXN_10));
+ AND2 XLXI_16 (.I0(XLXN_8),
+ .I1(XLXN_10),
+ .O(result));
endmodule
`timescale 1ns / 1ps
@@ -350,33 +350,38 @@ module Negate_2_MUSER_ALU(b0,
input b3;
output result;
- wire XLXN_7;
- wire XLXN_9;
- wire XLXN_10;
- wire XLXN_12;
- wire XLXN_16;
- wire XLXN_17;
-
- AND2 XLXI_1 (.I0(XLXN_7),
- .I1(b3),
- .O(XLXN_9));
- AND3 XLXI_2 (.I0(b2),
- .I1(XLXN_16),
- .I2(XLXN_17),
- .O(XLXN_10));
- OR2 XLXI_3 (.I0(XLXN_10),
- .I1(XLXN_9),
+ wire XLXN_35;
+ wire XLXN_37;
+ wire XLXN_40;
+ wire XLXN_41;
+ wire XLXN_44;
+ wire XLXN_47;
+ wire XLXN_49;
+
+ OR4 XLXI_8 (.I0(XLXN_37),
+ .I1(XLXN_41),
+ .I2(XLXN_40),
+ .I3(XLXN_35),
.O(result));
- OR3 XLXI_4 (.I0(XLXN_12),
- .I1(b1),
- .I2(b0),
- .O(XLXN_7));
- INV XLXI_5 (.I(b2),
- .O(XLXN_12));
- INV XLXI_6 (.I(b1),
- .O(XLXN_16));
- INV XLXI_7 (.I(b0),
- .O(XLXN_17));
+ AND2 XLXI_9 (.I0(XLXN_44),
+ .I1(b3),
+ .O(XLXN_35));
+ AND2 XLXI_10 (.I0(b1),
+ .I1(XLXN_44),
+ .O(XLXN_41));
+ AND2 XLXI_11 (.I0(b0),
+ .I1(XLXN_44),
+ .O(XLXN_40));
+ INV XLXI_14 (.I(b2),
+ .O(XLXN_44));
+ AND3 XLXI_15 (.I0(XLXN_47),
+ .I1(XLXN_49),
+ .I2(b2),
+ .O(XLXN_37));
+ INV XLXI_16 (.I(b1),
+ .O(XLXN_49));
+ INV XLXI_17 (.I(b0),
+ .O(XLXN_47));
endmodule
`timescale 1ns / 1ps
@@ -467,23 +472,40 @@ module Modulo_0_MUSER_ALU(b0,
wire XLXN_1;
wire XLXN_3;
wire XLXN_4;
- wire XLXN_5;
+ wire XLXN_12;
+ wire XLXN_14;
+ wire XLXN_15;
+ wire XLXN_16;
+ wire XLXN_27;
+ wire XLXN_28;
- XNOR2 XLXI_1 (.I0(b0),
- .I1(b1),
- .O(XLXN_1));
AND2 XLXI_2 (.I0(XLXN_1),
.I1(b2),
.O(XLXN_4));
- NAND3 XLXI_3 (.I0(XLXN_5),
- .I1(b1),
- .I2(b2),
- .O(XLXN_3));
OR2 XLXI_4 (.I0(XLXN_4),
.I1(XLXN_3),
.O(result));
- INV XLXI_5 (.I(b0),
- .O(XLXN_5));
+ INV XLXI_9 (.I(b1),
+ .O(XLXN_15));
+ INV XLXI_10 (.I(b0),
+ .O(XLXN_16));
+ AND3 XLXI_11 (.I0(b0),
+ .I1(XLXN_28),
+ .I2(XLXN_27),
+ .O(XLXN_3));
+ INV XLXI_12 (.I(b2),
+ .O(XLXN_27));
+ INV XLXI_13 (.I(b1),
+ .O(XLXN_28));
+ OR2 XLXI_14 (.I0(XLXN_14),
+ .I1(XLXN_12),
+ .O(XLXN_1));
+ AND2 XLXI_15 (.I0(b0),
+ .I1(b1),
+ .O(XLXN_12));
+ AND2 XLXI_16 (.I0(XLXN_16),
+ .I1(XLXN_15),
+ .O(XLXN_14));
endmodule
`timescale 1ns / 1ps
@@ -499,24 +521,24 @@ module Modulo_1_MUSER_ALU(b0,
input b3;
output result;
- wire XLXN_1;
wire XLXN_2;
wire XLXN_3;
wire XLXN_5;
wire XLXN_6;
wire XLXN_7;
- wire XLXN_18;
- wire XLXN_19;
- wire XLXN_20;
- wire XLXN_21;
- wire XLXN_22;
wire XLXN_23;
wire XLXN_24;
+ wire XLXN_50;
+ wire XLXN_51;
+ wire XLXN_54;
+ wire XLXN_55;
+ wire XLXN_56;
+ wire XLXN_57;
AND3 XLXI_1 (.I0(b1),
.I1(b2),
.I2(b3),
- .O(XLXN_1));
+ .O(XLXN_55));
AND3 XLXI_2 (.I0(XLXN_6),
.I1(XLXN_5),
.I2(b3),
@@ -525,38 +547,38 @@ module Modulo_1_MUSER_ALU(b0,
.I1(XLXN_7),
.I2(b3),
.O(XLXN_3));
- OR3 XLXI_4 (.I0(XLXN_3),
- .I1(XLXN_2),
- .I2(XLXN_1),
- .O(XLXN_21));
INV XLXI_5 (.I(b1),
.O(XLXN_5));
INV XLXI_6 (.I(b0),
.O(XLXN_6));
INV XLXI_7 (.I(b2),
.O(XLXN_7));
- OR2 XLXI_9 (.I0(XLXN_20),
- .I1(XLXN_21),
- .O(result));
AND4 XLXI_11 (.I0(b0),
.I1(XLXN_24),
.I2(b2),
.I3(XLXN_23),
- .O(XLXN_19));
- OR2 XLXI_12 (.I0(XLXN_19),
- .I1(XLXN_18),
- .O(XLXN_20));
- NAND4 XLXI_13 (.I0(b0),
- .I1(XLXN_22),
- .I2(b2),
- .I3(b3),
- .O(XLXN_18));
- INV XLXI_14 (.I(b1),
- .O(XLXN_22));
+ .O(XLXN_57));
INV XLXI_15 (.I(b3),
.O(XLXN_23));
INV XLXI_16 (.I(b1),
.O(XLXN_24));
+ AND4 XLXI_18 (.I0(XLXN_54),
+ .I1(b1),
+ .I2(XLXN_50),
+ .I3(XLXN_51),
+ .O(XLXN_56));
+ INV XLXI_19 (.I(b2),
+ .O(XLXN_50));
+ INV XLXI_20 (.I(b3),
+ .O(XLXN_51));
+ INV XLXI_21 (.I(b0),
+ .O(XLXN_54));
+ OR5 XLXI_22 (.I0(XLXN_57),
+ .I1(XLXN_56),
+ .I2(XLXN_3),
+ .I3(XLXN_2),
+ .I4(XLXN_55),
+ .O(result));
endmodule
`timescale 1ns / 1ps
@@ -708,25 +730,24 @@ module Divide_2_MUSER_ALU(b0,
input b3;
output result;
- wire XLXN_1;
- wire XLXN_2;
- wire XLXN_3;
- wire XLXN_7;
+ wire XLXN_9;
+ wire XLXN_13;
+ wire XLXN_14;
+ wire XLXN_15;
- OR3 XLXI_1 (.I0(XLXN_1),
- .I1(XLXN_7),
- .I2(XLXN_3),
- .O(result));
- AND3 XLXI_2 (.I0(XLXN_2),
- .I1(b3),
- .I2(b1),
- .O(XLXN_1));
- INV XLXI_3 (.I(b2),
- .O(XLXN_2));
- INV XLXI_4 (.I(b0),
- .O(XLXN_3));
- INV XLXI_9 (.I(b1),
- .O(XLXN_7));
+ AND2 XLXI_10 (.I0(XLXN_9),
+ .I1(b3),
+ .O(result));
+ OR3 XLXI_12 (.I0(XLXN_15),
+ .I1(XLXN_14),
+ .I2(XLXN_13),
+ .O(XLXN_9));
+ INV XLXI_13 (.I(b0),
+ .O(XLXN_13));
+ INV XLXI_15 (.I(b1),
+ .O(XLXN_14));
+ INV XLXI_16 (.I(b2),
+ .O(XLXN_15));
endmodule
`timescale 1ns / 1ps
@@ -743,14 +764,23 @@ module Divide_3_MUSER_ALU(b0,
output result;
wire XLXN_2;
+ wire XLXN_13;
+ wire XLXN_14;
+ wire XLXN_15;
AND2 XLXI_2 (.I0(XLXN_2),
.I1(b3),
.O(result));
- NOR3 XLXI_3 (.I0(b0),
- .I1(b1),
- .I2(b2),
- .O(XLXN_2));
+ OR3 XLXI_4 (.I0(XLXN_15),
+ .I1(XLXN_14),
+ .I2(XLXN_13),
+ .O(XLXN_2));
+ INV XLXI_6 (.I(b2),
+ .O(XLXN_13));
+ INV XLXI_7 (.I(b1),
+ .O(XLXN_14));
+ INV XLXI_8 (.I(b0),
+ .O(XLXN_15));
endmodule
`timescale 1ns / 1ps
@@ -766,25 +796,23 @@ module Divide_0_MUSER_ALU(b0,
input b3;
output result;
- wire XLXN_1;
wire XLXN_2;
wire XLXN_3;
wire XLXN_4;
wire XLXN_5;
wire XLXN_6;
+ wire XLXN_12;
- AND3 XLXI_1 (.I0(b3),
+ AND3 XLXI_1 (.I0(b0),
.I1(b3),
.I2(XLXN_2),
.O(XLXN_5));
AND2 XLXI_2 (.I0(b1),
- .I1(XLXN_1),
+ .I1(XLXN_12),
.O(XLXN_4));
AND2 XLXI_3 (.I0(b1),
.I1(XLXN_3),
.O(XLXN_6));
- INV XLXI_4 (.I(b3),
- .O(XLXN_1));
INV XLXI_5 (.I(b1),
.O(XLXN_2));
INV XLXI_6 (.I(b0),
@@ -793,6 +821,8 @@ module Divide_0_MUSER_ALU(b0,
.I1(XLXN_5),
.I2(XLXN_4),
.O(result));
+ INV XLXI_9 (.I(b3),
+ .O(XLXN_12));
endmodule
`timescale 1ns / 1ps
@@ -830,10 +860,10 @@ module Divide_MUSER_ALU(b0,
.b2(b2),
.b3(b3),
.result(out3));
- Divide_0_MUSER_ALU XLXI_12 (.b0(b1),
- .b1(b2),
+ Divide_0_MUSER_ALU XLXI_12 (.b0(b0),
+ .b1(b1),
.b2(b2),
- .b3(b0),
+ .b3(b3),
.result(out0));
endmodule
`timescale 1ns / 1ps
@@ -881,10 +911,6 @@ module ALU(A,
wire XLXN_23;
wire XLXN_24;
wire XLXN_25;
- wire XLXN_26;
- wire XLXN_27;
- wire XLXN_28;
- wire XLXN_31;
wire XLXN_33;
wire XLXN_34;
wire XLXN_35;
@@ -893,6 +919,10 @@ module ALU(A,
wire XLXN_38;
wire XLXN_39;
wire XLXN_41;
+ wire XLXN_42;
+ wire XLXN_43;
+ wire XLXN_44;
+ wire XLXN_45;
Divide_MUSER_ALU XLXI_1 (.b0(D),
.b1(C),
@@ -914,13 +944,13 @@ module ALU(A,
.b1(C),
.b2(B),
.b3(A),
- .out0(XLXN_27),
- .out1(XLXN_28),
- .out2(XLXN_31),
- .out3(XLXN_26));
+ .out0(XLXN_42),
+ .out1(XLXN_43),
+ .out2(XLXN_44),
+ .out3(XLXN_45));
(* HU_SET = "XLXI_4_0" *)
M4_1E_HXILINX_ALU XLXI_4 (.D0(A),
- .D1(XLXN_26),
+ .D1(XLXN_45),
.D2(XLXN_33),
.D3(XLXN_41),
.E(XLXN_12),
@@ -929,7 +959,7 @@ module ALU(A,
.O(XLXN_22));
(* HU_SET = "XLXI_5_1" *)
M4_1E_HXILINX_ALU XLXI_5 (.D0(B),
- .D1(XLXN_27),
+ .D1(XLXN_44),
.D2(XLXN_34),
.D3(XLXN_39),
.E(XLXN_12),
@@ -938,7 +968,7 @@ module ALU(A,
.O(XLXN_23));
(* HU_SET = "XLXI_6_2" *)
M4_1E_HXILINX_ALU XLXI_6 (.D0(C),
- .D1(XLXN_28),
+ .D1(XLXN_43),
.D2(XLXN_35),
.D3(XLXN_38),
.E(XLXN_12),
@@ -947,7 +977,7 @@ module ALU(A,
.O(XLXN_24));
(* HU_SET = "XLXI_7_3" *)
M4_1E_HXILINX_ALU XLXI_7 (.D0(D),
- .D1(XLXN_31),
+ .D1(XLXN_42),
.D2(XLXN_36),
.D3(XLXN_37),
.E(XLXN_12),
diff --git a/ALU_bitgen.xwbt b/ALU_bitgen.xwbt
index f3acff2..78a0bc1 100755
--- a/ALU_bitgen.xwbt
+++ b/ALU_bitgen.xwbt
@@ -1,8 +1,8 @@
INTSTYLE=ise
-INFILE=X:\My Documents\ec311\lab1\ALU.ncd
-OUTFILE=X:\My Documents\ec311\lab1\ALU.bit
+INFILE=X:\My Documents\ec311\ec311-lab1\ALU.ncd
+OUTFILE=X:\My Documents\ec311\ec311-lab1\ALU.bit
FAMILY=Spartan6
PART=xc6slx16-3csg324
-WORKINGDIR=X:\My Documents\ec311\lab1
+WORKINGDIR=X:\My Documents\ec311\ec311-lab1
LICENSE=ISE
USER_INFO=__174135685_174135686_174419191
diff --git a/ALU_envsettings.html b/ALU_envsettings.html
index 2c65f7c..109e8da 100644
--- a/ALU_envsettings.html
+++ b/ALU_envsettings.html
@@ -14,53 +14,53 @@
<td><b>par</b></td>
</tr>
<tr>
-<td>PATH</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C:<br>\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\PlanAhead\bin;C:<br>\Xilinx\13.3\ISE_DS\ISE\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\ISE\lib\nt64;C:<br>\Xilinx\13.3\ISE_DS\EDK\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\EDK\lib\nt64;C:<br>\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C:<br>\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C:<br>\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C:<br>\Xilinx\13.3\ISE_DS\common\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\common\lib\nt64;C:<br>\Windows\system32;C:<br>\Windows;C:<br>\Windows\System32\Wbem;C:<br>\Windows\System32\WindowsPowerShell\v1.0\;C:<br>\Program Files\MATLAB\R2011a\runtime\win64;C:<br>\Program Files\MATLAB\R2011a\bin;C:<br>\VXIPNP\WinNT\Bin;C:<br>\Program Files (x86)\Altium Designer Summer 09\System;C:<br>\Program Files (x86)\QuickTime\QTSystem\;C:<br>\Program Files\NetBeans 7.0.1\java\ant\bin;C:<br>\Program Files\Java\jdk1.6.0_27\bin;C:<br>\Program Files\TortoiseSVN\bin;C:<br>\Program Files (x86)\Rational\Rose RealTime\bin\win32;C:<br>\Program Files (x86)\Rational\common;C:<br>\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:<br>\Cadence\SPB_16.5\tools\Capture;C:<br>\Cadence\SPB_16.5\tools\PSpice\Library;C:<br>\Cadence\SPB_16.5\tools\PSpice;C:<br>\Cadence\SPB_16.5\tools\specctra\bin;C:<br>\Cadence\SPB_16.5\tools\fet\bin;C:<br>\Cadence\SPB_16.5\tools\libutil\bin;C:<br>\Cadence\SPB_16.5\tools\bin;C:<br>\Cadence\SPB_16.5\tools\pcb\bin</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C:<br>\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\PlanAhead\bin;C:<br>\Xilinx\13.3\ISE_DS\ISE\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\ISE\lib\nt64;C:<br>\Xilinx\13.3\ISE_DS\EDK\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\EDK\lib\nt64;C:<br>\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C:<br>\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C:<br>\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C:<br>\Xilinx\13.3\ISE_DS\common\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\common\lib\nt64;C:<br>\Windows\system32;C:<br>\Windows;C:<br>\Windows\System32\Wbem;C:<br>\Windows\System32\WindowsPowerShell\v1.0\;C:<br>\Program Files\MATLAB\R2011a\runtime\win64;C:<br>\Program Files\MATLAB\R2011a\bin;C:<br>\VXIPNP\WinNT\Bin;C:<br>\Program Files (x86)\Altium Designer Summer 09\System;C:<br>\Program Files (x86)\QuickTime\QTSystem\;C:<br>\Program Files\NetBeans 7.0.1\java\ant\bin;C:<br>\Program Files\Java\jdk1.6.0_27\bin;C:<br>\Program Files\TortoiseSVN\bin;C:<br>\Program Files (x86)\Rational\Rose RealTime\bin\win32;C:<br>\Program Files (x86)\Rational\common;C:<br>\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:<br>\Cadence\SPB_16.5\tools\Capture;C:<br>\Cadence\SPB_16.5\tools\PSpice\Library;C:<br>\Cadence\SPB_16.5\tools\PSpice;C:<br>\Cadence\SPB_16.5\tools\specctra\bin;C:<br>\Cadence\SPB_16.5\tools\fet\bin;C:<br>\Cadence\SPB_16.5\tools\libutil\bin;C:<br>\Cadence\SPB_16.5\tools\bin;C:<br>\Cadence\SPB_16.5\tools\pcb\bin</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C:<br>\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\PlanAhead\bin;C:<br>\Xilinx\13.3\ISE_DS\ISE\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\ISE\lib\nt64;C:<br>\Xilinx\13.3\ISE_DS\EDK\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\EDK\lib\nt64;C:<br>\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C:<br>\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C:<br>\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C:<br>\Xilinx\13.3\ISE_DS\common\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\common\lib\nt64;C:<br>\Windows\system32;C:<br>\Windows;C:<br>\Windows\System32\Wbem;C:<br>\Windows\System32\WindowsPowerShell\v1.0\;C:<br>\Program Files\MATLAB\R2011a\runtime\win64;C:<br>\Program Files\MATLAB\R2011a\bin;C:<br>\VXIPNP\WinNT\Bin;C:<br>\Program Files (x86)\Altium Designer Summer 09\System;C:<br>\Program Files (x86)\QuickTime\QTSystem\;C:<br>\Program Files\NetBeans 7.0.1\java\ant\bin;C:<br>\Program Files\Java\jdk1.6.0_27\bin;C:<br>\Program Files\TortoiseSVN\bin;C:<br>\Program Files (x86)\Rational\Rose RealTime\bin\win32;C:<br>\Program Files (x86)\Rational\common;C:<br>\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:<br>\Cadence\SPB_16.5\tools\Capture;C:<br>\Cadence\SPB_16.5\tools\PSpice\Library;C:<br>\Cadence\SPB_16.5\tools\PSpice;C:<br>\Cadence\SPB_16.5\tools\specctra\bin;C:<br>\Cadence\SPB_16.5\tools\fet\bin;C:<br>\Cadence\SPB_16.5\tools\libutil\bin;C:<br>\Cadence\SPB_16.5\tools\bin;C:<br>\Cadence\SPB_16.5\tools\pcb\bin</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C:<br>\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\PlanAhead\bin;C:<br>\Xilinx\13.3\ISE_DS\ISE\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\ISE\lib\nt64;C:<br>\Xilinx\13.3\ISE_DS\EDK\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\EDK\lib\nt64;C:<br>\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C:<br>\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C:<br>\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C:<br>\Xilinx\13.3\ISE_DS\common\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\common\lib\nt64;C:<br>\Windows\system32;C:<br>\Windows;C:<br>\Windows\System32\Wbem;C:<br>\Windows\System32\WindowsPowerShell\v1.0\;C:<br>\Program Files\MATLAB\R2011a\runtime\win64;C:<br>\Program Files\MATLAB\R2011a\bin;C:<br>\VXIPNP\WinNT\Bin;C:<br>\Program Files (x86)\Altium Designer Summer 09\System;C:<br>\Program Files (x86)\QuickTime\QTSystem\;C:<br>\Program Files\NetBeans 7.0.1\java\ant\bin;C:<br>\Program Files\Java\jdk1.6.0_27\bin;C:<br>\Program Files\TortoiseSVN\bin;C:<br>\Program Files (x86)\Rational\Rose RealTime\bin\win32;C:<br>\Program Files (x86)\Rational\common;C:<br>\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:<br>\Cadence\SPB_16.5\tools\Capture;C:<br>\Cadence\SPB_16.5\tools\PSpice\Library;C:<br>\Cadence\SPB_16.5\tools\PSpice;C:<br>\Cadence\SPB_16.5\tools\specctra\bin;C:<br>\Cadence\SPB_16.5\tools\fet\bin;C:<br>\Cadence\SPB_16.5\tools\libutil\bin;C:<br>\Cadence\SPB_16.5\tools\bin;C:<br>\Cadence\SPB_16.5\tools\pcb\bin</td>
+<td>PATHEXT</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
+<td><font color=gray>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</font></td>
</tr>
<tr>
-<td>PATHEXT</td>
-<td>.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC</td>
-<td>.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC</td>
-<td>.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC</td>
-<td>.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC</td>
+<td>Path</td>
+<td>C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\13.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\MATLAB\R2011a\runtime\win64;<br>C:\Program Files\MATLAB\R2011a\bin;<br>C:\VXIPNP\WinNT\Bin;<br>C:\Program Files (x86)\Altium Designer Summer 09\System;<br>C:\Program Files (x86)\QuickTime\QTSystem\;<br>C:\Program Files\NetBeans 7.0.1\java\ant\bin;<br>C:\Program Files\Java\jdk1.6.0_27\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\Rational\Rose RealTime\bin\win32;<br>C:\Program Files (x86)\Rational\common;<br>C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;<br>C:\Cadence\SPB_16.5\tools\Capture;<br>C:\Cadence\SPB_16.5\tools\PSpice\Library;<br>C:\Cadence\SPB_16.5\tools\PSpice;<br>C:\Cadence\SPB_16.5\tools\specctra\bin;<br>C:\Cadence\SPB_16.5\tools\fet\bin;<br>C:\Cadence\SPB_16.5\tools\libutil\bin;<br>C:\Cadence\SPB_16.5\tools\bin;<br>C:\Cadence\SPB_16.5\tools\pcb\bin</td>
+<td>C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\13.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\MATLAB\R2011a\runtime\win64;<br>C:\Program Files\MATLAB\R2011a\bin;<br>C:\VXIPNP\WinNT\Bin;<br>C:\Program Files (x86)\Altium Designer Summer 09\System;<br>C:\Program Files (x86)\QuickTime\QTSystem\;<br>C:\Program Files\NetBeans 7.0.1\java\ant\bin;<br>C:\Program Files\Java\jdk1.6.0_27\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\Rational\Rose RealTime\bin\win32;<br>C:\Program Files (x86)\Rational\common;<br>C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;<br>C:\Cadence\SPB_16.5\tools\Capture;<br>C:\Cadence\SPB_16.5\tools\PSpice\Library;<br>C:\Cadence\SPB_16.5\tools\PSpice;<br>C:\Cadence\SPB_16.5\tools\specctra\bin;<br>C:\Cadence\SPB_16.5\tools\fet\bin;<br>C:\Cadence\SPB_16.5\tools\libutil\bin;<br>C:\Cadence\SPB_16.5\tools\bin;<br>C:\Cadence\SPB_16.5\tools\pcb\bin</td>
+<td>C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\13.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\MATLAB\R2011a\runtime\win64;<br>C:\Program Files\MATLAB\R2011a\bin;<br>C:\VXIPNP\WinNT\Bin;<br>C:\Program Files (x86)\Altium Designer Summer 09\System;<br>C:\Program Files (x86)\QuickTime\QTSystem\;<br>C:\Program Files\NetBeans 7.0.1\java\ant\bin;<br>C:\Program Files\Java\jdk1.6.0_27\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\Rational\Rose RealTime\bin\win32;<br>C:\Program Files (x86)\Rational\common;<br>C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;<br>C:\Cadence\SPB_16.5\tools\Capture;<br>C:\Cadence\SPB_16.5\tools\PSpice\Library;<br>C:\Cadence\SPB_16.5\tools\PSpice;<br>C:\Cadence\SPB_16.5\tools\specctra\bin;<br>C:\Cadence\SPB_16.5\tools\fet\bin;<br>C:\Cadence\SPB_16.5\tools\libutil\bin;<br>C:\Cadence\SPB_16.5\tools\bin;<br>C:\Cadence\SPB_16.5\tools\pcb\bin</td>
+<td><font color=gray>C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\13.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\13.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\MATLAB\R2011a\runtime\win64;<br>C:\Program Files\MATLAB\R2011a\bin;<br>C:\VXIPNP\WinNT\Bin;<br>C:\Program Files (x86)\Altium Designer Summer 09\System;<br>C:\Program Files (x86)\QuickTime\QTSystem\;<br>C:\Program Files\NetBeans 7.0.1\java\ant\bin;<br>C:\Program Files\Java\jdk1.6.0_27\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\Rational\Rose RealTime\bin\win32;<br>C:\Program Files (x86)\Rational\common;<br>C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;<br>C:\Cadence\SPB_16.5\tools\Capture;<br>C:\Cadence\SPB_16.5\tools\PSpice\Library;<br>C:\Cadence\SPB_16.5\tools\PSpice;<br>C:\Cadence\SPB_16.5\tools\specctra\bin;<br>C:\Cadence\SPB_16.5\tools\fet\bin;<br>C:\Cadence\SPB_16.5\tools\libutil\bin;<br>C:\Cadence\SPB_16.5\tools\bin;<br>C:\Cadence\SPB_16.5\tools\pcb\bin</font></td>
</tr>
<tr>
<td>XILINX</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\ISE\</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\ISE\</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\ISE\</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\ISE\</td>
+<td>C:\Xilinx\13.3\ISE_DS\ISE\</td>
+<td>C:\Xilinx\13.3\ISE_DS\ISE\</td>
+<td>C:\Xilinx\13.3\ISE_DS\ISE\</td>
+<td><font color=gray>C:\Xilinx\13.3\ISE_DS\ISE\</font></td>
</tr>
<tr>
<td>XILINXD_LICENSE_FILE</td>
<td>2100@XilinxLM.bu.edu</td>
<td>2100@XilinxLM.bu.edu</td>
<td>2100@XilinxLM.bu.edu</td>
-<td>2100@XilinxLM.bu.edu</td>
+<td><font color=gray>2100@XilinxLM.bu.edu</font></td>
</tr>
<tr>
<td>XILINX_DSP</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\ISE</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\ISE</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\ISE</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\ISE</td>
+<td>C:\Xilinx\13.3\ISE_DS\ISE</td>
+<td>C:\Xilinx\13.3\ISE_DS\ISE</td>
+<td>C:\Xilinx\13.3\ISE_DS\ISE</td>
+<td><font color=gray>C:\Xilinx\13.3\ISE_DS\ISE</font></td>
</tr>
<tr>
<td>XILINX_EDK</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\EDK</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\EDK</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\EDK</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\EDK</td>
+<td>C:\Xilinx\13.3\ISE_DS\EDK</td>
+<td>C:\Xilinx\13.3\ISE_DS\EDK</td>
+<td>C:\Xilinx\13.3\ISE_DS\EDK</td>
+<td><font color=gray>C:\Xilinx\13.3\ISE_DS\EDK</font></td>
</tr>
<tr>
<td>XILINX_PLANAHEAD</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\PlanAhead</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\PlanAhead</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\PlanAhead</td>
-<td>C:<br>\Xilinx\13.3\ISE_DS\PlanAhead</td>
+<td>C:\Xilinx\13.3\ISE_DS\PlanAhead</td>
+<td>C:\Xilinx\13.3\ISE_DS\PlanAhead</td>
+<td>C:\Xilinx\13.3\ISE_DS\PlanAhead</td>
+<td><font color=gray>C:\Xilinx\13.3\ISE_DS\PlanAhead</font></td>
</tr>
</TABLE>
<A NAME="Synthesis Property Settings"></A>
@@ -477,28 +477,28 @@
<td><b>Default Value</b></td>
</tr>
<tr>
-<td>-intstyle</td>
-<td>&nbsp;</td>
-<td>ise</td>
-<td>&nbsp;</td>
+<td><font color=gray>-intstyle</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>ise</font></td>
+<td><font color=gray>&nbsp;</font></td>
</tr>
<tr>
-<td>-mt</td>
-<td>Enable Multi-Threading</td>
-<td>off</td>
-<td>off</td>
+<td><font color=gray>-mt</font></td>
+<td><font color=gray>Enable Multi-Threading</font></td>
+<td><font color=gray>off</font></td>
+<td><font color=gray>off</font></td>
</tr>
<tr>
-<td>-ol</td>
-<td>Place & Route Effort Level (Overall)</td>
-<td>high</td>
-<td>std</td>
+<td><font color=gray>-ol</font></td>
+<td><font color=gray>Place & Route Effort Level (Overall)</font></td>
+<td><font color=gray>high</font></td>
+<td><font color=gray>std</font></td>
</tr>
<tr>
-<td>-w</td>
-<td>&nbsp;</td>
-<td>true</td>
-<td>false</td>
+<td><font color=gray>-w</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>true</font></td>
+<td><font color=gray>false</font></td>
</tr>
</TABLE>
<A NAME="Operating System Information"></A>
@@ -518,28 +518,28 @@
<td>Intel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz</td>
-<td>Intel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz</td>
+<td><font color=gray>Intel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz</font></td>
</tr>
<tr>
<td>Host</td>
-<td>ECE-PHO115-09</td>
-<td>ECE-PHO115-09</td>
-<td>ECE-PHO115-09</td>
-<td>ECE-PHO115-09</td>
+<td>ECE-PHO115-08</td>
+<td>ECE-PHO115-08</td>
+<td>ECE-PHO115-08</td>
+<td><font color=gray>ECE-PHO115-08</font></td>
</tr>
<tr>
<td>OS Name</td>
<td>Microsoft Windows 7 , 64-bit</td>
<td>Microsoft Windows 7 , 64-bit</td>
<td>Microsoft Windows 7 , 64-bit</td>
-<td>Microsoft Windows 7 , 64-bit</td>
+<td><font color=gray>Microsoft Windows 7 , 64-bit</font></td>
</tr>
<tr>
<td>OS Release</td>
<td>Service Pack 1 (build 7601)</td>
<td>Service Pack 1 (build 7601)</td>
<td>Service Pack 1 (build 7601)</td>
-<td>Service Pack 1 (build 7601)</td>
+<td><font color=gray>Service Pack 1 (build 7601)</font></td>
</tr>
</TABLE>
</BODY> </HTML> \ No newline at end of file
diff --git a/ALU_guide.ncd b/ALU_guide.ncd
index be0b713..ca10a31 100755
--- a/ALU_guide.ncd
+++ b/ALU_guide.ncd
@@ -1,3 +1,3 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
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NbY21NjacLB9tQ9GrG8zs/fy9d5we2bhLcqksY4p/ub+3LxuNddhvwhrsvtAZQtPEhyoqMP8gcpjrsBXqcdsga9yj9kCb1/EwHauaJUe6xYt5ouWixHWU7RYULTUdTODdy6m40a/XJsrXxk3bcdr56LwvOMdL6zjweOizxP2DbDq8cSvThARb+/z7qIcFnIucKYQ3gXOZCJwAfKYcwHzmHGBucHDD9L45vrOXGsBBols7rTMVQ9gUGnMPY+5/gAMJDN3H+azIGA5tt8EzacyiTH7ncxcsMs1iL1dN5fWEmP2xtpcBEsssbfA5nZVYpm9WjXv+4DVyL7sm3doiRH7Am2+z0qM2Y+z5puXxDL7wct8R5JYYT8imY8aEivtFw1zVSIxd01iP+AACB339Sb4/gvhLrj8DKxcqkoqe5DWkjdF4DnY0d+Bo00DZ5x34GJValVJlrTM0daaVjdwRlK0dfi5LlPLwVO1S7ivYIWWQmgpVBAlD0paQ47NwkQ3pRIZok59wJYmrYYq1twHnVJzrDRHdU8v74aJgonmCz6UFxb6Ghw9SP+psdqAQDOIQaMZbAVKaKwaWElKoTYmtdEBLSkdbaRp9ZRYS+w3QKClnlYzNFMgMxSt2xiBlnlaoml1AxmjaFG46YHTpV6Aq33PXS4h62RV1tydDXHWdUe0VH2SZHoNosWSqSf9qaWj2ujSIdL2SNs+snkODCqkZyI7ExsG2mzSMLU6yikGWDNAtqBkigGudTho+2ATUVosmeKSD9Z8as0n0nzcizXRfHLFJzZ2ru2RWn+VVXEklI8kX1mErpHQWWQ+0X9P4XTBAS4jD9MARh5mAYw9HAcw8XASwNTDaQAzD+cBHHtYBHDi4SqAUwfjKIAzD6MAzj2MA7jwcGgT4eHQJqWHQ5tUHg5t4u2NA5tU3t44sEml71LN/0Ci4bO0BCtXDwQRTHJKqKCMpVSwmqWAJSyTv1HEUvhXUxpFIQ30aprQDLCaMUZJBs8zWjHant9LCWSEUkyIn0UxwxTRUs3HBLn5mpZJWuh05ilqoqiZozDU0OymRo5iP3XSpoUW99BSoI3dc0srCHK0Nc1A1/Yc5ujUnMBmkrKWs5W82HIIZzqujVl2DqVgy5oGT2E2UDDQZSfHX84BP/4+x2fOUS2WlGAGi+OWpfAuKjkGWu0T8JmsTOqCOFaxHwWhT0jxIFlC6IdhK52NSQoCVwwrd0S97ohb4e7n9dN2Uaao968NiqhQi1rUOKCWFEwadIe0RCXSf6MnMgHWnin5VbRSCRE5Ll0pn7sOUTShu5EqAVGIQouhgsRNJ/c9d6hJNvjHWMgX7aJo8KBqHIQs/FKKIGiRkVxyADKgAa7PWvX3eXZmBKn4X6wXzI5hTazSxxTn/2ml3+HWKITG8u2N4nlefC6nbpHsPgsj1/Lvo6/MNtQX7cQ9N5mhsqSftpNFv6BVG9ZvULPfos4MxX8Azq34ww==###2516:XlxV32DM 3fff 9bceNrFW1uS3CoM3ZKFhB+dddwFTPrxmb98TWXvFzBWYywZsN01lapUT/tIwqA3aiKLXdfRk55IZMLniZ6W7MuOCIh2QoPIiC0a6U7WjvSIFCZQjOsn7tOLBscZA/eXo0UcHOYRPkOCvq8kj+snAh9A23V2dP9ehGhOcLIB45+R53mYDzIf49fz798feOKtu/Xff8bXDX79HZ838+u/8XFDQ99+e/FL2HTPxNIdwW26PwBpwZN4XGVK2FC+j80frokHrb3c8a2ZeGvw1FFNfFT9KeWZEuXpT6nzyOpsxL3ts72dP29NbkaTYHI6utsx0BwNvJI6tGlAjw1Y2sW+aHJ7mdOsdfJlraXgRlJaw9ThuTszk3FYcZ+fi1wXnPSsLKUnIGPNmy5IZF4O7bQnUL78BlSvqiy5JKl1ZQckuv+JwGEhWojnQN4ruW+nyPe8XBHhvjPujz6ElWMrm/nK0lIJHjFr9iA/P+ifsdI/z1yCLw1hhlyYwRBmHkmYgQd+e7N3YUZ3lN5BouowZ/WDgJRfSMY6YDDMfCOGZCNscAFGRgdFheiOncOW6NwHSYqJq+sZEdFu13X0G1FGh3dsQFMTumtA9xusWRRjg7X8fFY/G7Gy43WhaKaJOC0xmPMwNsgV5daROqqFxoVw8AasOwKFa5HOaeIxzg10bPIv725s6jiY3/vbHOX/Tl1IMGLLRnxPjfg3eSO2qhEPS0ZUMOI53d4a8SAYccCyeWFGZwOdTcwLd9DDUkqkaDZ5LJg8JiavS1mMGPI1RdNB0dCGxHjKaGxATw1Ym2O9KTNWNktinB5JQFRz2jFLnCOnbl4qx12aPbNSOVbSJAbViWZImdl1+d8bM+ydGY7BDKe0ZBtGX7JNasmWm1CvHIsUEaMqxtTAJEqQo8clkefjN2q0NUnar0dNWcGAVawUhagpZpEUs2IyY/bj0Hp/HL0p0CDj5l2Sykncp1dp6uMgfiQO4jVxsKyJwpvOJe2Wclzvd3au7XKwOufs1VxwCVabXHA3P63T/QUt6b5R33ssaqXZ72YtbYtCuO9VvTmc5Zxo/5iYpMDaIa9stTpb2qyDd7awjjnLn/ePxDdi3Sxy6hNO9gQnZD5hb060tDrmZGKYPx6nArcQDgfOSl9pVjr0Pis1Qlb6VvO4PQVFnTQzEZF1eSOsSsVS3ggr91DOBE1Ddjc2YGmNrSrQ6HCBRh8JTPSxAo0uLtCouUAbb3Cjb28EEIzAWFxKs/08qncb65fqluxE2KZjgg8dFFx1VDvvDpXvrhUrEEvWK8sVKFPtFx8XvK9+1vChs4aPmeXM+6xhNnEsFoBbPb/ScUCb6xA5QEtZWsWh7L4m575McF9dcF+v1zcOmwC+BDm7XNgVe8NWDJJW7A3bpHndlerPpVnuT0i9loQDXvOo57i+1QGXNjvgQLvji2+oKW13fP3ebXdw+6FTimSfUVF6m+IL/5AB0ea2ZG0uwnP+VrgTyvhefidUlvyZW7Ajcs/d91VI/NDdZoXkK+5uhdtl5i+tainks1vsQANJGd8lef0Wa1d95hIWq7G06jKXsLYBC9VYbHg33L5brMk6pZbDQJX29LukAlxLGBYsV306FuJ6MjQ3XaWpBUwQCzoNY/mN7ZS0t7rkYg60+12+mgPRo9Jq6Kq9OdAn8y54Yt5lXseDmwzHJ3l6nuQ5MxFE3FratiVroxUpkzubM1T0o1ZOOIUQdH9z0LVp0O17H3T7YtAFhf1QXBgo4XrQNyA6OUg2AA7KoSSUL0MW3U5iYAqJgVmFDp/bPZNhkZmzimEuBwZZ6uS2c9VD+lGJSW5aHbwrZTXwqwrfXaXcSl5qKqANmr0lSCtDJZSYQNWtg5QWBgParm7AymjTgKZVw7GMpiZ014DGprdE4S31gBmTgnfA5FQN6vxY5G2KwdjsjGkdD1nAIcueCqE8+nHy5mBIkgM6NQw7cXKwjKbdOdRhGup869TE1qkYSHazIW0gbZsRDzvTsyMj9jOD47mS4e3oTylMxwpzLuciVphzo/fJNWTW/oGYtWOlQ5wzcbtbGWxd9UxVWf/Eqgab0EMD2tZWTBFtm9D7bynvjVzTZtR61d1YdxeCbZWczyYTutzrE6YGWRelg6rEQk/sTOKryVrxL6TvO3VURS1c4/3lFKJWTvCXIYg9OIiZNIhN1gexQQ1iQ+HHOOotfYGy119JRUuvl7tuSjbmvY3De9j80GoRhya1OdUO/smG8M+1hH+iKfyTbeHPN4ZLrWGlGsR3c7gi+cGW9nBEYwO6ukUc0bYJDQ1obHpLuVUsJfL0rh3T1qzCW/FvxSJhKBQJcKpIAC4Szv36dOAiAU4VCZaLBHOqSKCkSIAYSJ88TfZMp8nutvhDpWW0rXAdXT80ijttg+QHRKu2waxWMjptYJTQ6x8QldHUhO4a0H2OjY4NhDHadCwWktuVHDstc2lFLM+9ZdjygACeGg/Ay4cD8PLRALxwMCAfr/0fSneOSA==###1472:XlxV32DM 1c56 5a8eNq9WcuS6yYQ/SX6gYTsza3kB3IX+QA/pOVUzSIr1fx7GiThFgZJWKmMq/xApxto+hwaxhhjkTseGO3AAxk7WCO/e9sa8/PzBf1wMRcav9xwAbj+4/oLXv92zws0/UhASDcmfrC1jh9i66SttZ1/F89OXgODMRoj3wZupQ/iwVrLZMzUI6f2OaQlS4SMBSsbETaiuYiGiAholscpWuKCDPwMdkiw2M3YuZd3u4AmQXfx+dLHg0CwlGB5ws7PrX8uRho7cCfjSW1cxAUbFTOPHLx1mCcuHrRl9LqyWmyYZb6SFa+nYi0IK3Mpety0kXWs93jQRmexzupVpLCEyuX+YF65b3Tu353PfZvJfb/iGEb9OJD5wp8kL5V9DlvM58mO1/m8gzYVaKCmCo0pOssQiWFAmzeO5NHdgtbsK6BxHonJcBUzaFZcjeox888c5J/J8m9SpTr+BZstLvlvn3Bwstvi1KbnCjvFLDjER0h/v/ERhI9d4GOr6IgdjF6ahY5HqWSzC8XzkmS2orjEkLVM5XyxdHPy4WQZEwo+7MdUyIVVJIVduYBdtEnRM+0gS2mnKA0xCqWZJ3HKRthWzx1DrPMS20aEDYhcNnR1PWapn2wBmU0CdzcJe3ocFPKzPI58/2te+Gfkc6ZQ8O37CWs4F4W84ak94ImUJzzhybzK1J212vYzFZOTpylXP/U0rVUoHzb8tAdWrYurZmcBxSigTgvonbyAUlFArSJKI9VwP6dtHq0RuemZDfGrk4DmJTVzzQ9qh4cP++HEDj8UWawSWcyJbKxtIDNzXNU2oM5GcCRO86q+C6SS5E2BRF8TxiR8vkXrmYjb85C44f8ubiuanBC3RkmSPSVu/5VMshK3M5LklLThKWkzUdpwM3fyObNe8WecV03+2M2yYD/rt8qCbUs3izCJCN+CCDdahPuHF2E+XMViQb6mY8jnocUYWj61+7SRVnQqZSCmzBk/nUphOkNORalTftQFGa+EtHZmNpKKsn6OC1g6onN5SAdqX96pfUtnkZpxdCWBsO181ioVKljX9+zvyInDFKSlrexxOeOY3VMVFbbwdvf0Rur0RrsnQ1InQ9o9dZIqiKh67nm797N0Ye5HYpZcwX7QCy2XFyyyz0H2b/ouEe4jdeomMV9HwfIp74LarbuyuMyOSBW7J6ndk3b3QCqkeHNiU7HBOgjHyZqviZKJ+7HcjeIG4V+3icX5HI0/rm8vQ1LZmFR3lVSPdqQmW0i0Wc++v75wNfWKab95NcXp+lWubNwSTlWqadlRE4HSqMpzCv3sXt9MdR/dZKkgLNXyv4SfL3axEWLjrYmNHBvvHBttbHxgbKTY+DSxEZdG+fv1688RkS7U3NjR0EvDHyOOrvNoeaEZrt/ufv0ZnV2awExNgv1r/C0TMNff94uB6zcY/+MbIPzyfgf/wfIh4H8BQdWKPw== \ No newline at end of file
diff --git a/ALU_map.map b/ALU_map.map
index f6a2ce0..693adae 100755
--- a/ALU_map.map
+++ b/ALU_map.map
@@ -10,7 +10,7 @@ Target Device : xc6slx16
Target Package : csg324
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
-Mapped Date : Wed Feb 15 15:15:50 2012
+Mapped Date : Thu Feb 16 19:52:56 2012
Mapping design into LUTs...
Running directed packing...
@@ -19,53 +19,53 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
-Total REAL time at the beginning of Placer: 7 secs
+Total REAL time at the beginning of Placer: 6 secs
Total CPU time at the beginning of Placer: 5 secs
Phase 1.1 Initial Placement Analysis
-Phase 1.1 Initial Placement Analysis (Checksum:743131b2) REAL time: 9 secs
+Phase 1.1 Initial Placement Analysis (Checksum:ecad4836) REAL time: 7 secs
Phase 2.7 Design Feasibility Check
-Phase 2.7 Design Feasibility Check (Checksum:743131b2) REAL time: 9 secs
+Phase 2.7 Design Feasibility Check (Checksum:ecad4836) REAL time: 7 secs
Phase 3.31 Local Placement Optimization
-Phase 3.31 Local Placement Optimization (Checksum:743131b2) REAL time: 9 secs
+Phase 3.31 Local Placement Optimization (Checksum:ecad4836) REAL time: 7 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
-(Checksum:743131b2) REAL time: 9 secs
+(Checksum:ecad4836) REAL time: 7 secs
Phase 5.36 Local Placement Optimization
-Phase 5.36 Local Placement Optimization (Checksum:743131b2) REAL time: 9 secs
+Phase 5.36 Local Placement Optimization (Checksum:ecad4836) REAL time: 7 secs
Phase 6.30 Global Clock Region Assignment
-Phase 6.30 Global Clock Region Assignment (Checksum:743131b2) REAL time: 9 secs
+Phase 6.30 Global Clock Region Assignment (Checksum:ecad4836) REAL time: 7 secs
Phase 7.3 Local Placement Optimization
-Phase 7.3 Local Placement Optimization (Checksum:743131b2) REAL time: 9 secs
+Phase 7.3 Local Placement Optimization (Checksum:ecad4836) REAL time: 7 secs
Phase 8.5 Local Placement Optimization
-Phase 8.5 Local Placement Optimization (Checksum:743131b2) REAL time: 9 secs
+Phase 8.5 Local Placement Optimization (Checksum:ecad4836) REAL time: 7 secs
Phase 9.8 Global Placement
..
..
-Phase 9.8 Global Placement (Checksum:46f7f38f) REAL time: 9 secs
+Phase 9.8 Global Placement (Checksum:59a47f53) REAL time: 7 secs
Phase 10.5 Local Placement Optimization
-Phase 10.5 Local Placement Optimization (Checksum:46f7f38f) REAL time: 9 secs
+Phase 10.5 Local Placement Optimization (Checksum:59a47f53) REAL time: 7 secs
Phase 11.18 Placement Optimization
-Phase 11.18 Placement Optimization (Checksum:9ea3640f) REAL time: 9 secs
+Phase 11.18 Placement Optimization (Checksum:87bc4903) REAL time: 7 secs
Phase 12.5 Local Placement Optimization
-Phase 12.5 Local Placement Optimization (Checksum:9ea3640f) REAL time: 10 secs
+Phase 12.5 Local Placement Optimization (Checksum:87bc4903) REAL time: 7 secs
Phase 13.34 Placement Validation
-Phase 13.34 Placement Validation (Checksum:9ea3640f) REAL time: 10 secs
+Phase 13.34 Placement Validation (Checksum:87bc4903) REAL time: 7 secs
-Total REAL time to Placer completion: 10 secs
-Total CPU time to Placer completion: 5 secs
+Total REAL time to Placer completion: 7 secs
+Total CPU time to Placer completion: 6 secs
Running post-placement packing...
Writing output files...
@@ -86,7 +86,7 @@ Slice Logic Utilization:
Number used as Memory: 0 out of 2,176 0%
Slice Logic Distribution:
- Number of occupied Slices: 5 out of 2,278 1%
+ Number of occupied Slices: 6 out of 2,278 1%
Nummber of MUXCYs used: 0 out of 4,556 0%
Number of LUT Flip Flop pairs used: 13
Number with an unused Flip Flop: 13 out of 13 100%
@@ -130,8 +130,8 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.32
-Peak Memory Usage: 352 MB
-Total REAL time to MAP completion: 11 secs
+Peak Memory Usage: 351 MB
+Total REAL time to MAP completion: 8 secs
Total CPU time to MAP completion: 6 secs
Mapping completed.
diff --git a/ALU_map.mrp b/ALU_map.mrp
index fa33483..44798c4 100755
--- a/ALU_map.mrp
+++ b/ALU_map.mrp
@@ -10,7 +10,7 @@ Target Device : xc6slx16
Target Package : csg324
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
-Mapped Date : Wed Feb 15 15:15:50 2012
+Mapped Date : Thu Feb 16 19:52:56 2012
Design Summary
--------------
@@ -27,7 +27,7 @@ Slice Logic Utilization:
Number used as Memory: 0 out of 2,176 0%
Slice Logic Distribution:
- Number of occupied Slices: 5 out of 2,278 1%
+ Number of occupied Slices: 6 out of 2,278 1%
Nummber of MUXCYs used: 0 out of 4,556 0%
Number of LUT Flip Flop pairs used: 13
Number with an unused Flip Flop: 13 out of 13 100%
@@ -71,8 +71,8 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.32
-Peak Memory Usage: 352 MB
-Total REAL time to MAP completion: 11 secs
+Peak Memory Usage: 351 MB
+Total REAL time to MAP completion: 8 secs
Total CPU time to MAP completion: 6 secs
Table of Contents
diff --git a/ALU_map.ncd b/ALU_map.ncd
index 34a2cbf..41d7376 100755
--- a/ALU_map.ncd
+++ b/ALU_map.ncd
@@ -1,3 +1,3 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
-###5580:XlxV32DM 35cd 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diff --git a/ALU_map.ngm b/ALU_map.ngm
index 4bfedaa..e3ef7bd 100755
--- a/ALU_map.ngm
+++ b/ALU_map.ngm
@@ -1,3 +1,3 @@
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\ No newline at end of file
diff --git a/ALU_map.xrpt b/ALU_map.xrpt
index 0af19e6..57b33c1 100755
--- a/ALU_map.xrpt
+++ b/ALU_map.xrpt
@@ -5,13 +5,13 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
- <application stringID="Map" timeStamp="Wed Feb 15 15:16:01 2012">
+ <application stringID="Map" timeStamp="Thu Feb 16 19:53:04 2012">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
- <item stringID="variable" value="PATH"/>
+ <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\13.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\13.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\13.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\13.3\ISE_DS\common\bin\nt64;C:\Xilinx\13.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\MATLAB\R2011a\runtime\win64;C:\Program Files\MATLAB\R2011a\bin;C:\VXIPNP\WinNT\Bin;C:\Program Files (x86)\Altium Designer Summer 09\System;C:\Program Files (x86)\QuickTime\QTSystem\;C:\Program Files\NetBeans 7.0.1\java\ant\bin;C:\Program Files\Java\jdk1.6.0_27\bin;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\Rational\Rose RealTime\bin\win32;C:\Program Files (x86)\Rational\common;C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:\Cadence\SPB_16.5\tools\Capture;C:\Cadence\SPB_16.5\tools\PSpice\Library;C:\Cadence\SPB_16.5\tools\PSpice;C:\Cadence\SPB_16.5\tools\specctra\bin;C:\Cadence\SPB_16.5\tools\fet\bin;C:\Cadence\SPB_16.5\tools\libutil\bin;C:\Cadence\SPB_16.5\tools\bin;C:\Cadence\SPB_16.5\tools\pcb\bin"/>
</row>
<row stringID="row" value="1">
@@ -43,7 +43,7 @@
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
</item>
- <item stringID="User_EnvHost" value="ECE-PHO115-09"/>
+ <item stringID="User_EnvHost" value="ECE-PHO115-08"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
@@ -121,8 +121,8 @@
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
- <item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="360720"/>
- <item stringID="MAP_TOTAL_REAL_TIME" value="11 secs "/>
+ <item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="358984"/>
+ <item stringID="MAP_TOTAL_REAL_TIME" value="8 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="6 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
@@ -155,10 +155,10 @@
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
- <item AVAILABLE="2278" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="5">
+ <item AVAILABLE="2278" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="6">
<item AVAILABLE="595" dataType="int" stringID="MAP_NUM_SLICEL" value="0"/>
<item AVAILABLE="544" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
- <item AVAILABLE="1139" dataType="int" stringID="MAP_NUM_SLICEX" value="5"/>
+ <item AVAILABLE="1139" dataType="int" stringID="MAP_NUM_SLICEX" value="6"/>
</item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="13">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="13"/>
diff --git a/ALU_ngdbuild.xrpt b/ALU_ngdbuild.xrpt
index bb02950..fad5196 100755
--- a/ALU_ngdbuild.xrpt
+++ b/ALU_ngdbuild.xrpt
@@ -5,13 +5,13 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
- <application stringID="NgdBuild" timeStamp="Wed Feb 15 15:15:47 2012">
+ <application stringID="NgdBuild" timeStamp="Thu Feb 16 19:52:52 2012">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
- <item stringID="variable" value="PATH"/>
+ <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\13.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\13.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\13.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\13.3\ISE_DS\common\bin\nt64;C:\Xilinx\13.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\MATLAB\R2011a\runtime\win64;C:\Program Files\MATLAB\R2011a\bin;C:\VXIPNP\WinNT\Bin;C:\Program Files (x86)\Altium Designer Summer 09\System;C:\Program Files (x86)\QuickTime\QTSystem\;C:\Program Files\NetBeans 7.0.1\java\ant\bin;C:\Program Files\Java\jdk1.6.0_27\bin;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\Rational\Rose RealTime\bin\win32;C:\Program Files (x86)\Rational\common;C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:\Cadence\SPB_16.5\tools\Capture;C:\Cadence\SPB_16.5\tools\PSpice\Library;C:\Cadence\SPB_16.5\tools\PSpice;C:\Cadence\SPB_16.5\tools\specctra\bin;C:\Cadence\SPB_16.5\tools\fet\bin;C:\Cadence\SPB_16.5\tools\libutil\bin;C:\Cadence\SPB_16.5\tools\bin;C:\Cadence\SPB_16.5\tools\pcb\bin"/>
</row>
<row stringID="row" value="1">
@@ -43,7 +43,7 @@
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
</item>
- <item stringID="User_EnvHost" value="ECE-PHO115-09"/>
+ <item stringID="User_EnvHost" value="ECE-PHO115-08"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
@@ -70,47 +70,39 @@
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
- <item dataType="int" stringID="NGDBUILD_NUM_AND2" value="22"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_AND2" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="21"/>
- <item dataType="int" stringID="NGDBUILD_NUM_AND4" value="2"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_AND4" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUF" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="6"/>
- <item dataType="int" stringID="NGDBUILD_NUM_INV" value="45"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_INV" value="53"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="4"/>
- <item dataType="int" stringID="NGDBUILD_NUM_NAND2" value="1"/>
- <item dataType="int" stringID="NGDBUILD_NUM_NAND3" value="1"/>
- <item dataType="int" stringID="NGDBUILD_NUM_NAND4" value="1"/>
- <item dataType="int" stringID="NGDBUILD_NUM_NOR3" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="12"/>
- <item dataType="int" stringID="NGDBUILD_NUM_OR2" value="7"/>
- <item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
- <item dataType="int" stringID="NGDBUILD_NUM_OR4" value="4"/>
- <item dataType="int" stringID="NGDBUILD_NUM_OR5" value="1"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_OR2" value="5"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_OR3" value="9"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_OR4" value="5"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_OR5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
- <item dataType="int" stringID="NGDBUILD_NUM_XNOR2" value="2"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_XNOR2" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="1"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
- <item dataType="int" stringID="NGDBUILD_NUM_AND2" value="22"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_AND2" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="21"/>
- <item dataType="int" stringID="NGDBUILD_NUM_AND4" value="2"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_AND4" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUF" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="6"/>
- <item dataType="int" stringID="NGDBUILD_NUM_INV" value="45"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_INV" value="53"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="4"/>
- <item dataType="int" stringID="NGDBUILD_NUM_NAND2" value="1"/>
- <item dataType="int" stringID="NGDBUILD_NUM_NAND3" value="1"/>
- <item dataType="int" stringID="NGDBUILD_NUM_NAND4" value="1"/>
- <item dataType="int" stringID="NGDBUILD_NUM_NOR3" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="12"/>
- <item dataType="int" stringID="NGDBUILD_NUM_OR2" value="7"/>
- <item dataType="int" stringID="NGDBUILD_NUM_OR3" value="10"/>
- <item dataType="int" stringID="NGDBUILD_NUM_OR4" value="4"/>
- <item dataType="int" stringID="NGDBUILD_NUM_OR5" value="1"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_OR2" value="5"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_OR3" value="9"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_OR4" value="5"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_OR5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
- <item dataType="int" stringID="NGDBUILD_NUM_XNOR2" value="2"/>
+ <item dataType="int" stringID="NGDBUILD_NUM_XNOR2" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XOR2" value="1"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
diff --git a/ALU_pad.csv b/ALU_pad.csv
index baff75f..5adfef1 100755
--- a/ALU_pad.csv
+++ b/ALU_pad.csv
@@ -1,7 +1,7 @@
#Release 13.3 - par O.76xd (nt64)
#Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
-#Wed Feb 15 15:16:12 2012
+#Thu Feb 16 19:53:16 2012
#
## NOTE: This file is designed to be imported into a spreadsheet program
@@ -26,7 +26,7 @@ A4,,IOBS,IO_L5N_0,UNUSED,,0,,,,,,,,,
A5,,IOBS,IO_L6N_0,UNUSED,,0,,,,,,,,,
A6,,IOBS,IO_L8N_VREF_0,UNUSED,,0,,,,,,,,,
A7,,IOBS,IO_L10N_0,UNUSED,,0,,,,,,,,,
-A8,C,IOB,IO_L33N_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
+A8,,IOBS,IO_L33N_0,UNUSED,,0,,,,,,,,,
A9,,IOBS,IO_L35N_GCLK16_0,UNUSED,,0,,,,,,,,,
A10,,IOBS,IO_L37N_GCLK12_0,UNUSED,,0,,,,,,,,,
A11,,IOBS,IO_L39N_0,UNUSED,,0,,,,,,,,,
@@ -58,12 +58,12 @@ B18,,,TMS,,,,,,,,,,,,
C1,,IOBS,IO_L83N_VREF_3,UNUSED,,3,,,,,,,,,
C2,,IOBM,IO_L83P_3,UNUSED,,3,,,,,,,,,
C3,,,GND,,,,,,,,,,,,
-C4,,IOBS,IO_L1N_VREF_0,UNUSED,,0,,,,,,,,,
+C4,A,IOB,IO_L1N_VREF_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
C5,,IOBM,IO_L6P_0,UNUSED,,0,,,,,,,,,
C6,,IOBS,IO_L3N_0,UNUSED,,0,,,,,,,,,
C7,,IOBM,IO_L10P_0,UNUSED,,0,,,,,,,,,
C8,,IOBS,IO_L11N_0,UNUSED,,0,,,,,,,,,
-C9,A,IOB,IO_L34N_GCLK18_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
+C9,D,IOB,IO_L34N_GCLK18_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
C10,,IOBM,IO_L37P_GCLK13_0,UNUSED,,0,,,,,,,,,
C11,,IOBS,IO_L36N_GCLK14_0,UNUSED,,0,,,,,,,,,
C12,,IOBS,IO_L47N_0,UNUSED,,0,,,,,,,,,
@@ -81,7 +81,7 @@ D5,,,GND,,,,,,,,,,,,
D6,,IOBM,IO_L3P_0,UNUSED,,0,,,,,,,,,
D7,,,VCCO_0,,,0,,,,,any******,,,,
D8,,IOBM,IO_L11P_0,UNUSED,,0,,,,,,,,,
-D9,D,IOB,IO_L34P_GCLK19_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
+D9,C,IOB,IO_L34P_GCLK19_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
D10,,,GND,,,,,,,,,,,,
D11,,IOBM,IO_L36P_GCLK15_0,UNUSED,,0,,,,,,,,,
D12,,IOBM,IO_L47P_0,UNUSED,,0,,,,,,,,,
diff --git a/ALU_pad.txt b/ALU_pad.txt
index 1a30998..1085c83 100755
--- a/ALU_pad.txt
+++ b/ALU_pad.txt
@@ -1,7 +1,7 @@
Release 13.3 - par O.76xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
-Wed Feb 15 15:16:19 2012
+Thu Feb 16 19:53:22 2012
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
@@ -27,7 +27,7 @@ Pinout by Pin Number:
|A5 | |IOBS |IO_L6N_0 |UNUSED | |0 | | | | | | | | |
|A6 | |IOBS |IO_L8N_VREF_0 |UNUSED | |0 | | | | | | | | |
|A7 | |IOBS |IO_L10N_0 |UNUSED | |0 | | | | | | | | |
-|A8 |C |IOB |IO_L33N_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
+|A8 | |IOBS |IO_L33N_0 |UNUSED | |0 | | | | | | | | |
|A9 | |IOBS |IO_L35N_GCLK16_0 |UNUSED | |0 | | | | | | | | |
|A10 | |IOBS |IO_L37N_GCLK12_0 |UNUSED | |0 | | | | | | | | |
|A11 | |IOBS |IO_L39N_0 |UNUSED | |0 | | | | | | | | |
@@ -59,12 +59,12 @@ Pinout by Pin Number:
|C1 | |IOBS |IO_L83N_VREF_3 |UNUSED | |3 | | | | | | | | |
|C2 | |IOBM |IO_L83P_3 |UNUSED | |3 | | | | | | | | |
|C3 | | |GND | | | | | | | | | | | |
-|C4 | |IOBS |IO_L1N_VREF_0 |UNUSED | |0 | | | | | | | | |
+|C4 |A |IOB |IO_L1N_VREF_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
|C5 | |IOBM |IO_L6P_0 |UNUSED | |0 | | | | | | | | |
|C6 | |IOBS |IO_L3N_0 |UNUSED | |0 | | | | | | | | |
|C7 | |IOBM |IO_L10P_0 |UNUSED | |0 | | | | | | | | |
|C8 | |IOBS |IO_L11N_0 |UNUSED | |0 | | | | | | | | |
-|C9 |A |IOB |IO_L34N_GCLK18_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
+|C9 |D |IOB |IO_L34N_GCLK18_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
|C10 | |IOBM |IO_L37P_GCLK13_0 |UNUSED | |0 | | | | | | | | |
|C11 | |IOBS |IO_L36N_GCLK14_0 |UNUSED | |0 | | | | | | | | |
|C12 | |IOBS |IO_L47N_0 |UNUSED | |0 | | | | | | | | |
@@ -82,7 +82,7 @@ Pinout by Pin Number:
|D6 | |IOBM |IO_L3P_0 |UNUSED | |0 | | | | | | | | |
|D7 | | |VCCO_0 | | |0 | | | | |any******| | | |
|D8 | |IOBM |IO_L11P_0 |UNUSED | |0 | | | | | | | | |
-|D9 |D |IOB |IO_L34P_GCLK19_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
+|D9 |C |IOB |IO_L34P_GCLK19_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
|D10 | | |GND | | | | | | | | | | | |
|D11 | |IOBM |IO_L36P_GCLK15_0 |UNUSED | |0 | | | | | | | | |
|D12 | |IOBM |IO_L47P_0 |UNUSED | |0 | | | | | | | | |
diff --git a/ALU_par.xrpt b/ALU_par.xrpt
index 41f4b3e..d089c4e 100755
--- a/ALU_par.xrpt
+++ b/ALU_par.xrpt
@@ -5,13 +5,13 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
- <application stringID="par" timeStamp="Wed Feb 15 15:16:09 2012">
+ <application stringID="par" timeStamp="Thu Feb 16 19:53:13 2012">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
- <item stringID="variable" value="PATH"/>
+ <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\13.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\13.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\13.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\13.3\ISE_DS\common\bin\nt64;C:\Xilinx\13.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\MATLAB\R2011a\runtime\win64;C:\Program Files\MATLAB\R2011a\bin;C:\VXIPNP\WinNT\Bin;C:\Program Files (x86)\Altium Designer Summer 09\System;C:\Program Files (x86)\QuickTime\QTSystem\;C:\Program Files\NetBeans 7.0.1\java\ant\bin;C:\Program Files\Java\jdk1.6.0_27\bin;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\Rational\Rose RealTime\bin\win32;C:\Program Files (x86)\Rational\common;C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:\Cadence\SPB_16.5\tools\Capture;C:\Cadence\SPB_16.5\tools\PSpice\Library;C:\Cadence\SPB_16.5\tools\PSpice;C:\Cadence\SPB_16.5\tools\specctra\bin;C:\Cadence\SPB_16.5\tools\fet\bin;C:\Cadence\SPB_16.5\tools\libutil\bin;C:\Cadence\SPB_16.5\tools\bin;C:\Cadence\SPB_16.5\tools\pcb\bin"/>
</row>
<row stringID="row" value="1">
@@ -43,7 +43,7 @@
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
</item>
- <item stringID="User_EnvHost" value="ECE-PHO115-09"/>
+ <item stringID="User_EnvHost" value="ECE-PHO115-08"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
@@ -67,7 +67,7 @@
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="6 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
- <item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="19 secs "/>
+ <item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="16 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="7 secs "/>
</section>
</task>
@@ -137,16 +137,10 @@
</row>
<row stringID="row" value="8">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="A8"/>
- <item label="Signal&#xA;Name" stringID="Signal_Name" value="C"/>
- <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
+ <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L33N_0"/>
- <item stringID="Direction" value="INPUT"/>
- <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
+ <item stringID="Direction" value="UNUSED"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
- <item label="IOB&#xA;Delay" stringID="IOB_Delay" value="NONE"/>
- <item label="Constraint" stringID="Constraint" value="LOCATED"/>
- <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
- <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="9">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="A9"/>
@@ -348,10 +342,16 @@
</row>
<row stringID="row" value="40">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="C4"/>
- <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
+ <item label="Signal&#xA;Name" stringID="Signal_Name" value="A"/>
+ <item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L1N_VREF_0"/>
- <item stringID="Direction" value="UNUSED"/>
+ <item stringID="Direction" value="INPUT"/>
+ <item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
+ <item label="IOB&#xA;Delay" stringID="IOB_Delay" value="NONE"/>
+ <item label="Constraint" stringID="Constraint" value="LOCATED"/>
+ <item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
+ <item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="41">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="C5"/>
@@ -383,7 +383,7 @@
</row>
<row stringID="row" value="45">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="C9"/>
- <item label="Signal&#xA;Name" stringID="Signal_Name" value="A"/>
+ <item label="Signal&#xA;Name" stringID="Signal_Name" value="D"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L34N_GCLK18_0"/>
<item stringID="Direction" value="INPUT"/>
@@ -508,7 +508,7 @@
</row>
<row stringID="row" value="63">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="D9"/>
- <item label="Signal&#xA;Name" stringID="Signal_Name" value="D"/>
+ <item label="Signal&#xA;Name" stringID="Signal_Name" value="C"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L34P_GCLK19_0"/>
<item stringID="Direction" value="INPUT"/>
@@ -2287,13 +2287,13 @@
</task>
</application>
- <application stringID="Par" timeStamp="Wed Feb 15 15:16:09 2012">
+ <application stringID="Par" timeStamp="Thu Feb 16 19:53:13 2012">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
- <item stringID="variable" value="PATH"/>
+ <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\13.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\13.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\13.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\13.3\ISE_DS\common\bin\nt64;C:\Xilinx\13.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\MATLAB\R2011a\runtime\win64;C:\Program Files\MATLAB\R2011a\bin;C:\VXIPNP\WinNT\Bin;C:\Program Files (x86)\Altium Designer Summer 09\System;C:\Program Files (x86)\QuickTime\QTSystem\;C:\Program Files\NetBeans 7.0.1\java\ant\bin;C:\Program Files\Java\jdk1.6.0_27\bin;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\Rational\Rose RealTime\bin\win32;C:\Program Files (x86)\Rational\common;C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:\Cadence\SPB_16.5\tools\Capture;C:\Cadence\SPB_16.5\tools\PSpice\Library;C:\Cadence\SPB_16.5\tools\PSpice;C:\Cadence\SPB_16.5\tools\specctra\bin;C:\Cadence\SPB_16.5\tools\fet\bin;C:\Cadence\SPB_16.5\tools\libutil\bin;C:\Cadence\SPB_16.5\tools\bin;C:\Cadence\SPB_16.5\tools\pcb\bin"/>
</row>
<row stringID="row" value="1">
@@ -2325,7 +2325,7 @@
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
</item>
- <item stringID="User_EnvHost" value="ECE-PHO115-09"/>
+ <item stringID="User_EnvHost" value="ECE-PHO115-08"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
@@ -2366,10 +2366,10 @@
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
- <item AVAILABLE="2278" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="5">
+ <item AVAILABLE="2278" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="6">
<item AVAILABLE="595" dataType="int" stringID="PAR_NUM_SLICEL" value="0"/>
<item AVAILABLE="544" dataType="int" stringID="PAR_NUM_SLICEM" value="0"/>
- <item AVAILABLE="1139" dataType="int" stringID="PAR_NUM_SLICEX" value="5"/>
+ <item AVAILABLE="1139" dataType="int" stringID="PAR_NUM_SLICEX" value="6"/>
</item>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="13">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="13"/>
diff --git a/ALU_summary.html b/ALU_summary.html
index 840a7a1..dd1ef6d 100755
--- a/ALU_summary.html
+++ b/ALU_summary.html
@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>ALU Project Status</B></TD></TR>
+<TD ALIGN=CENTER COLSPAN='4'><B>ALU Project Status (02/16/2012 - 18:30:33)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>lab1.xise</TD>
@@ -13,26 +13,25 @@
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>ALU</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
-<TD>Placed and Routed</TD>
+<TD>Mapped</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx16-3csg324</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
-<TD>
-No Errors</TD>
+<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.3</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
-<TD ALIGN=LEFT><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/_xmsgs/*.xmsgs?&DataKey=Warning'>2 Warnings (0 new)</A></TD>
+<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
-<A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/ALU.unroutes'>All Signals Completely Routed</A></TD>
+&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
@@ -43,11 +42,11 @@ No Errors</TD>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
-<A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/ALU_envsettings.html'>
+<A HREF_DISABLED='X:/My Documents/ec311/ec311-lab1\ALU_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
-<TD>0 &nbsp;<A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/ALU.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
+<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
@@ -107,7 +106,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
-<TD ALIGN=RIGHT>5</TD>
+<TD ALIGN=RIGHT>7</TD>
<TD ALIGN=RIGHT>2,278</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -148,7 +147,7 @@ System Settings</A>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
-<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/ALU_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='X:/My Documents/ec311/ec311-lab1\ALU_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>18</TD>
<TD ALIGN=RIGHT>232</TD>
<TD ALIGN=RIGHT>7%</TD>
@@ -287,7 +286,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
-<TD ALIGN=RIGHT>3.32</TD>
+<TD ALIGN=RIGHT>3.26</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -296,26 +295,7 @@ System Settings</A>
-&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
-<TD>0 (Setup: 0, Hold: 0)</TD>
-<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
-<TD COLSPAN='2'><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/ALU_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
-<A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/ALU.unroutes'>All Signals Completely Routed</A></TD>
-<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
-<TD COLSPAN='2'><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/ALU_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
-<TD>&nbsp;</TD>
-<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
-<TD COLSPAN='2'>&nbsp;</TD>
-</TABLE>
+
@@ -323,21 +303,21 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/ALU.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Feb 15 18:59:45 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/_xmsgs/xst.xmsgs?&DataKey=Warning'>2 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/ALU.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Feb 15 18:59:45 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/ALU_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Feb 15 18:59:45 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/_xmsgs/map.xmsgs?&DataKey=Info'>6 Infos (6 new)</A></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/ALU.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Feb 15 18:59:46 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/_xmsgs/par.xmsgs?&DataKey=Info'>2 Infos (2 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='X:/My Documents/ec311/ec311-lab1\ALU.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Feb 16 18:30:08 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='X:/My Documents/ec311/ec311-lab1\_xmsgs/xst.xmsgs?&DataKey=Warning'>2 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='X:/My Documents/ec311/ec311-lab1\ALU.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Feb 16 18:30:17 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='X:/My Documents/ec311/ec311-lab1\ALU_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Feb 16 18:30:30 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='X:/My Documents/ec311/ec311-lab1\ALU.par'>Place and Route Report</A></TD><TD>Out of Date</TD><TD>Thu Feb 16 18:19:18 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='X:/My Documents/ec311/ec311-lab1\_xmsgs/par.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/ALU.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Feb 15 18:59:46 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
-<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='X:/My Documents/ec311/ec311-lab1\ALU.twr'>Post-PAR Static Timing Report</A></TD><TD>Out of Date</TD><TD>Thu Feb 16 18:19:28 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='X:/My Documents/ec311/ec311-lab1\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='X:/My Documents/ec311/ec311-lab1\ALU.bgn'>Bitgen Report</A></TD><TD>Out of Date</TD><TD>Thu Feb 16 18:19:51 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='X:/My Documents/ec311/ec311-lab1\_xmsgs/bitgen.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Feb 15 18:59:48 2012</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab1/webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Feb 15 18:59:48 2012</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='X:/My Documents/ec311/ec311-lab1\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu Feb 16 18:19:55 2012</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='X:/My Documents/ec311/ec311-lab1\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu Feb 16 18:20:07 2012</TD></TR>
</TABLE>
-<br><center><b>Date Generated:</b> 02/15/2012 - 19:01:09</center>
+<br><center><b>Date Generated:</b> 02/16/2012 - 18:37:40</center>
</BODY></HTML> \ No newline at end of file
diff --git a/ALU_summary.xml b/ALU_summary.xml
index fb30df9..2bacdf8 100755
--- a/ALU_summary.xml
+++ b/ALU_summary.xml
@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
-<DesignSummary rev="2">
+<DesignSummary rev="23">
<CmdHistory>
</CmdHistory>
</DesignSummary>
diff --git a/ALU_usage.xml b/ALU_usage.xml
index 333ec93..2bf179f 100755
--- a/ALU_usage.xml
+++ b/ALU_usage.xml
@@ -4,242 +4,246 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
-<DeviceUsageSummary rev="2">
-<DesignStatistics TimeStamp="Wed Feb 15 15:16:54 2012"><group name="NetStatistics">
-<item name="NumNets_Active" rev="2">
+<DeviceUsageSummary rev="23">
+<DesignStatistics TimeStamp="Thu Feb 16 19:53:54 2012"><group name="NetStatistics">
+<item name="NumNets_Active" rev="23">
<attrib name="value" value="37"/></item>
-<item name="NumNets_Gnd" rev="2">
+<item name="NumNets_Gnd" rev="23">
<attrib name="value" value="1"/></item>
-<item name="NumNets_Vcc" rev="2">
+<item name="NumNets_Vcc" rev="23">
<attrib name="value" value="1"/></item>
-<item name="NumNodesOfType_Active_BOUNCEIN" rev="2">
+<item name="NumNodesOfType_Active_BOUNCEIN" rev="23">
<attrib name="value" value="1"/></item>
-<item name="NumNodesOfType_Active_DOUBLE" rev="2">
-<attrib name="value" value="22"/></item>
-<item name="NumNodesOfType_Active_GENERIC" rev="2">
+<item name="NumNodesOfType_Active_DOUBLE" rev="23">
+<attrib name="value" value="24"/></item>
+<item name="NumNodesOfType_Active_GENERIC" rev="23">
<attrib name="value" value="20"/></item>
-<item name="NumNodesOfType_Active_IOBIN2OUT" rev="2">
+<item name="NumNodesOfType_Active_IOBIN2OUT" rev="23">
<attrib name="value" value="14"/></item>
-<item name="NumNodesOfType_Active_IOBOUTPUT" rev="2">
+<item name="NumNodesOfType_Active_IOBOUTPUT" rev="23">
<attrib name="value" value="14"/></item>
-<item name="NumNodesOfType_Active_LUTINPUT" rev="2">
+<item name="NumNodesOfType_Active_LUTINPUT" rev="23">
<attrib name="value" value="55"/></item>
-<item name="NumNodesOfType_Active_OUTBOUND" rev="2">
+<item name="NumNodesOfType_Active_OUTBOUND" rev="23">
<attrib name="value" value="26"/></item>
-<item name="NumNodesOfType_Active_OUTPUT" rev="2">
+<item name="NumNodesOfType_Active_OUTPUT" rev="23">
<attrib name="value" value="14"/></item>
-<item name="NumNodesOfType_Active_PADINPUT" rev="2">
+<item name="NumNodesOfType_Active_PADINPUT" rev="23">
<attrib name="value" value="8"/></item>
-<item name="NumNodesOfType_Active_PADOUTPUT" rev="2">
+<item name="NumNodesOfType_Active_PADOUTPUT" rev="23">
<attrib name="value" value="6"/></item>
-<item name="NumNodesOfType_Active_PINBOUNCE" rev="2">
-<attrib name="value" value="6"/></item>
-<item name="NumNodesOfType_Active_PINFEED" rev="2">
+<item name="NumNodesOfType_Active_PINBOUNCE" rev="23">
+<attrib name="value" value="3"/></item>
+<item name="NumNodesOfType_Active_PINFEED" rev="23">
<attrib name="value" value="63"/></item>
-<item name="NumNodesOfType_Active_QUAD" rev="2">
-<attrib name="value" value="107"/></item>
-<item name="NumNodesOfType_Active_SINGLE" rev="2">
-<attrib name="value" value="25"/></item>
-<item name="NumNodesOfType_Gnd_GENERIC" rev="2">
+<item name="NumNodesOfType_Active_QUAD" rev="23">
+<attrib name="value" value="108"/></item>
+<item name="NumNodesOfType_Active_SINGLE" rev="23">
+<attrib name="value" value="27"/></item>
+<item name="NumNodesOfType_Gnd_GENERIC" rev="23">
<attrib name="value" value="1"/></item>
-<item name="NumNodesOfType_Gnd_IOBIN2OUT" rev="2">
+<item name="NumNodesOfType_Gnd_IOBIN2OUT" rev="23">
<attrib name="value" value="1"/></item>
-<item name="NumNodesOfType_Gnd_IOBOUTPUT" rev="2">
+<item name="NumNodesOfType_Gnd_IOBOUTPUT" rev="23">
<attrib name="value" value="1"/></item>
-<item name="NumNodesOfType_Gnd_OUTBOUND" rev="2">
+<item name="NumNodesOfType_Gnd_OUTBOUND" rev="23">
<attrib name="value" value="1"/></item>
-<item name="NumNodesOfType_Gnd_OUTPUT" rev="2">
+<item name="NumNodesOfType_Gnd_OUTPUT" rev="23">
<attrib name="value" value="1"/></item>
-<item name="NumNodesOfType_Gnd_PADINPUT" rev="2">
+<item name="NumNodesOfType_Gnd_PADINPUT" rev="23">
<attrib name="value" value="1"/></item>
-<item name="NumNodesOfType_Gnd_PINFEED" rev="2">
+<item name="NumNodesOfType_Gnd_PINFEED" rev="23">
<attrib name="value" value="1"/></item>
-<item name="NumNodesOfType_Gnd_SINGLE" rev="2">
+<item name="NumNodesOfType_Gnd_SINGLE" rev="23">
<attrib name="value" value="1"/></item>
-<item name="NumNodesOfType_Vcc_GENERIC" rev="2">
+<item name="NumNodesOfType_Vcc_GENERIC" rev="23">
<attrib name="value" value="3"/></item>
-<item name="NumNodesOfType_Vcc_HVCCOUT" rev="2">
+<item name="NumNodesOfType_Vcc_HVCCOUT" rev="23">
<attrib name="value" value="2"/></item>
-<item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="2">
+<item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="23">
<attrib name="value" value="3"/></item>
-<item name="NumNodesOfType_Vcc_IOBOUTPUT" rev="2">
+<item name="NumNodesOfType_Vcc_IOBOUTPUT" rev="23">
<attrib name="value" value="3"/></item>
-<item name="NumNodesOfType_Vcc_PADINPUT" rev="2">
+<item name="NumNodesOfType_Vcc_PADINPUT" rev="23">
<attrib name="value" value="3"/></item>
-<item name="NumNodesOfType_Vcc_PINFEED" rev="2">
+<item name="NumNodesOfType_Vcc_PINFEED" rev="23">
<attrib name="value" value="3"/></item>
</group>
<group name="SiteStatistics">
-<item name="IOB-IOBM" rev="2">
+<item name="IOB-IOBM" rev="23">
<attrib name="value" value="9"/></item>
-<item name="IOB-IOBS" rev="2">
+<item name="IOB-IOBS" rev="23">
<attrib name="value" value="9"/></item>
-<item name="IOB-UNPLACED" rev="2">
+<item name="IOB-UNPLACED" rev="23">
<attrib name="value" value="14"/></item>
-<item name="SLICEX-SLICEM" rev="2">
-<attrib name="value" value="4"/></item>
+<item name="SLICEX-SLICEL" rev="23">
+<attrib name="value" value="2"/></item>
+<item name="SLICEX-SLICEM" rev="23">
+<attrib name="value" value="1"/></item>
</group>
<group name="MiscellaneousStatistics">
-<item name="AGG_BONDED_IO" rev="1">
+<item name="AGG_BONDED_IO" rev="22">
<attrib name="value" value="18"/></item>
-<item name="AGG_IO" rev="1">
+<item name="AGG_IO" rev="22">
<attrib name="value" value="18"/></item>
-<item name="AGG_LOCED_IO" rev="1">
+<item name="AGG_LOCED_IO" rev="22">
<attrib name="value" value="18"/></item>
-<item name="AGG_SLICE" rev="1">
-<attrib name="value" value="5"/></item>
-<item name="NUM_BONDED_IOB" rev="1">
+<item name="AGG_SLICE" rev="22">
+<attrib name="value" value="6"/></item>
+<item name="NUM_BONDED_IOB" rev="22">
<attrib name="value" value="18"/></item>
-<item name="NUM_BSLUTONLY" rev="1">
+<item name="NUM_BSLUTONLY" rev="22">
<attrib name="value" value="13"/></item>
-<item name="NUM_BSUSED" rev="1">
+<item name="NUM_BSUSED" rev="22">
<attrib name="value" value="13"/></item>
-<item name="NUM_LOCED_IOB" rev="1">
+<item name="NUM_LOCED_IOB" rev="22">
<attrib name="value" value="18"/></item>
-<item name="NUM_LOGIC_O6ONLY" rev="1">
+<item name="NUM_LOGIC_O6ONLY" rev="22">
<attrib name="value" value="13"/></item>
-<item name="NUM_SLICEX" rev="1">
-<attrib name="value" value="5"/></item>
-<item name="NUM_SLICE_CYINIT" rev="1">
+<item name="NUM_SLICEX" rev="22">
+<attrib name="value" value="6"/></item>
+<item name="NUM_SLICE_CYINIT" rev="22">
<attrib name="value" value="13"/></item>
-<item name="NUM_SLICE_UNUSEDCTRL" rev="1">
-<attrib name="value" value="5"/></item>
+<item name="NUM_SLICE_UNUSEDCTRL" rev="22">
+<attrib name="value" value="6"/></item>
</group>
</DesignStatistics>
-<DeviceUsage TimeStamp="Wed Feb 15 15:16:54 2012"><group name="SiteSummary">
-<item name="IOB" rev="2">
+<DeviceUsage TimeStamp="Thu Feb 16 19:53:54 2012"><group name="SiteSummary">
+<item name="IOB" rev="23">
<attrib name="total" value="1000000"/><attrib name="used" value="32"/></item>
-<item name="IOB_IMUX" rev="2">
+<item name="IOB_IMUX" rev="23">
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item>
-<item name="IOB_INBUF" rev="2">
+<item name="IOB_INBUF" rev="23">
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item>
-<item name="IOB_OUTBUF" rev="2">
+<item name="IOB_OUTBUF" rev="23">
<attrib name="total" value="1000000"/><attrib name="used" value="23"/></item>
-<item name="LUT6" rev="2">
+<item name="LUT6" rev="23">
<attrib name="total" value="1000000"/><attrib name="used" value="13"/></item>
-<item name="PAD" rev="2">
+<item name="PAD" rev="23">
<attrib name="total" value="1000000"/><attrib name="used" value="32"/></item>
-<item name="PULL_OR_KEEP1" rev="2">
+<item name="PULL_OR_KEEP1" rev="23">
<attrib name="total" value="1000000"/><attrib name="used" value="12"/></item>
-<item name="SLICEX" rev="2">
-<attrib name="total" value="1000000"/><attrib name="used" value="5"/></item>
+<item name="SLICEX" rev="23">
+<attrib name="total" value="1000000"/><attrib name="used" value="6"/></item>
</group>
</DeviceUsage>
-<ReportConfigData TimeStamp="Wed Feb 15 15:16:54 2012"><group name="IOB_OUTBUF">
-<item name="DRIVEATTRBOX" rev="2">
+<ReportConfigData TimeStamp="Thu Feb 16 19:53:54 2012"><group name="IOB_OUTBUF">
+<item name="DRIVEATTRBOX" rev="23">
<attrib name="12" value="23"/></item>
-<item name="SLEW" rev="2">
+<item name="SLEW" rev="23">
<attrib name="SLOW" value="23"/></item>
-<item name="SUSPEND" rev="2">
+<item name="SUSPEND" rev="23">
<attrib name="3STATE" value="12"/></item>
</group>
<group name="PULL_OR_KEEP1">
-<item name="PULLTYPE" rev="2">
+<item name="PULLTYPE" rev="23">
<attrib name="PULLUP" value="12"/></item>
</group>
</ReportConfigData>
-<ReportPinData TimeStamp="Wed Feb 15 15:16:54 2012"><group name="IOB_OUTBUF">
-<item name="IN" rev="2">
+<ReportPinData TimeStamp="Thu Feb 16 19:53:54 2012"><group name="IOB_OUTBUF">
+<item name="IN" rev="23">
<attrib name="value" value="23"/></item>
-<item name="OUT" rev="2">
+<item name="OUT" rev="23">
<attrib name="value" value="23"/></item>
-<item name="TRI" rev="2">
+<item name="TRI" rev="23">
<attrib name="value" value="11"/></item>
</group>
<group name="SLICEX">
-<item name="A" rev="2">
-<attrib name="value" value="3"/></item>
-<item name="A3" rev="2">
+<item name="A" rev="23">
<attrib name="value" value="3"/></item>
-<item name="A4" rev="2">
+<item name="A3" rev="23">
+<attrib name="value" value="2"/></item>
+<item name="A4" rev="23">
+<attrib name="value" value="2"/></item>
+<item name="A5" rev="23">
<attrib name="value" value="3"/></item>
-<item name="A5" rev="2">
+<item name="A6" rev="23">
<attrib name="value" value="3"/></item>
-<item name="A6" rev="2">
+<item name="B" rev="23">
<attrib name="value" value="3"/></item>
-<item name="B" rev="2">
-<attrib name="value" value="2"/></item>
-<item name="B1" rev="2">
+<item name="B1" rev="23">
<attrib name="value" value="2"/></item>
-<item name="B2" rev="2">
+<item name="B2" rev="23">
<attrib name="value" value="2"/></item>
-<item name="B3" rev="2">
-<attrib name="value" value="2"/></item>
-<item name="B4" rev="2">
+<item name="B3" rev="23">
+<attrib name="value" value="3"/></item>
+<item name="B4" rev="23">
+<attrib name="value" value="3"/></item>
+<item name="B5" rev="23">
+<attrib name="value" value="3"/></item>
+<item name="B6" rev="23">
+<attrib name="value" value="3"/></item>
+<item name="C" rev="23">
+<attrib name="value" value="3"/></item>
+<item name="C1" rev="23">
+<attrib name="value" value="1"/></item>
+<item name="C2" rev="23">
<attrib name="value" value="2"/></item>
-<item name="B5" rev="2">
+<item name="C3" rev="23">
<attrib name="value" value="2"/></item>
-<item name="B6" rev="2">
+<item name="C4" rev="23">
<attrib name="value" value="2"/></item>
-<item name="C" rev="2">
+<item name="C5" rev="23">
<attrib name="value" value="3"/></item>
-<item name="C2" rev="2">
-<attrib name="value" value="1"/></item>
-<item name="C3" rev="2">
+<item name="C6" rev="23">
+<attrib name="value" value="3"/></item>
+<item name="D" rev="23">
+<attrib name="value" value="4"/></item>
+<item name="D1" rev="23">
<attrib name="value" value="1"/></item>
-<item name="C4" rev="2">
+<item name="D2" rev="23">
<attrib name="value" value="1"/></item>
-<item name="C5" rev="2">
+<item name="D3" rev="23">
<attrib name="value" value="3"/></item>
-<item name="C6" rev="2">
+<item name="D4" rev="23">
<attrib name="value" value="3"/></item>
-<item name="D" rev="2">
-<attrib name="value" value="5"/></item>
-<item name="D1" rev="2">
-<attrib name="value" value="2"/></item>
-<item name="D2" rev="2">
-<attrib name="value" value="2"/></item>
-<item name="D3" rev="2">
+<item name="D5" rev="23">
<attrib name="value" value="4"/></item>
-<item name="D4" rev="2">
+<item name="D6" rev="23">
<attrib name="value" value="4"/></item>
-<item name="D5" rev="2">
-<attrib name="value" value="5"/></item>
-<item name="D6" rev="2">
-<attrib name="value" value="5"/></item>
</group>
<group name="PULL_OR_KEEP1">
-<item name="PAD" rev="2">
+<item name="PAD" rev="23">
<attrib name="value" value="12"/></item>
</group>
<group name="PAD">
-<item name="PAD" rev="2">
+<item name="PAD" rev="23">
<attrib name="value" value="32"/></item>
</group>
<group name="IOB_INBUF">
-<item name="OUT" rev="2">
+<item name="OUT" rev="23">
<attrib name="value" value="18"/></item>
-<item name="PAD" rev="2">
+<item name="PAD" rev="23">
<attrib name="value" value="18"/></item>
</group>
<group name="LUT6">
-<item name="A1" rev="2">
+<item name="A1" rev="23">
<attrib name="value" value="4"/></item>
-<item name="A2" rev="2">
+<item name="A2" rev="23">
<attrib name="value" value="5"/></item>
-<item name="A3" rev="2">
+<item name="A3" rev="23">
<attrib name="value" value="10"/></item>
-<item name="A4" rev="2">
+<item name="A4" rev="23">
<attrib name="value" value="10"/></item>
-<item name="A5" rev="2">
+<item name="A5" rev="23">
<attrib name="value" value="13"/></item>
-<item name="A6" rev="2">
+<item name="A6" rev="23">
<attrib name="value" value="13"/></item>
-<item name="O6" rev="2">
+<item name="O6" rev="23">
<attrib name="value" value="13"/></item>
</group>
<group name="IOB_IMUX">
-<item name="I" rev="2">
+<item name="I" rev="23">
<attrib name="value" value="18"/></item>
-<item name="OUT" rev="2">
+<item name="OUT" rev="23">
<attrib name="value" value="18"/></item>
</group>
<group name="IOB">
-<item name="I" rev="2">
+<item name="I" rev="23">
<attrib name="value" value="6"/></item>
-<item name="O" rev="2">
+<item name="O" rev="23">
<attrib name="value" value="12"/></item>
-<item name="PAD" rev="2">
+<item name="PAD" rev="23">
<attrib name="value" value="18"/></item>
</group>
</ReportPinData>
diff --git a/ALU_xst.xrpt b/ALU_xst.xrpt
index 9b982ba..c3ab59a 100755
--- a/ALU_xst.xrpt
+++ b/ALU_xst.xrpt
@@ -5,13 +5,13 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
- <application stringID="Xst" timeStamp="Wed Feb 15 15:15:31 2012">
+ <application stringID="Xst" timeStamp="Thu Feb 16 19:52:37 2012">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
- <item stringID="variable" value="PATH"/>
+ <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\13.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\13.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\13.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\13.3\ISE_DS\common\bin\nt64;C:\Xilinx\13.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\MATLAB\R2011a\runtime\win64;C:\Program Files\MATLAB\R2011a\bin;C:\VXIPNP\WinNT\Bin;C:\Program Files (x86)\Altium Designer Summer 09\System;C:\Program Files (x86)\QuickTime\QTSystem\;C:\Program Files\NetBeans 7.0.1\java\ant\bin;C:\Program Files\Java\jdk1.6.0_27\bin;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\Rational\Rose RealTime\bin\win32;C:\Program Files (x86)\Rational\common;C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:\Cadence\SPB_16.5\tools\Capture;C:\Cadence\SPB_16.5\tools\PSpice\Library;C:\Cadence\SPB_16.5\tools\PSpice;C:\Cadence\SPB_16.5\tools\specctra\bin;C:\Cadence\SPB_16.5\tools\fet\bin;C:\Cadence\SPB_16.5\tools\libutil\bin;C:\Cadence\SPB_16.5\tools\bin;C:\Cadence\SPB_16.5\tools\pcb\bin"/>
</row>
<row stringID="row" value="1">
@@ -43,7 +43,7 @@
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
</item>
- <item stringID="User_EnvHost" value="ECE-PHO115-09"/>
+ <item stringID="User_EnvHost" value="ECE-PHO115-08"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
@@ -112,10 +112,6 @@
<item dataType="int" stringID="XST_NUM_BUF" value="1"/>
<item dataType="int" stringID="XST_NUM_GND" value="1"/>
<item dataType="int" stringID="XST_NUM_INV" value="1"/>
- <item dataType="int" stringID="XST_NUM_NAND2" value="1"/>
- <item dataType="int" stringID="XST_NUM_NAND3" value="1"/>
- <item dataType="int" stringID="XST_NUM_NAND4" value="1"/>
- <item dataType="int" stringID="XST_NUM_NOR3" value="1"/>
<item dataType="int" stringID="XST_NUM_OR2" value="1"/>
<item dataType="int" stringID="XST_NUM_OR3" value="1"/>
<item dataType="int" stringID="XST_NUM_OR4" value="1"/>
@@ -147,15 +143,15 @@
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="ALU.ngc"/>
</section>
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
- <item dataType="int" stringID="XST_BELS" value="125">
- <item dataType="int" stringID="XST_AND2" value="22"/>
+ <item dataType="int" stringID="XST_BELS" value="138">
+ <item dataType="int" stringID="XST_AND2" value="28"/>
<item dataType="int" stringID="XST_AND3" value="21"/>
- <item dataType="int" stringID="XST_AND4" value="2"/>
+ <item dataType="int" stringID="XST_AND4" value="3"/>
<item dataType="int" stringID="XST_BUF" value="4"/>
<item dataType="int" stringID="XST_GND" value="1"/>
- <item dataType="int" stringID="XST_INV" value="45"/>
+ <item dataType="int" stringID="XST_INV" value="53"/>
<item dataType="int" stringID="XST_LUT6" value="4"/>
- <item dataType="int" stringID="XST_OR2" value="7"/>
+ <item dataType="int" stringID="XST_OR2" value="5"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XOR2" value="1"/>
</item>
@@ -167,12 +163,12 @@
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="6slx16csg324-3"/>
- <item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="49"/>
- <item AVAILABLE="9112" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="49"/>
- <item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="49"/>
- <item AVAILABLE="49" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="49"/>
- <item AVAILABLE="49" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="0"/>
- <item AVAILABLE="49" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="0"/>
+ <item AVAILABLE="9112" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="57"/>
+ <item AVAILABLE="9112" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="57"/>
+ <item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="57"/>
+ <item AVAILABLE="57" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="57"/>
+ <item AVAILABLE="57" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="0"/>
+ <item AVAILABLE="57" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="0"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="0"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="18"/>
<item AVAILABLE="232" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="18"/>
diff --git a/Divide.cmd_log b/Divide.cmd_log
index c6e0126..b7540e1 100755
--- a/Divide.cmd_log
+++ b/Divide.cmd_log
@@ -1,2 +1,11 @@
sch2sym -intstyle ise -family spartan6 -refsym Divide {X:/My Documents/ec311/lab1/Divide.sch} {X:/My Documents/ec311/lab1/Divide.sym}
sch2sym -intstyle ise -family spartan6 -w -refsym Divide /home/michael/Documents/School/EC311/lab1/Divide.sch /home/michael/Documents/School/EC311/lab1/Divide.sym
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym}
diff --git a/Divide.jhd b/Divide.jhd
index eba0746..0b08bb7 100755
--- a/Divide.jhd
+++ b/Divide.jhd
@@ -1,9 +1,9 @@
-MODULE Divide
- SUBMODULE Divide_1
- INSTANCE XLXI_8
- SUBMODULE Divide_2
- INSTANCE XLXI_9
- SUBMODULE Divide_3
- INSTANCE XLXI_10
- SUBMODULE Divide_0
- INSTANCE XLXI_12
+MODULE Divide
+ SUBMODULE Divide_1
+ INSTANCE XLXI_8
+ SUBMODULE Divide_2
+ INSTANCE XLXI_9
+ SUBMODULE Divide_3
+ INSTANCE XLXI_10
+ SUBMODULE Divide_0
+ INSTANCE XLXI_12
diff --git a/Divide.sch b/Divide.sch
index 01ec9d9..1104a30 100755
--- a/Divide.sch
+++ b/Divide.sch
@@ -1,171 +1,170 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<drawing version="7">
- <attr value="spartan6" name="DeviceFamilyName">
- <trait delete="all:0" />
- <trait editname="all:0" />
- <trait edittrait="all:0" />
- </attr>
- <netlist>
- <signal name="out0" />
- <signal name="out1" />
- <signal name="out2" />
- <signal name="b3" />
- <signal name="b0" />
- <signal name="b1" />
- <signal name="b2" />
- <signal name="out3" />
- <port polarity="Output" name="out0" />
- <port polarity="Output" name="out1" />
- <port polarity="Output" name="out2" />
- <port polarity="Input" name="b3" />
- <port polarity="Input" name="b0" />
- <port polarity="Input" name="b1" />
- <port polarity="Input" name="b2" />
- <port polarity="Output" name="out3" />
- <blockdef name="Divide_1">
- <timestamp>2012-2-16T0:25:5</timestamp>
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </blockdef>
- <blockdef name="Divide_2">
- <timestamp>2012-2-16T0:25:9</timestamp>
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </blockdef>
- <blockdef name="Divide_3">
- <timestamp>2012-2-16T0:25:12</timestamp>
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </blockdef>
- <blockdef name="Divide_0">
- <timestamp>2012-2-16T0:25:16</timestamp>
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </blockdef>
- <block symbolname="Divide_0" name="XLXI_12">
- <blockpin signalname="b2" name="b2" />
- <blockpin signalname="b0" name="b3" />
- <blockpin signalname="b2" name="b1" />
- <blockpin signalname="b1" name="b0" />
- <blockpin signalname="out0" name="result" />
- </block>
- <block symbolname="Divide_3" name="XLXI_10">
- <blockpin signalname="b2" name="b2" />
- <blockpin signalname="b1" name="b1" />
- <blockpin signalname="b0" name="b0" />
- <blockpin signalname="b3" name="b3" />
- <blockpin signalname="out3" name="result" />
- </block>
- <block symbolname="Divide_2" name="XLXI_9">
- <blockpin signalname="b3" name="b3" />
- <blockpin signalname="b1" name="b1" />
- <blockpin signalname="b0" name="b0" />
- <blockpin signalname="b2" name="b2" />
- <blockpin signalname="out2" name="result" />
- </block>
- <block symbolname="Divide_1" name="XLXI_8">
- <blockpin signalname="b2" name="b2" />
- <blockpin signalname="b1" name="b1" />
- <blockpin signalname="b3" name="b3" />
- <blockpin signalname="b0" name="b0" />
- <blockpin signalname="out1" name="result" />
- </block>
- </netlist>
- <sheet sheetnum="1" width="3520" height="2720">
- <iomarker fontsize="28" x="2032" y="1008" name="out0" orien="R0" />
- <iomarker fontsize="28" x="2032" y="1424" name="out1" orien="R0" />
- <iomarker fontsize="28" x="2032" y="1744" name="out2" orien="R0" />
- <branch name="b0">
- <wire x2="1440" y1="1072" y2="1072" x1="1280" />
- <wire x2="1472" y1="1072" y2="1072" x1="1440" />
- <wire x2="1440" y1="1072" y2="1616" x1="1440" />
- <wire x2="1472" y1="1616" y2="1616" x1="1440" />
- <wire x2="1440" y1="1616" y2="1936" x1="1440" />
- <wire x2="1472" y1="1936" y2="1936" x1="1440" />
- <wire x2="1440" y1="1936" y2="2192" x1="1440" />
- <wire x2="1456" y1="2192" y2="2192" x1="1440" />
- </branch>
- <iomarker fontsize="28" x="1280" y="1008" name="b3" orien="R180" />
- <iomarker fontsize="28" x="1280" y="1072" name="b0" orien="R180" />
- <iomarker fontsize="28" x="1264" y="1200" name="b1" orien="R180" />
- <instance x="1472" y="1296" name="XLXI_12" orien="R0">
- </instance>
- <instance x="1472" y="1968" name="XLXI_9" orien="R0">
- </instance>
- <instance x="1472" y="1648" name="XLXI_8" orien="R0">
- </instance>
- <branch name="b1">
- <wire x2="1424" y1="1168" y2="1168" x1="1264" />
- <wire x2="1424" y1="1168" y2="1488" x1="1424" />
- <wire x2="1472" y1="1488" y2="1488" x1="1424" />
- <wire x2="1424" y1="1488" y2="1744" x1="1424" />
- <wire x2="1472" y1="1744" y2="1744" x1="1424" />
- <wire x2="1424" y1="1744" y2="2128" x1="1424" />
- <wire x2="1456" y1="2128" y2="2128" x1="1424" />
- <wire x2="1264" y1="1168" y2="1200" x1="1264" />
- <wire x2="1472" y1="1136" y2="1136" x1="1424" />
- <wire x2="1424" y1="1136" y2="1168" x1="1424" />
- </branch>
- <iomarker fontsize="28" x="2096" y="2080" name="out3" orien="R0" />
- <instance x="1456" y="2288" name="XLXI_10" orien="R0">
- </instance>
- <branch name="b3">
- <wire x2="1456" y1="1008" y2="1008" x1="1280" />
- <wire x2="1456" y1="1008" y2="1552" x1="1456" />
- <wire x2="1472" y1="1552" y2="1552" x1="1456" />
- <wire x2="1456" y1="1552" y2="1808" x1="1456" />
- <wire x2="1472" y1="1808" y2="1808" x1="1456" />
- <wire x2="1392" y1="1808" y2="2256" x1="1392" />
- <wire x2="1456" y1="2256" y2="2256" x1="1392" />
- <wire x2="1456" y1="1808" y2="1808" x1="1392" />
- </branch>
- <branch name="b2">
- <wire x2="1408" y1="1312" y2="1312" x1="1264" />
- <wire x2="1408" y1="1312" y2="1424" x1="1408" />
- <wire x2="1472" y1="1424" y2="1424" x1="1408" />
- <wire x2="1408" y1="1424" y2="1872" x1="1408" />
- <wire x2="1472" y1="1872" y2="1872" x1="1408" />
- <wire x2="1408" y1="1872" y2="2064" x1="1408" />
- <wire x2="1456" y1="2064" y2="2064" x1="1408" />
- <wire x2="1472" y1="1200" y2="1200" x1="1408" />
- <wire x2="1408" y1="1200" y2="1264" x1="1408" />
- <wire x2="1408" y1="1264" y2="1312" x1="1408" />
- <wire x2="1472" y1="1264" y2="1264" x1="1408" />
- </branch>
- <iomarker fontsize="28" x="1264" y="1312" name="b2" orien="R180" />
- <branch name="out0">
- <wire x2="2000" y1="1072" y2="1072" x1="1856" />
- <wire x2="2032" y1="1008" y2="1008" x1="2000" />
- <wire x2="2000" y1="1008" y2="1072" x1="2000" />
- </branch>
- <branch name="out1">
- <wire x2="2000" y1="1424" y2="1424" x1="1856" />
- <wire x2="2032" y1="1424" y2="1424" x1="2000" />
- </branch>
- <branch name="out2">
- <wire x2="2000" y1="1744" y2="1744" x1="1856" />
- <wire x2="2032" y1="1744" y2="1744" x1="2000" />
- </branch>
- <branch name="out3">
- <wire x2="2016" y1="2064" y2="2064" x1="1840" />
- <wire x2="2016" y1="2064" y2="2080" x1="2016" />
- <wire x2="2096" y1="2080" y2="2080" x1="2016" />
- </branch>
- </sheet>
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+ <attr value="spartan6" name="DeviceFamilyName">
+ <trait delete="all:0" />
+ <trait editname="all:0" />
+ <trait edittrait="all:0" />
+ </attr>
+ <netlist>
+ <signal name="out0" />
+ <signal name="out1" />
+ <signal name="out2" />
+ <signal name="b3" />
+ <signal name="b0" />
+ <signal name="b1" />
+ <signal name="b2" />
+ <signal name="out3" />
+ <port polarity="Output" name="out0" />
+ <port polarity="Output" name="out1" />
+ <port polarity="Output" name="out2" />
+ <port polarity="Input" name="b3" />
+ <port polarity="Input" name="b0" />
+ <port polarity="Input" name="b1" />
+ <port polarity="Input" name="b2" />
+ <port polarity="Output" name="out3" />
+ <blockdef name="Divide_1">
+ <timestamp>2012-2-16T23:13:16</timestamp>
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </blockdef>
+ <blockdef name="Divide_2">
+ <timestamp>2012-2-17T0:27:48</timestamp>
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </blockdef>
+ <blockdef name="Divide_3">
+ <timestamp>2012-2-17T0:22:15</timestamp>
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </blockdef>
+ <blockdef name="Divide_0">
+ <timestamp>2012-2-16T23:51:54</timestamp>
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </blockdef>
+ <block symbolname="Divide_0" name="XLXI_12">
+ <blockpin signalname="b2" name="b2" />
+ <blockpin signalname="b3" name="b3" />
+ <blockpin signalname="b1" name="b1" />
+ <blockpin signalname="b0" name="b0" />
+ <blockpin signalname="out0" name="result" />
+ </block>
+ <block symbolname="Divide_3" name="XLXI_10">
+ <blockpin signalname="b3" name="b3" />
+ <blockpin signalname="b2" name="b2" />
+ <blockpin signalname="b1" name="b1" />
+ <blockpin signalname="b0" name="b0" />
+ <blockpin signalname="out3" name="result" />
+ </block>
+ <block symbolname="Divide_2" name="XLXI_9">
+ <blockpin signalname="b3" name="b3" />
+ <blockpin signalname="b1" name="b1" />
+ <blockpin signalname="b0" name="b0" />
+ <blockpin signalname="b2" name="b2" />
+ <blockpin signalname="out2" name="result" />
+ </block>
+ <block symbolname="Divide_1" name="XLXI_8">
+ <blockpin signalname="b2" name="b2" />
+ <blockpin signalname="b1" name="b1" />
+ <blockpin signalname="b3" name="b3" />
+ <blockpin signalname="b0" name="b0" />
+ <blockpin signalname="out1" name="result" />
+ </block>
+ </netlist>
+ <sheet sheetnum="1" width="3520" height="2720">
+ <iomarker fontsize="28" x="2032" y="1008" name="out0" orien="R0" />
+ <iomarker fontsize="28" x="2032" y="1424" name="out1" orien="R0" />
+ <iomarker fontsize="28" x="2032" y="1744" name="out2" orien="R0" />
+ <iomarker fontsize="28" x="1280" y="1008" name="b3" orien="R180" />
+ <iomarker fontsize="28" x="1280" y="1072" name="b0" orien="R180" />
+ <iomarker fontsize="28" x="1264" y="1200" name="b1" orien="R180" />
+ <instance x="1472" y="1296" name="XLXI_12" orien="R0">
+ </instance>
+ <instance x="1472" y="1968" name="XLXI_9" orien="R0">
+ </instance>
+ <instance x="1472" y="1648" name="XLXI_8" orien="R0">
+ </instance>
+ <iomarker fontsize="28" x="2096" y="2080" name="out3" orien="R0" />
+ <instance x="1456" y="2288" name="XLXI_10" orien="R0">
+ </instance>
+ <iomarker fontsize="28" x="1264" y="1312" name="b2" orien="R180" />
+ <branch name="out0">
+ <wire x2="2000" y1="1072" y2="1072" x1="1856" />
+ <wire x2="2032" y1="1008" y2="1008" x1="2000" />
+ <wire x2="2000" y1="1008" y2="1072" x1="2000" />
+ </branch>
+ <branch name="out1">
+ <wire x2="2032" y1="1424" y2="1424" x1="1856" />
+ </branch>
+ <branch name="out2">
+ <wire x2="2032" y1="1744" y2="1744" x1="1856" />
+ </branch>
+ <branch name="out3">
+ <wire x2="2016" y1="2064" y2="2064" x1="1840" />
+ <wire x2="2016" y1="2064" y2="2080" x1="2016" />
+ <wire x2="2096" y1="2080" y2="2080" x1="2016" />
+ </branch>
+ <branch name="b0">
+ <wire x2="1440" y1="1072" y2="1072" x1="1280" />
+ <wire x2="1440" y1="1072" y2="1136" x1="1440" />
+ <wire x2="1440" y1="1136" y2="1616" x1="1440" />
+ <wire x2="1472" y1="1616" y2="1616" x1="1440" />
+ <wire x2="1440" y1="1616" y2="1936" x1="1440" />
+ <wire x2="1472" y1="1936" y2="1936" x1="1440" />
+ <wire x2="1440" y1="1936" y2="2192" x1="1440" />
+ <wire x2="1456" y1="2192" y2="2192" x1="1440" />
+ <wire x2="1472" y1="1136" y2="1136" x1="1440" />
+ </branch>
+ <branch name="b2">
+ <wire x2="1408" y1="1312" y2="1312" x1="1264" />
+ <wire x2="1408" y1="1312" y2="1424" x1="1408" />
+ <wire x2="1472" y1="1424" y2="1424" x1="1408" />
+ <wire x2="1408" y1="1424" y2="1872" x1="1408" />
+ <wire x2="1472" y1="1872" y2="1872" x1="1408" />
+ <wire x2="1408" y1="1872" y2="2064" x1="1408" />
+ <wire x2="1456" y1="2064" y2="2064" x1="1408" />
+ <wire x2="1408" y1="1264" y2="1312" x1="1408" />
+ <wire x2="1472" y1="1264" y2="1264" x1="1408" />
+ </branch>
+ <branch name="b1">
+ <wire x2="1264" y1="1168" y2="1200" x1="1264" />
+ <wire x2="1424" y1="1168" y2="1168" x1="1264" />
+ <wire x2="1424" y1="1168" y2="1200" x1="1424" />
+ <wire x2="1424" y1="1200" y2="1488" x1="1424" />
+ <wire x2="1472" y1="1488" y2="1488" x1="1424" />
+ <wire x2="1424" y1="1488" y2="1744" x1="1424" />
+ <wire x2="1472" y1="1744" y2="1744" x1="1424" />
+ <wire x2="1424" y1="1744" y2="2128" x1="1424" />
+ <wire x2="1456" y1="2128" y2="2128" x1="1424" />
+ <wire x2="1472" y1="1200" y2="1200" x1="1424" />
+ </branch>
+ <branch name="b3">
+ <wire x2="1456" y1="1008" y2="1008" x1="1280" />
+ <wire x2="1456" y1="1008" y2="1072" x1="1456" />
+ <wire x2="1472" y1="1072" y2="1072" x1="1456" />
+ <wire x2="1456" y1="1072" y2="1552" x1="1456" />
+ <wire x2="1472" y1="1552" y2="1552" x1="1456" />
+ <wire x2="1456" y1="1552" y2="1808" x1="1456" />
+ <wire x2="1472" y1="1808" y2="1808" x1="1456" />
+ <wire x2="1456" y1="1808" y2="1808" x1="1392" />
+ <wire x2="1392" y1="1808" y2="2256" x1="1392" />
+ <wire x2="1456" y1="2256" y2="2256" x1="1392" />
+ </branch>
+ </sheet>
</drawing> \ No newline at end of file
diff --git a/Divide.schlog b/Divide.schlog
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/Divide.schlog
diff --git a/Divide.sym b/Divide.sym
index 0ca17af..dfbf436 100755
--- a/Divide.sym
+++ b/Divide.sym
@@ -1,33 +1,33 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="Divide">
- <symboltype>BLOCK</symboltype>
- <timestamp>2012-2-16T0:25:40</timestamp>
- <pin polarity="Input" x="0" y="-224" name="b3" />
- <pin polarity="Input" x="0" y="-160" name="b0" />
- <pin polarity="Input" x="0" y="-96" name="b1" />
- <pin polarity="Input" x="0" y="-32" name="b2" />
- <pin polarity="Output" x="384" y="-224" name="out0" />
- <pin polarity="Output" x="384" y="-160" name="out1" />
- <pin polarity="Output" x="384" y="-96" name="out2" />
- <pin polarity="Output" x="384" y="-32" name="out3" />
- <graph>
- <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b3" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b0" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b1" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b2" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin out0" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin out1" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin out2" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin out3" />
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- <line x2="384" y1="-160" y2="-160" x1="320" />
- <line x2="384" y1="-96" y2="-96" x1="320" />
- <line x2="384" y1="-32" y2="-32" x1="320" />
- </graph>
-</symbol>
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="Divide">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-17T0:27:58</timestamp>
+ <pin polarity="Input" x="0" y="-224" name="b3" />
+ <pin polarity="Input" x="0" y="-160" name="b0" />
+ <pin polarity="Input" x="0" y="-96" name="b1" />
+ <pin polarity="Input" x="0" y="-32" name="b2" />
+ <pin polarity="Output" x="384" y="-224" name="out0" />
+ <pin polarity="Output" x="384" y="-160" name="out1" />
+ <pin polarity="Output" x="384" y="-96" name="out2" />
+ <pin polarity="Output" x="384" y="-32" name="out3" />
+ <graph>
+ <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b3" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b1" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b2" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin out0" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin out1" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin out2" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin out3" />
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ <line x2="384" y1="-160" y2="-160" x1="320" />
+ <line x2="384" y1="-96" y2="-96" x1="320" />
+ <line x2="384" y1="-32" y2="-32" x1="320" />
+ </graph>
+</symbol>
diff --git a/Divide.vf b/Divide.vf
index c428df2..8d6a587 100755
--- a/Divide.vf
+++ b/Divide.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Divide.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:11
+// /___/ /\ Timestamp : 02/16/2012 19:28:10
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Divide.vf" -w "X:/My Documents/ec311/lab1/Divide.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Divide.vf" -w "X:/My Documents/ec311/ec311-lab1/Divide.sch"
//Design Name: Divide
//Device: spartan6
//Purpose:
@@ -82,25 +82,24 @@ module Divide_2_MUSER_Divide(b0,
input b3;
output result;
- wire XLXN_1;
- wire XLXN_2;
- wire XLXN_3;
- wire XLXN_7;
+ wire XLXN_9;
+ wire XLXN_13;
+ wire XLXN_14;
+ wire XLXN_15;
- OR3 XLXI_1 (.I0(XLXN_1),
- .I1(XLXN_7),
- .I2(XLXN_3),
- .O(result));
- AND3 XLXI_2 (.I0(XLXN_2),
- .I1(b3),
- .I2(b1),
- .O(XLXN_1));
- INV XLXI_3 (.I(b2),
- .O(XLXN_2));
- INV XLXI_4 (.I(b0),
- .O(XLXN_3));
- INV XLXI_9 (.I(b1),
- .O(XLXN_7));
+ AND2 XLXI_10 (.I0(XLXN_9),
+ .I1(b3),
+ .O(result));
+ OR3 XLXI_12 (.I0(XLXN_15),
+ .I1(XLXN_14),
+ .I2(XLXN_13),
+ .O(XLXN_9));
+ INV XLXI_13 (.I(b0),
+ .O(XLXN_13));
+ INV XLXI_15 (.I(b1),
+ .O(XLXN_14));
+ INV XLXI_16 (.I(b2),
+ .O(XLXN_15));
endmodule
`timescale 1ns / 1ps
@@ -117,14 +116,23 @@ module Divide_3_MUSER_Divide(b0,
output result;
wire XLXN_2;
+ wire XLXN_13;
+ wire XLXN_14;
+ wire XLXN_15;
AND2 XLXI_2 (.I0(XLXN_2),
.I1(b3),
.O(result));
- NOR3 XLXI_3 (.I0(b0),
- .I1(b1),
- .I2(b2),
- .O(XLXN_2));
+ OR3 XLXI_4 (.I0(XLXN_15),
+ .I1(XLXN_14),
+ .I2(XLXN_13),
+ .O(XLXN_2));
+ INV XLXI_6 (.I(b2),
+ .O(XLXN_13));
+ INV XLXI_7 (.I(b1),
+ .O(XLXN_14));
+ INV XLXI_8 (.I(b0),
+ .O(XLXN_15));
endmodule
`timescale 1ns / 1ps
@@ -140,25 +148,23 @@ module Divide_0_MUSER_Divide(b0,
input b3;
output result;
- wire XLXN_1;
wire XLXN_2;
wire XLXN_3;
wire XLXN_4;
wire XLXN_5;
wire XLXN_6;
+ wire XLXN_12;
- AND3 XLXI_1 (.I0(b3),
+ AND3 XLXI_1 (.I0(b0),
.I1(b3),
.I2(XLXN_2),
.O(XLXN_5));
AND2 XLXI_2 (.I0(b1),
- .I1(XLXN_1),
+ .I1(XLXN_12),
.O(XLXN_4));
AND2 XLXI_3 (.I0(b1),
.I1(XLXN_3),
.O(XLXN_6));
- INV XLXI_4 (.I(b3),
- .O(XLXN_1));
INV XLXI_5 (.I(b1),
.O(XLXN_2));
INV XLXI_6 (.I(b0),
@@ -167,6 +173,8 @@ module Divide_0_MUSER_Divide(b0,
.I1(XLXN_5),
.I2(XLXN_4),
.O(result));
+ INV XLXI_9 (.I(b3),
+ .O(XLXN_12));
endmodule
`timescale 1ns / 1ps
@@ -204,9 +212,9 @@ module Divide(b0,
.b2(b2),
.b3(b3),
.result(out3));
- Divide_0_MUSER_Divide XLXI_12 (.b0(b1),
- .b1(b2),
+ Divide_0_MUSER_Divide XLXI_12 (.b0(b0),
+ .b1(b1),
.b2(b2),
- .b3(b0),
+ .b3(b3),
.result(out0));
endmodule
diff --git a/Divide_0.cmd_log b/Divide_0.cmd_log
index f4446c4..8050f67 100755
--- a/Divide_0.cmd_log
+++ b/Divide_0.cmd_log
@@ -1,2 +1,9 @@
sch2sym -intstyle ise -family spartan6 -refsym Divide_0 {X:/My Documents/ec311/lab1/Divide_0.sch} {X:/My Documents/ec311/lab1/Divide_0.sym}
sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 /home/michael/Documents/School/EC311/lab1/Divide_0.sch /home/michael/Documents/School/EC311/lab1/Divide_0.sym
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 {X:/My Documents/ec311/ec311-lab1/Divide_0.sch} {X:/My Documents/ec311/ec311-lab1/Divide_0.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 {X:/My Documents/ec311/ec311-lab1/Divide_0.sch} {X:/My Documents/ec311/ec311-lab1/Divide_0.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 {X:/My Documents/ec311/ec311-lab1/Divide_0.sch} {X:/My Documents/ec311/ec311-lab1/Divide_0.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 {X:/My Documents/ec311/ec311-lab1/Divide_0.sch} {X:/My Documents/ec311/ec311-lab1/Divide_0.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 {X:/My Documents/ec311/ec311-lab1/Divide_0.sch} {X:/My Documents/ec311/ec311-lab1/Divide_0.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 {X:/My Documents/ec311/ec311-lab1/Divide_0.sch} {X:/My Documents/ec311/ec311-lab1/Divide_0.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 {X:/My Documents/ec311/ec311-lab1/Divide_0.sch} {X:/My Documents/ec311/ec311-lab1/Divide_0.sym}
diff --git a/Divide_0.jhd b/Divide_0.jhd
index 3505e32..ca45971 100755
--- a/Divide_0.jhd
+++ b/Divide_0.jhd
@@ -1 +1 @@
-MODULE Divide_0
+MODULE Divide_0
diff --git a/Divide_0.sch b/Divide_0.sch
index f1040fd..1ad0c3d 100755
--- a/Divide_0.sch
+++ b/Divide_0.sch
@@ -1,170 +1,169 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<drawing version="7">
- <attr value="spartan6" name="DeviceFamilyName">
- <trait delete="all:0" />
- <trait editname="all:0" />
- <trait edittrait="all:0" />
- </attr>
- <netlist>
- <signal name="XLXN_1" />
- <signal name="XLXN_2" />
- <signal name="XLXN_3" />
- <signal name="XLXN_4" />
- <signal name="XLXN_5" />
- <signal name="XLXN_6" />
- <signal name="result" />
- <signal name="b2" />
- <signal name="b3" />
- <signal name="b1" />
- <signal name="b0" />
- <port polarity="Output" name="result" />
- <port polarity="Input" name="b2" />
- <port polarity="Input" name="b3" />
- <port polarity="Input" name="b1" />
- <port polarity="Input" name="b0" />
- <blockdef name="and3">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="64" y1="-64" y2="-64" x1="0" />
- <line x2="64" y1="-128" y2="-128" x1="0" />
- <line x2="64" y1="-192" y2="-192" x1="0" />
- <line x2="192" y1="-128" y2="-128" x1="256" />
- <line x2="144" y1="-176" y2="-176" x1="64" />
- <line x2="64" y1="-80" y2="-80" x1="144" />
- <arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
- <line x2="64" y1="-64" y2="-192" x1="64" />
- </blockdef>
- <blockdef name="and2">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="64" y1="-64" y2="-64" x1="0" />
- <line x2="64" y1="-128" y2="-128" x1="0" />
- <line x2="192" y1="-96" y2="-96" x1="256" />
- <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
- <line x2="64" y1="-48" y2="-48" x1="144" />
- <line x2="144" y1="-144" y2="-144" x1="64" />
- <line x2="64" y1="-48" y2="-144" x1="64" />
- </blockdef>
- <blockdef name="inv">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="64" y1="-32" y2="-32" x1="0" />
- <line x2="160" y1="-32" y2="-32" x1="224" />
- <line x2="128" y1="-64" y2="-32" x1="64" />
- <line x2="64" y1="-32" y2="0" x1="128" />
- <line x2="64" y1="0" y2="-64" x1="64" />
- <circle r="16" cx="144" cy="-32" />
- </blockdef>
- <blockdef name="or3">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="48" y1="-64" y2="-64" x1="0" />
- <line x2="72" y1="-128" y2="-128" x1="0" />
- <line x2="48" y1="-192" y2="-192" x1="0" />
- <line x2="192" y1="-128" y2="-128" x1="256" />
- <arc ex="192" ey="-128" sx="112" sy="-80" r="88" cx="116" cy="-168" />
- <arc ex="48" ey="-176" sx="48" sy="-80" r="56" cx="16" cy="-128" />
- <line x2="48" y1="-64" y2="-80" x1="48" />
- <line x2="48" y1="-192" y2="-176" x1="48" />
- <line x2="48" y1="-80" y2="-80" x1="112" />
- <arc ex="112" ey="-176" sx="192" sy="-128" r="88" cx="116" cy="-88" />
- <line x2="48" y1="-176" y2="-176" x1="112" />
- </blockdef>
- <block symbolname="and3" name="XLXI_1">
- <blockpin signalname="b0" name="I0" />
- <blockpin signalname="b3" name="I1" />
- <blockpin signalname="XLXN_2" name="I2" />
- <blockpin signalname="XLXN_5" name="O" />
- </block>
- <block symbolname="and2" name="XLXI_2">
- <blockpin signalname="b1" name="I0" />
- <blockpin signalname="XLXN_1" name="I1" />
- <blockpin signalname="XLXN_4" name="O" />
- </block>
- <block symbolname="and2" name="XLXI_3">
- <blockpin signalname="b1" name="I0" />
- <blockpin signalname="XLXN_3" name="I1" />
- <blockpin signalname="XLXN_6" name="O" />
- </block>
- <block symbolname="inv" name="XLXI_5">
- <blockpin signalname="b1" name="I" />
- <blockpin signalname="XLXN_2" name="O" />
- </block>
- <block symbolname="inv" name="XLXI_6">
- <blockpin signalname="b0" name="I" />
- <blockpin signalname="XLXN_3" name="O" />
- </block>
- <block symbolname="or3" name="XLXI_7">
- <blockpin signalname="XLXN_6" name="I0" />
- <blockpin signalname="XLXN_5" name="I1" />
- <blockpin signalname="XLXN_4" name="I2" />
- <blockpin signalname="result" name="O" />
- </block>
- <block symbolname="inv" name="XLXI_4">
- <blockpin signalname="b3" name="I" />
- <blockpin signalname="XLXN_1" name="O" />
- </block>
- </netlist>
- <sheet sheetnum="1" width="3520" height="2720">
- <instance x="1936" y="1488" name="XLXI_1" orien="R0" />
- <instance x="1952" y="1152" name="XLXI_2" orien="R0" />
- <instance x="1920" y="1808" name="XLXI_3" orien="R0" />
- <branch name="XLXN_1">
- <wire x2="1952" y1="1024" y2="1024" x1="1920" />
- </branch>
- <branch name="XLXN_2">
- <wire x2="1936" y1="1296" y2="1296" x1="1904" />
- </branch>
- <instance x="1680" y="1328" name="XLXI_5" orien="R0" />
- <branch name="XLXN_3">
- <wire x2="1920" y1="1680" y2="1680" x1="1888" />
- </branch>
- <instance x="1664" y="1712" name="XLXI_6" orien="R0" />
- <instance x="2304" y="1488" name="XLXI_7" orien="R0" />
- <branch name="XLXN_4">
- <wire x2="2304" y1="1056" y2="1056" x1="2208" />
- <wire x2="2304" y1="1056" y2="1296" x1="2304" />
- </branch>
- <branch name="XLXN_5">
- <wire x2="2304" y1="1360" y2="1360" x1="2192" />
- </branch>
- <branch name="XLXN_6">
- <wire x2="2304" y1="1712" y2="1712" x1="2176" />
- <wire x2="2304" y1="1424" y2="1712" x1="2304" />
- </branch>
- <branch name="result">
- <wire x2="2592" y1="1360" y2="1360" x1="2560" />
- </branch>
- <iomarker fontsize="28" x="2592" y="1360" name="result" orien="R0" />
- <branch name="b2">
- <wire x2="2192" y1="1952" y2="1952" x1="1664" />
- </branch>
- <iomarker fontsize="28" x="1664" y="1952" name="b2" orien="R180" />
- <instance x="1696" y="1056" name="XLXI_4" orien="R0" />
- <branch name="b3">
- <wire x2="1696" y1="1024" y2="1024" x1="1664" />
- </branch>
- <iomarker fontsize="28" x="1664" y="1024" name="b3" orien="R180" />
- <branch name="b1">
- <wire x2="1952" y1="1088" y2="1088" x1="1920" />
- </branch>
- <iomarker fontsize="28" x="1920" y="1088" name="b1" orien="R180" />
- <branch name="b1">
- <wire x2="1680" y1="1296" y2="1296" x1="1648" />
- </branch>
- <iomarker fontsize="28" x="1648" y="1296" name="b1" orien="R180" />
- <branch name="b3">
- <wire x2="1936" y1="1360" y2="1360" x1="1904" />
- </branch>
- <iomarker fontsize="28" x="1904" y="1360" name="b3" orien="R180" />
- <branch name="b0">
- <wire x2="1936" y1="1424" y2="1424" x1="1904" />
- </branch>
- <iomarker fontsize="28" x="1904" y="1424" name="b0" orien="R180" />
- <branch name="b0">
- <wire x2="1648" y1="1680" y2="1680" x1="1632" />
- <wire x2="1664" y1="1680" y2="1680" x1="1648" />
- </branch>
- <branch name="b1">
- <wire x2="1920" y1="1744" y2="1744" x1="1888" />
- </branch>
- <iomarker fontsize="28" x="1888" y="1744" name="b1" orien="R180" />
- <iomarker fontsize="28" x="1632" y="1680" name="b0" orien="R180" />
- </sheet>
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+ <attr value="spartan6" name="DeviceFamilyName">
+ <trait delete="all:0" />
+ <trait editname="all:0" />
+ <trait edittrait="all:0" />
+ </attr>
+ <netlist>
+ <signal name="XLXN_2" />
+ <signal name="XLXN_3" />
+ <signal name="XLXN_4" />
+ <signal name="XLXN_5" />
+ <signal name="XLXN_6" />
+ <signal name="result" />
+ <signal name="b2" />
+ <signal name="b3" />
+ <signal name="b1" />
+ <signal name="b0" />
+ <signal name="XLXN_12" />
+ <port polarity="Output" name="result" />
+ <port polarity="Input" name="b2" />
+ <port polarity="Input" name="b3" />
+ <port polarity="Input" name="b1" />
+ <port polarity="Input" name="b0" />
+ <blockdef name="and3">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-64" y2="-64" x1="0" />
+ <line x2="64" y1="-128" y2="-128" x1="0" />
+ <line x2="64" y1="-192" y2="-192" x1="0" />
+ <line x2="192" y1="-128" y2="-128" x1="256" />
+ <line x2="144" y1="-176" y2="-176" x1="64" />
+ <line x2="64" y1="-80" y2="-80" x1="144" />
+ <arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
+ <line x2="64" y1="-64" y2="-192" x1="64" />
+ </blockdef>
+ <blockdef name="and2">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-64" y2="-64" x1="0" />
+ <line x2="64" y1="-128" y2="-128" x1="0" />
+ <line x2="192" y1="-96" y2="-96" x1="256" />
+ <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
+ <line x2="64" y1="-48" y2="-48" x1="144" />
+ <line x2="144" y1="-144" y2="-144" x1="64" />
+ <line x2="64" y1="-48" y2="-144" x1="64" />
+ </blockdef>
+ <blockdef name="inv">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-32" y2="-32" x1="0" />
+ <line x2="160" y1="-32" y2="-32" x1="224" />
+ <line x2="128" y1="-64" y2="-32" x1="64" />
+ <line x2="64" y1="-32" y2="0" x1="128" />
+ <line x2="64" y1="0" y2="-64" x1="64" />
+ <circle r="16" cx="144" cy="-32" />
+ </blockdef>
+ <blockdef name="or3">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="48" y1="-64" y2="-64" x1="0" />
+ <line x2="72" y1="-128" y2="-128" x1="0" />
+ <line x2="48" y1="-192" y2="-192" x1="0" />
+ <line x2="192" y1="-128" y2="-128" x1="256" />
+ <arc ex="192" ey="-128" sx="112" sy="-80" r="88" cx="116" cy="-168" />
+ <arc ex="48" ey="-176" sx="48" sy="-80" r="56" cx="16" cy="-128" />
+ <line x2="48" y1="-64" y2="-80" x1="48" />
+ <line x2="48" y1="-192" y2="-176" x1="48" />
+ <line x2="48" y1="-80" y2="-80" x1="112" />
+ <arc ex="112" ey="-176" sx="192" sy="-128" r="88" cx="116" cy="-88" />
+ <line x2="48" y1="-176" y2="-176" x1="112" />
+ </blockdef>
+ <block symbolname="and3" name="XLXI_1">
+ <blockpin signalname="b0" name="I0" />
+ <blockpin signalname="b3" name="I1" />
+ <blockpin signalname="XLXN_2" name="I2" />
+ <blockpin signalname="XLXN_5" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_2">
+ <blockpin signalname="b1" name="I0" />
+ <blockpin signalname="XLXN_12" name="I1" />
+ <blockpin signalname="XLXN_4" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_3">
+ <blockpin signalname="b1" name="I0" />
+ <blockpin signalname="XLXN_3" name="I1" />
+ <blockpin signalname="XLXN_6" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_5">
+ <blockpin signalname="b1" name="I" />
+ <blockpin signalname="XLXN_2" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_6">
+ <blockpin signalname="b0" name="I" />
+ <blockpin signalname="XLXN_3" name="O" />
+ </block>
+ <block symbolname="or3" name="XLXI_7">
+ <blockpin signalname="XLXN_6" name="I0" />
+ <blockpin signalname="XLXN_5" name="I1" />
+ <blockpin signalname="XLXN_4" name="I2" />
+ <blockpin signalname="result" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_9">
+ <blockpin signalname="b3" name="I" />
+ <blockpin signalname="XLXN_12" name="O" />
+ </block>
+ </netlist>
+ <sheet sheetnum="1" width="3520" height="2720">
+ <instance x="1936" y="1488" name="XLXI_1" orien="R0" />
+ <instance x="1952" y="1152" name="XLXI_2" orien="R0" />
+ <instance x="1920" y="1808" name="XLXI_3" orien="R0" />
+ <branch name="XLXN_2">
+ <wire x2="1936" y1="1296" y2="1296" x1="1856" />
+ </branch>
+ <branch name="XLXN_3">
+ <wire x2="1920" y1="1680" y2="1680" x1="1888" />
+ </branch>
+ <instance x="1664" y="1712" name="XLXI_6" orien="R0" />
+ <instance x="2304" y="1488" name="XLXI_7" orien="R0" />
+ <branch name="XLXN_4">
+ <wire x2="2304" y1="1056" y2="1056" x1="2208" />
+ <wire x2="2304" y1="1056" y2="1296" x1="2304" />
+ </branch>
+ <branch name="XLXN_5">
+ <wire x2="2304" y1="1360" y2="1360" x1="2192" />
+ </branch>
+ <branch name="XLXN_6">
+ <wire x2="2304" y1="1712" y2="1712" x1="2176" />
+ <wire x2="2304" y1="1424" y2="1712" x1="2304" />
+ </branch>
+ <branch name="result">
+ <wire x2="2592" y1="1360" y2="1360" x1="2560" />
+ </branch>
+ <iomarker fontsize="28" x="2592" y="1360" name="result" orien="R0" />
+ <branch name="b2">
+ <wire x2="2400" y1="1952" y2="1952" x1="1664" />
+ </branch>
+ <iomarker fontsize="28" x="1664" y="1952" name="b2" orien="R180" />
+ <branch name="b1">
+ <wire x2="1952" y1="1088" y2="1088" x1="1920" />
+ </branch>
+ <iomarker fontsize="28" x="1920" y="1088" name="b1" orien="R180" />
+ <branch name="b3">
+ <wire x2="1936" y1="1360" y2="1360" x1="1904" />
+ </branch>
+ <iomarker fontsize="28" x="1904" y="1360" name="b3" orien="R180" />
+ <branch name="b0">
+ <wire x2="1936" y1="1424" y2="1424" x1="1904" />
+ </branch>
+ <iomarker fontsize="28" x="1904" y="1424" name="b0" orien="R180" />
+ <branch name="b0">
+ <wire x2="1664" y1="1680" y2="1680" x1="1632" />
+ </branch>
+ <branch name="b1">
+ <wire x2="1920" y1="1744" y2="1744" x1="1888" />
+ </branch>
+ <iomarker fontsize="28" x="1888" y="1744" name="b1" orien="R180" />
+ <iomarker fontsize="28" x="1632" y="1680" name="b0" orien="R180" />
+ <instance x="1632" y="1328" name="XLXI_5" orien="R0" />
+ <branch name="b1">
+ <wire x2="1632" y1="1296" y2="1296" x1="1568" />
+ </branch>
+ <iomarker fontsize="28" x="1568" y="1296" name="b1" orien="R180" />
+ <branch name="XLXN_12">
+ <wire x2="1952" y1="1024" y2="1024" x1="1920" />
+ </branch>
+ <instance x="1696" y="1056" name="XLXI_9" orien="R0" />
+ <branch name="b3">
+ <wire x2="1696" y1="1024" y2="1024" x1="1664" />
+ </branch>
+ <iomarker fontsize="28" x="1664" y="1024" name="b3" orien="R180" />
+ </sheet>
</drawing> \ No newline at end of file
diff --git a/Divide_0.sym b/Divide_0.sym
index 42aebcb..3703413 100755
--- a/Divide_0.sym
+++ b/Divide_0.sym
@@ -1,24 +1,24 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="Divide_0">
- <symboltype>BLOCK</symboltype>
- <timestamp>2012-2-16T0:25:16</timestamp>
- <pin polarity="Input" x="0" y="-32" name="b2" />
- <pin polarity="Input" x="0" y="-224" name="b3" />
- <pin polarity="Input" x="0" y="-96" name="b1" />
- <pin polarity="Input" x="0" y="-160" name="b0" />
- <pin polarity="Output" x="384" y="-224" name="result" />
- <graph>
- <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b2" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b3" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b1" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b0" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </graph>
-</symbol>
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="Divide_0">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-16T23:51:54</timestamp>
+ <pin polarity="Input" x="0" y="-32" name="b2" />
+ <pin polarity="Input" x="0" y="-224" name="b3" />
+ <pin polarity="Input" x="0" y="-96" name="b1" />
+ <pin polarity="Input" x="0" y="-160" name="b0" />
+ <pin polarity="Output" x="384" y="-224" name="result" />
+ <graph>
+ <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b2" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b3" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b1" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b0" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </graph>
+</symbol>
diff --git a/Divide_0.vf b/Divide_0.vf
index 1ffdc18..72398c8 100755
--- a/Divide_0.vf
+++ b/Divide_0.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Divide_0.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:06
+// /___/ /\ Timestamp : 02/16/2012 18:52:20
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Divide_0.vf" -w "X:/My Documents/ec311/lab1/Divide_0.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Divide_0.vf" -w "X:/My Documents/ec311/ec311-lab1/Divide_0.sch"
//Design Name: Divide_0
//Device: spartan6
//Purpose:
@@ -32,25 +32,23 @@ module Divide_0(b0,
input b3;
output result;
- wire XLXN_1;
wire XLXN_2;
wire XLXN_3;
wire XLXN_4;
wire XLXN_5;
wire XLXN_6;
+ wire XLXN_12;
- AND3 XLXI_1 (.I0(b3),
+ AND3 XLXI_1 (.I0(b0),
.I1(b3),
.I2(XLXN_2),
.O(XLXN_5));
AND2 XLXI_2 (.I0(b1),
- .I1(XLXN_1),
+ .I1(XLXN_12),
.O(XLXN_4));
AND2 XLXI_3 (.I0(b1),
.I1(XLXN_3),
.O(XLXN_6));
- INV XLXI_4 (.I(b3),
- .O(XLXN_1));
INV XLXI_5 (.I(b1),
.O(XLXN_2));
INV XLXI_6 (.I(b0),
@@ -59,4 +57,6 @@ module Divide_0(b0,
.I1(XLXN_5),
.I2(XLXN_4),
.O(result));
+ INV XLXI_9 (.I(b3),
+ .O(XLXN_12));
endmodule
diff --git a/Divide_1.cmd_log b/Divide_1.cmd_log
index c56fcf2..c5e6a18 100755
--- a/Divide_1.cmd_log
+++ b/Divide_1.cmd_log
@@ -1,3 +1,4 @@
sch2sym -intstyle ise -family spartan6 -refsym Divide_1 {X:/My Documents/ec311/lab1/Divide_1.sch} {X:/My Documents/ec311/lab1/Divide_1.sym}
sch2sym -intstyle ise -family spartan6 -refsym Divide_1 /home/michael/Documents/School/EC311/lab1/Divide_1.sch /home/michael/Documents/School/EC311/lab1/Divide_1.sym
sch2sym -intstyle ise -family spartan6 -w -refsym Divide_1 /home/michael/Documents/School/EC311/lab1/Divide_1.sch /home/michael/Documents/School/EC311/lab1/Divide_1.sym
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide_1 {X:/My Documents/ec311/ec311-lab1/Divide_1.sch} {X:/My Documents/ec311/ec311-lab1/Divide_1.sym}
diff --git a/Divide_1.jhd b/Divide_1.jhd
index f1151f9..de505b8 100755
--- a/Divide_1.jhd
+++ b/Divide_1.jhd
@@ -1 +1 @@
-MODULE Divide_1
+MODULE Divide_1
diff --git a/Divide_1.sch b/Divide_1.sch
index fe2cc4d..4e46655 100755
--- a/Divide_1.sch
+++ b/Divide_1.sch
@@ -1,209 +1,209 @@
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+ </branch>
+ <iomarker fontsize="28" x="2288" y="1440" name="b1" orien="R180" />
+ <branch name="b3">
+ <wire x2="2320" y1="1504" y2="1504" x1="2288" />
+ </branch>
+ <iomarker fontsize="28" x="2288" y="1504" name="b3" orien="R180" />
+ <branch name="result">
+ <wire x2="2912" y1="1200" y2="1200" x1="2880" />
+ </branch>
+ <iomarker fontsize="28" x="2912" y="1200" name="result" orien="R0" />
+ <branch name="b2">
+ <wire x2="2064" y1="1376" y2="1376" x1="2032" />
+ </branch>
+ <iomarker fontsize="28" x="2032" y="1376" name="b2" orien="R180" />
+ </sheet>
</drawing> \ No newline at end of file
diff --git a/Divide_1.sym b/Divide_1.sym
index 4cf6ead..8793446 100755
--- a/Divide_1.sym
+++ b/Divide_1.sym
@@ -1,24 +1,24 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="Divide_1">
- <symboltype>BLOCK</symboltype>
- <timestamp>2012-2-16T0:25:5</timestamp>
- <pin polarity="Input" x="0" y="-224" name="b2" />
- <pin polarity="Input" x="0" y="-160" name="b1" />
- <pin polarity="Input" x="0" y="-96" name="b3" />
- <pin polarity="Input" x="0" y="-32" name="b0" />
- <pin polarity="Output" x="384" y="-224" name="result" />
- <graph>
- <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b2" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b1" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b3" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b0" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </graph>
-</symbol>
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="Divide_1">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-16T23:13:16</timestamp>
+ <pin polarity="Input" x="0" y="-224" name="b2" />
+ <pin polarity="Input" x="0" y="-160" name="b1" />
+ <pin polarity="Input" x="0" y="-96" name="b3" />
+ <pin polarity="Input" x="0" y="-32" name="b0" />
+ <pin polarity="Output" x="384" y="-224" name="result" />
+ <graph>
+ <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b2" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b1" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b3" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b0" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </graph>
+</symbol>
diff --git a/Divide_1.vf b/Divide_1.vf
index ddd2752..fb10a43 100755
--- a/Divide_1.vf
+++ b/Divide_1.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Divide_1.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:06
+// /___/ /\ Timestamp : 02/16/2012 18:40:35
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Divide_1.vf" -w "X:/My Documents/ec311/lab1/Divide_1.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Divide_1.vf" -w "X:/My Documents/ec311/ec311-lab1/Divide_1.sch"
//Design Name: Divide_1
//Device: spartan6
//Purpose:
diff --git a/Divide_2.cmd_log b/Divide_2.cmd_log
index 9059580..efabe69 100755
--- a/Divide_2.cmd_log
+++ b/Divide_2.cmd_log
@@ -1,2 +1,4 @@
sch2sym -intstyle ise -family spartan6 -refsym Divide_2 {X:/My Documents/ec311/lab1/Divide_2.sch} {X:/My Documents/ec311/lab1/Divide_2.sym}
sch2sym -intstyle ise -family spartan6 -w -refsym Divide_2 /home/michael/Documents/School/EC311/lab1/Divide_2.sch /home/michael/Documents/School/EC311/lab1/Divide_2.sym
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide_2 {X:/My Documents/ec311/ec311-lab1/Divide_2.sch} {X:/My Documents/ec311/ec311-lab1/Divide_2.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide_2 {X:/My Documents/ec311/ec311-lab1/Divide_2.sch} {X:/My Documents/ec311/ec311-lab1/Divide_2.sym}
diff --git a/Divide_2.jhd b/Divide_2.jhd
index 26b7fc0..17d24fb 100755
--- a/Divide_2.jhd
+++ b/Divide_2.jhd
@@ -1 +1 @@
-MODULE Divide_2
+MODULE Divide_2
diff --git a/Divide_2.sch b/Divide_2.sch
index 152b17f..500f1fa 100755
--- a/Divide_2.sch
+++ b/Divide_2.sch
@@ -1,84 +1,120 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<drawing version="7">
- <attr value="spartan6" name="DeviceFamilyName">
- <trait delete="all:0" />
- <trait editname="all:0" />
- <trait edittrait="all:0" />
- </attr>
- <netlist>
- <signal name="result" />
- <signal name="b3" />
- <signal name="XLXN_9" />
- <signal name="b1" />
- <signal name="b0" />
- <signal name="b2" />
- <port polarity="Output" name="result" />
- <port polarity="Input" name="b3" />
- <port polarity="Input" name="b1" />
- <port polarity="Input" name="b0" />
- <port polarity="Input" name="b2" />
- <blockdef name="and2">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="64" y1="-64" y2="-64" x1="0" />
- <line x2="64" y1="-128" y2="-128" x1="0" />
- <line x2="192" y1="-96" y2="-96" x1="256" />
- <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
- <line x2="64" y1="-48" y2="-48" x1="144" />
- <line x2="144" y1="-144" y2="-144" x1="64" />
- <line x2="64" y1="-48" y2="-144" x1="64" />
- </blockdef>
- <blockdef name="nor3">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="48" y1="-64" y2="-64" x1="0" />
- <line x2="72" y1="-128" y2="-128" x1="0" />
- <line x2="48" y1="-192" y2="-192" x1="0" />
- <line x2="216" y1="-128" y2="-128" x1="256" />
- <circle r="12" cx="204" cy="-128" />
- <line x2="48" y1="-64" y2="-80" x1="48" />
- <line x2="48" y1="-192" y2="-176" x1="48" />
- <line x2="48" y1="-80" y2="-80" x1="112" />
- <line x2="48" y1="-176" y2="-176" x1="112" />
- <arc ex="48" ey="-176" sx="48" sy="-80" r="56" cx="16" cy="-128" />
- <arc ex="192" ey="-128" sx="112" sy="-80" r="88" cx="116" cy="-168" />
- <arc ex="112" ey="-176" sx="192" sy="-128" r="88" cx="116" cy="-88" />
- </blockdef>
- <block symbolname="and2" name="XLXI_10">
- <blockpin signalname="XLXN_9" name="I0" />
- <blockpin signalname="b3" name="I1" />
- <blockpin signalname="result" name="O" />
- </block>
- <block symbolname="nor3" name="XLXI_11">
- <blockpin signalname="b2" name="I0" />
- <blockpin signalname="b1" name="I1" />
- <blockpin signalname="b0" name="I2" />
- <blockpin signalname="XLXN_9" name="O" />
- </block>
- </netlist>
- <sheet sheetnum="1" width="3520" height="2720">
- <branch name="result">
- <wire x2="2192" y1="1264" y2="1264" x1="2160" />
- </branch>
- <iomarker fontsize="28" x="2192" y="1264" name="result" orien="R0" />
- <instance x="1904" y="1360" name="XLXI_10" orien="R0" />
- <branch name="b3">
- <wire x2="1904" y1="1232" y2="1232" x1="1872" />
- </branch>
- <iomarker fontsize="28" x="1872" y="1232" name="b3" orien="R180" />
- <branch name="XLXN_9">
- <wire x2="1904" y1="1296" y2="1296" x1="1872" />
- </branch>
- <instance x="1616" y="1424" name="XLXI_11" orien="R0" />
- <branch name="b1">
- <wire x2="1616" y1="1296" y2="1296" x1="1536" />
- </branch>
- <iomarker fontsize="28" x="1536" y="1296" name="b1" orien="R180" />
- <branch name="b0">
- <wire x2="1616" y1="1232" y2="1232" x1="1584" />
- </branch>
- <iomarker fontsize="28" x="1584" y="1232" name="b0" orien="R180" />
- <branch name="b2">
- <wire x2="1616" y1="1360" y2="1360" x1="1584" />
- </branch>
- <iomarker fontsize="28" x="1584" y="1360" name="b2" orien="R180" />
- </sheet>
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+ <attr value="spartan6" name="DeviceFamilyName">
+ <trait delete="all:0" />
+ <trait editname="all:0" />
+ <trait edittrait="all:0" />
+ </attr>
+ <netlist>
+ <signal name="result" />
+ <signal name="b3" />
+ <signal name="XLXN_9" />
+ <signal name="XLXN_13" />
+ <signal name="XLXN_14" />
+ <signal name="XLXN_15" />
+ <signal name="b1" />
+ <signal name="b0" />
+ <signal name="b2" />
+ <port polarity="Output" name="result" />
+ <port polarity="Input" name="b3" />
+ <port polarity="Input" name="b1" />
+ <port polarity="Input" name="b0" />
+ <port polarity="Input" name="b2" />
+ <blockdef name="and2">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-64" y2="-64" x1="0" />
+ <line x2="64" y1="-128" y2="-128" x1="0" />
+ <line x2="192" y1="-96" y2="-96" x1="256" />
+ <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
+ <line x2="64" y1="-48" y2="-48" x1="144" />
+ <line x2="144" y1="-144" y2="-144" x1="64" />
+ <line x2="64" y1="-48" y2="-144" x1="64" />
+ </blockdef>
+ <blockdef name="or3">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="48" y1="-64" y2="-64" x1="0" />
+ <line x2="72" y1="-128" y2="-128" x1="0" />
+ <line x2="48" y1="-192" y2="-192" x1="0" />
+ <line x2="192" y1="-128" y2="-128" x1="256" />
+ <arc ex="192" ey="-128" sx="112" sy="-80" r="88" cx="116" cy="-168" />
+ <arc ex="48" ey="-176" sx="48" sy="-80" r="56" cx="16" cy="-128" />
+ <line x2="48" y1="-64" y2="-80" x1="48" />
+ <line x2="48" y1="-192" y2="-176" x1="48" />
+ <line x2="48" y1="-80" y2="-80" x1="112" />
+ <arc ex="112" ey="-176" sx="192" sy="-128" r="88" cx="116" cy="-88" />
+ <line x2="48" y1="-176" y2="-176" x1="112" />
+ </blockdef>
+ <blockdef name="inv">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-32" y2="-32" x1="0" />
+ <line x2="160" y1="-32" y2="-32" x1="224" />
+ <line x2="128" y1="-64" y2="-32" x1="64" />
+ <line x2="64" y1="-32" y2="0" x1="128" />
+ <line x2="64" y1="0" y2="-64" x1="64" />
+ <circle r="16" cx="144" cy="-32" />
+ </blockdef>
+ <block symbolname="and2" name="XLXI_10">
+ <blockpin signalname="XLXN_9" name="I0" />
+ <blockpin signalname="b3" name="I1" />
+ <blockpin signalname="result" name="O" />
+ </block>
+ <block symbolname="or3" name="XLXI_12">
+ <blockpin signalname="XLXN_15" name="I0" />
+ <blockpin signalname="XLXN_14" name="I1" />
+ <blockpin signalname="XLXN_13" name="I2" />
+ <blockpin signalname="XLXN_9" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_13">
+ <blockpin signalname="b0" name="I" />
+ <blockpin signalname="XLXN_13" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_15">
+ <blockpin signalname="b1" name="I" />
+ <blockpin signalname="XLXN_14" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_16">
+ <blockpin signalname="b2" name="I" />
+ <blockpin signalname="XLXN_15" name="O" />
+ </block>
+ </netlist>
+ <sheet sheetnum="1" width="3520" height="2720">
+ <branch name="result">
+ <wire x2="2192" y1="1264" y2="1264" x1="2160" />
+ </branch>
+ <iomarker fontsize="28" x="2192" y="1264" name="result" orien="R0" />
+ <instance x="1904" y="1360" name="XLXI_10" orien="R0" />
+ <branch name="b3">
+ <wire x2="1904" y1="1232" y2="1232" x1="1872" />
+ </branch>
+ <iomarker fontsize="28" x="1872" y="1232" name="b3" orien="R180" />
+ <branch name="XLXN_9">
+ <wire x2="1888" y1="1296" y2="1296" x1="1872" />
+ <wire x2="1904" y1="1296" y2="1296" x1="1888" />
+ </branch>
+ <instance x="1632" y="1424" name="XLXI_12" orien="R0" />
+ <branch name="XLXN_13">
+ <wire x2="1632" y1="1232" y2="1232" x1="1600" />
+ </branch>
+ <instance x="1376" y="1264" name="XLXI_13" orien="R0" />
+ <branch name="XLXN_14">
+ <wire x2="1632" y1="1296" y2="1296" x1="1600" />
+ </branch>
+ <instance x="1376" y="1328" name="XLXI_15" orien="R0" />
+ <branch name="XLXN_15">
+ <wire x2="1632" y1="1360" y2="1360" x1="1600" />
+ </branch>
+ <instance x="1376" y="1392" name="XLXI_16" orien="R0" />
+ <branch name="b1">
+ <wire x2="1376" y1="1296" y2="1296" x1="1296" />
+ </branch>
+ <branch name="b0">
+ <wire x2="1376" y1="1232" y2="1232" x1="1344" />
+ </branch>
+ <branch name="b2">
+ <wire x2="1376" y1="1360" y2="1360" x1="1344" />
+ </branch>
+ <iomarker fontsize="28" x="1296" y="1296" name="b1" orien="R180" />
+ <iomarker fontsize="28" x="1344" y="1232" name="b0" orien="R180" />
+ <iomarker fontsize="28" x="1344" y="1360" name="b2" orien="R180" />
+ </sheet>
</drawing> \ No newline at end of file
diff --git a/Divide_2.sym b/Divide_2.sym
index 87e2127..2554cf8 100755
--- a/Divide_2.sym
+++ b/Divide_2.sym
@@ -1,24 +1,24 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="Divide_2">
- <symboltype>BLOCK</symboltype>
- <timestamp>2012-2-16T0:25:9</timestamp>
- <pin polarity="Input" x="0" y="-160" name="b3" />
- <pin polarity="Input" x="0" y="-224" name="b1" />
- <pin polarity="Input" x="0" y="-32" name="b0" />
- <pin polarity="Input" x="0" y="-96" name="b2" />
- <pin polarity="Output" x="384" y="-224" name="result" />
- <graph>
- <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b3" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b1" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b0" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b2" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </graph>
-</symbol>
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="Divide_2">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-17T0:27:48</timestamp>
+ <pin polarity="Input" x="0" y="-160" name="b3" />
+ <pin polarity="Input" x="0" y="-224" name="b1" />
+ <pin polarity="Input" x="0" y="-32" name="b0" />
+ <pin polarity="Input" x="0" y="-96" name="b2" />
+ <pin polarity="Output" x="384" y="-224" name="result" />
+ <graph>
+ <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b3" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b1" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b2" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </graph>
+</symbol>
diff --git a/Divide_2.vf b/Divide_2.vf
index a09efec..453ee10 100755
--- a/Divide_2.vf
+++ b/Divide_2.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Divide_2.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:06
+// /___/ /\ Timestamp : 02/16/2012 19:28:08
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Divide_2.vf" -w "X:/My Documents/ec311/lab1/Divide_2.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Divide_2.vf" -w "X:/My Documents/ec311/ec311-lab1/Divide_2.sch"
//Design Name: Divide_2
//Device: spartan6
//Purpose:
@@ -32,23 +32,22 @@ module Divide_2(b0,
input b3;
output result;
- wire XLXN_1;
- wire XLXN_2;
- wire XLXN_3;
- wire XLXN_7;
+ wire XLXN_9;
+ wire XLXN_13;
+ wire XLXN_14;
+ wire XLXN_15;
- OR3 XLXI_1 (.I0(XLXN_1),
- .I1(XLXN_7),
- .I2(XLXN_3),
- .O(result));
- AND3 XLXI_2 (.I0(XLXN_2),
- .I1(b3),
- .I2(b1),
- .O(XLXN_1));
- INV XLXI_3 (.I(b2),
- .O(XLXN_2));
- INV XLXI_4 (.I(b0),
- .O(XLXN_3));
- INV XLXI_9 (.I(b1),
- .O(XLXN_7));
+ AND2 XLXI_10 (.I0(XLXN_9),
+ .I1(b3),
+ .O(result));
+ OR3 XLXI_12 (.I0(XLXN_15),
+ .I1(XLXN_14),
+ .I2(XLXN_13),
+ .O(XLXN_9));
+ INV XLXI_13 (.I(b0),
+ .O(XLXN_13));
+ INV XLXI_15 (.I(b1),
+ .O(XLXN_14));
+ INV XLXI_16 (.I(b2),
+ .O(XLXN_15));
endmodule
diff --git a/Divide_3.cmd_log b/Divide_3.cmd_log
index 6f95eb8..ec2b844 100755
--- a/Divide_3.cmd_log
+++ b/Divide_3.cmd_log
@@ -1,2 +1,4 @@
sch2sym -intstyle ise -family spartan6 -refsym Divide_3 {X:/My Documents/ec311/lab1/Divide_3.sch} {X:/My Documents/ec311/lab1/Divide_3.sym}
sch2sym -intstyle ise -family spartan6 -w -refsym Divide_3 /home/michael/Documents/School/EC311/lab1/Divide_3.sch /home/michael/Documents/School/EC311/lab1/Divide_3.sym
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide_3 {X:/My Documents/ec311/ec311-lab1/Divide_3.sch} {X:/My Documents/ec311/ec311-lab1/Divide_3.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Divide_3 {X:/My Documents/ec311/ec311-lab1/Divide_3.sch} {X:/My Documents/ec311/ec311-lab1/Divide_3.sym}
diff --git a/Divide_3.sch b/Divide_3.sch
index c586db1..4760890 100755
--- a/Divide_3.sch
+++ b/Divide_3.sch
@@ -8,15 +8,18 @@
<netlist>
<signal name="XLXN_2" />
<signal name="result" />
+ <signal name="b3" />
<signal name="b2" />
<signal name="b1" />
<signal name="b0" />
- <signal name="b3" />
+ <signal name="XLXN_13" />
+ <signal name="XLXN_14" />
+ <signal name="XLXN_15" />
<port polarity="Output" name="result" />
+ <port polarity="Input" name="b3" />
<port polarity="Input" name="b2" />
<port polarity="Input" name="b1" />
<port polarity="Input" name="b0" />
- <port polarity="Input" name="b3" />
<blockdef name="and2">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
@@ -27,58 +30,90 @@
<line x2="144" y1="-144" y2="-144" x1="64" />
<line x2="64" y1="-48" y2="-144" x1="64" />
</blockdef>
- <blockdef name="nor3">
+ <blockdef name="or3">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="48" y1="-64" y2="-64" x1="0" />
<line x2="72" y1="-128" y2="-128" x1="0" />
<line x2="48" y1="-192" y2="-192" x1="0" />
- <line x2="216" y1="-128" y2="-128" x1="256" />
- <circle r="12" cx="204" cy="-128" />
+ <line x2="192" y1="-128" y2="-128" x1="256" />
+ <arc ex="192" ey="-128" sx="112" sy="-80" r="88" cx="116" cy="-168" />
+ <arc ex="48" ey="-176" sx="48" sy="-80" r="56" cx="16" cy="-128" />
<line x2="48" y1="-64" y2="-80" x1="48" />
<line x2="48" y1="-192" y2="-176" x1="48" />
<line x2="48" y1="-80" y2="-80" x1="112" />
- <line x2="48" y1="-176" y2="-176" x1="112" />
- <arc ex="48" ey="-176" sx="48" sy="-80" r="56" cx="16" cy="-128" />
- <arc ex="192" ey="-128" sx="112" sy="-80" r="88" cx="116" cy="-168" />
<arc ex="112" ey="-176" sx="192" sy="-128" r="88" cx="116" cy="-88" />
+ <line x2="48" y1="-176" y2="-176" x1="112" />
+ </blockdef>
+ <blockdef name="inv">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-32" y2="-32" x1="0" />
+ <line x2="160" y1="-32" y2="-32" x1="224" />
+ <line x2="128" y1="-64" y2="-32" x1="64" />
+ <line x2="64" y1="-32" y2="0" x1="128" />
+ <line x2="64" y1="0" y2="-64" x1="64" />
+ <circle r="16" cx="144" cy="-32" />
</blockdef>
<block symbolname="and2" name="XLXI_2">
<blockpin signalname="XLXN_2" name="I0" />
<blockpin signalname="b3" name="I1" />
<blockpin signalname="result" name="O" />
</block>
- <block symbolname="nor3" name="XLXI_3">
- <blockpin signalname="b0" name="I0" />
- <blockpin signalname="b1" name="I1" />
- <blockpin signalname="b2" name="I2" />
+ <block symbolname="or3" name="XLXI_4">
+ <blockpin signalname="XLXN_15" name="I0" />
+ <blockpin signalname="XLXN_14" name="I1" />
+ <blockpin signalname="XLXN_13" name="I2" />
<blockpin signalname="XLXN_2" name="O" />
</block>
+ <block symbolname="inv" name="XLXI_6">
+ <blockpin signalname="b2" name="I" />
+ <blockpin signalname="XLXN_13" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_7">
+ <blockpin signalname="b1" name="I" />
+ <blockpin signalname="XLXN_14" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_8">
+ <blockpin signalname="b0" name="I" />
+ <blockpin signalname="XLXN_15" name="O" />
+ </block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
<instance x="1920" y="1408" name="XLXI_2" orien="R0" />
<branch name="XLXN_2">
<wire x2="1920" y1="1344" y2="1344" x1="1888" />
</branch>
- <instance x="1632" y="1472" name="XLXI_3" orien="R0" />
<branch name="result">
<wire x2="2208" y1="1312" y2="1312" x1="2176" />
</branch>
<iomarker fontsize="28" x="2208" y="1312" name="result" orien="R0" />
- <branch name="b2">
+ <branch name="b3">
+ <wire x2="1920" y1="1280" y2="1280" x1="1888" />
+ </branch>
+ <iomarker fontsize="28" x="1888" y="1280" name="b3" orien="R180" />
+ <instance x="1632" y="1472" name="XLXI_4" orien="R0" />
+ <branch name="XLXN_13">
<wire x2="1632" y1="1280" y2="1280" x1="1600" />
</branch>
- <iomarker fontsize="28" x="1600" y="1280" name="b2" orien="R180" />
- <branch name="b1">
+ <instance x="1376" y="1312" name="XLXI_6" orien="R0" />
+ <branch name="XLXN_14">
<wire x2="1632" y1="1344" y2="1344" x1="1600" />
</branch>
- <iomarker fontsize="28" x="1600" y="1344" name="b1" orien="R180" />
- <branch name="b0">
+ <instance x="1376" y="1376" name="XLXI_7" orien="R0" />
+ <branch name="XLXN_15">
<wire x2="1632" y1="1408" y2="1408" x1="1600" />
</branch>
- <iomarker fontsize="28" x="1600" y="1408" name="b0" orien="R180" />
- <branch name="b3">
- <wire x2="1920" y1="1280" y2="1280" x1="1888" />
+ <instance x="1376" y="1440" name="XLXI_8" orien="R0" />
+ <branch name="b2">
+ <wire x2="1376" y1="1280" y2="1280" x1="1360" />
</branch>
- <iomarker fontsize="28" x="1888" y="1280" name="b3" orien="R180" />
+ <branch name="b1">
+ <wire x2="1376" y1="1344" y2="1344" x1="1360" />
+ </branch>
+ <branch name="b0">
+ <wire x2="1376" y1="1408" y2="1408" x1="1360" />
+ </branch>
+ <iomarker fontsize="28" x="1360" y="1280" name="b2" orien="R180" />
+ <iomarker fontsize="28" x="1360" y="1344" name="b1" orien="R180" />
+ <iomarker fontsize="28" x="1360" y="1408" name="b0" orien="R180" />
</sheet>
</drawing> \ No newline at end of file
diff --git a/Divide_3.sym b/Divide_3.sym
index 65fc49e..f48e1f2 100755
--- a/Divide_3.sym
+++ b/Divide_3.sym
@@ -1,24 +1,24 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="Divide_3">
- <symboltype>BLOCK</symboltype>
- <timestamp>2012-2-16T0:25:12</timestamp>
- <pin polarity="Input" x="0" y="-224" name="b2" />
- <pin polarity="Input" x="0" y="-160" name="b1" />
- <pin polarity="Input" x="0" y="-96" name="b0" />
- <pin polarity="Input" x="0" y="-32" name="b3" />
- <pin polarity="Output" x="384" y="-224" name="result" />
- <graph>
- <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b2" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b1" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b0" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b3" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </graph>
-</symbol>
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="Divide_3">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-17T0:22:15</timestamp>
+ <pin polarity="Input" x="0" y="-32" name="b3" />
+ <pin polarity="Input" x="0" y="-224" name="b2" />
+ <pin polarity="Input" x="0" y="-160" name="b1" />
+ <pin polarity="Input" x="0" y="-96" name="b0" />
+ <pin polarity="Output" x="384" y="-224" name="result" />
+ <graph>
+ <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b3" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b2" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b1" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b0" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </graph>
+</symbol>
diff --git a/Divide_3.vf b/Divide_3.vf
index 7a443d9..3bb123e 100755
--- a/Divide_3.vf
+++ b/Divide_3.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Divide_3.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:07
+// /___/ /\ Timestamp : 02/16/2012 19:22:52
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Divide_3.vf" -w "X:/My Documents/ec311/lab1/Divide_3.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Divide_3.vf" -w "X:/My Documents/ec311/ec311-lab1/Divide_3.sch"
//Design Name: Divide_3
//Device: spartan6
//Purpose:
@@ -33,12 +33,21 @@ module Divide_3(b0,
output result;
wire XLXN_2;
+ wire XLXN_13;
+ wire XLXN_14;
+ wire XLXN_15;
AND2 XLXI_2 (.I0(XLXN_2),
.I1(b3),
.O(result));
- NOR3 XLXI_3 (.I0(b0),
- .I1(b1),
- .I2(b2),
- .O(XLXN_2));
+ OR3 XLXI_4 (.I0(XLXN_15),
+ .I1(XLXN_14),
+ .I2(XLXN_13),
+ .O(XLXN_2));
+ INV XLXI_6 (.I(b2),
+ .O(XLXN_13));
+ INV XLXI_7 (.I(b1),
+ .O(XLXN_14));
+ INV XLXI_8 (.I(b0),
+ .O(XLXN_15));
endmodule
diff --git a/Modulo.cmd_log b/Modulo.cmd_log
index 8d43cf1..6afaaf8 100755
--- a/Modulo.cmd_log
+++ b/Modulo.cmd_log
@@ -1,2 +1,7 @@
sch2sym -intstyle ise -family spartan6 -refsym Modulo {X:/My Documents/ec311/lab1/Modulo.sch} {X:/My Documents/ec311/lab1/Modulo.sym}
sch2sym -intstyle ise -family spartan6 -w -refsym Modulo /home/michael/Documents/School/EC311/lab1/Modulo.sch /home/michael/Documents/School/EC311/lab1/Modulo.sym
+sch2sym -intstyle ise -family spartan6 -w -refsym Modulo {X:/My Documents/ec311/ec311-lab1/Modulo.sch} {X:/My Documents/ec311/ec311-lab1/Modulo.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Modulo {X:/My Documents/ec311/ec311-lab1/Modulo.sch} {X:/My Documents/ec311/ec311-lab1/Modulo.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Modulo {X:/My Documents/ec311/ec311-lab1/Modulo.sch} {X:/My Documents/ec311/ec311-lab1/Modulo.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Modulo {X:/My Documents/ec311/ec311-lab1/Modulo.sch} {X:/My Documents/ec311/ec311-lab1/Modulo.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Modulo {X:/My Documents/ec311/ec311-lab1/Modulo.sch} {X:/My Documents/ec311/ec311-lab1/Modulo.sym}
diff --git a/Modulo.sch b/Modulo.sch
index 62c204d..7240d6b 100755
--- a/Modulo.sch
+++ b/Modulo.sch
@@ -23,7 +23,7 @@
<port polarity="Output" name="out1" />
<port polarity="Output" name="out0" />
<blockdef name="Modulo_3">
- <timestamp>2012-2-15T19:55:5</timestamp>
+ <timestamp>2012-2-17T0:37:33</timestamp>
<rect width="256" x="64" y="-256" height="256" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<line x2="0" y1="-160" y2="-160" x1="64" />
@@ -32,7 +32,7 @@
<line x2="384" y1="-224" y2="-224" x1="320" />
</blockdef>
<blockdef name="Modulo_1">
- <timestamp>2012-2-15T19:55:48</timestamp>
+ <timestamp>2012-2-17T0:43:13</timestamp>
<rect width="256" x="64" y="-256" height="256" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<line x2="0" y1="-160" y2="-160" x1="64" />
@@ -41,7 +41,7 @@
<line x2="384" y1="-224" y2="-224" x1="320" />
</blockdef>
<blockdef name="Modulo_0">
- <timestamp>2012-2-15T19:55:1</timestamp>
+ <timestamp>2012-2-17T0:51:57</timestamp>
<rect width="256" x="64" y="-256" height="256" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<line x2="0" y1="-160" y2="-160" x1="64" />
diff --git a/Modulo.schlog b/Modulo.schlog
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/Modulo.schlog
diff --git a/Modulo.sym b/Modulo.sym
index 618989f..f139633 100755
--- a/Modulo.sym
+++ b/Modulo.sym
@@ -1,33 +1,33 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="Modulo">
- <symboltype>BLOCK</symboltype>
- <timestamp>2012-2-16T0:29:51</timestamp>
- <pin polarity="Input" x="0" y="-224" name="b0" />
- <pin polarity="Input" x="0" y="-160" name="b3" />
- <pin polarity="Input" x="0" y="-96" name="b2" />
- <pin polarity="Input" x="0" y="-32" name="b1" />
- <pin polarity="Output" x="384" y="-224" name="out3" />
- <pin polarity="Output" x="384" y="-160" name="out2" />
- <pin polarity="Output" x="384" y="-96" name="out1" />
- <pin polarity="Output" x="384" y="-32" name="out0" />
- <graph>
- <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b0" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b3" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b2" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b1" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin out3" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin out2" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin out1" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin out0" />
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- <line x2="384" y1="-160" y2="-160" x1="320" />
- <line x2="384" y1="-96" y2="-96" x1="320" />
- <line x2="384" y1="-32" y2="-32" x1="320" />
- </graph>
-</symbol>
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="Modulo">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-17T0:52:15</timestamp>
+ <pin polarity="Input" x="0" y="-224" name="b0" />
+ <pin polarity="Input" x="0" y="-160" name="b3" />
+ <pin polarity="Input" x="0" y="-96" name="b2" />
+ <pin polarity="Input" x="0" y="-32" name="b1" />
+ <pin polarity="Output" x="384" y="-224" name="out3" />
+ <pin polarity="Output" x="384" y="-160" name="out2" />
+ <pin polarity="Output" x="384" y="-96" name="out1" />
+ <pin polarity="Output" x="384" y="-32" name="out0" />
+ <graph>
+ <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b3" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b2" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b1" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin out3" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin out2" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin out1" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin out0" />
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ <line x2="384" y1="-160" y2="-160" x1="320" />
+ <line x2="384" y1="-96" y2="-96" x1="320" />
+ <line x2="384" y1="-32" y2="-32" x1="320" />
+ </graph>
+</symbol>
diff --git a/Modulo.vf b/Modulo.vf
index 045ae26..0007fe1 100755
--- a/Modulo.vf
+++ b/Modulo.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Modulo.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:07
+// /___/ /\ Timestamp : 02/16/2012 19:52:31
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Modulo.vf" -w "X:/My Documents/ec311/lab1/Modulo.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Modulo.vf" -w "X:/My Documents/ec311/ec311-lab1/Modulo.sch"
//Design Name: Modulo
//Device: spartan6
//Purpose:
@@ -35,23 +35,40 @@ module Modulo_0_MUSER_Modulo(b0,
wire XLXN_1;
wire XLXN_3;
wire XLXN_4;
- wire XLXN_5;
+ wire XLXN_12;
+ wire XLXN_14;
+ wire XLXN_15;
+ wire XLXN_16;
+ wire XLXN_27;
+ wire XLXN_28;
- XNOR2 XLXI_1 (.I0(b0),
- .I1(b1),
- .O(XLXN_1));
AND2 XLXI_2 (.I0(XLXN_1),
.I1(b2),
.O(XLXN_4));
- NAND3 XLXI_3 (.I0(XLXN_5),
- .I1(b1),
- .I2(b2),
- .O(XLXN_3));
OR2 XLXI_4 (.I0(XLXN_4),
.I1(XLXN_3),
.O(result));
- INV XLXI_5 (.I(b0),
- .O(XLXN_5));
+ INV XLXI_9 (.I(b1),
+ .O(XLXN_15));
+ INV XLXI_10 (.I(b0),
+ .O(XLXN_16));
+ AND3 XLXI_11 (.I0(b0),
+ .I1(XLXN_28),
+ .I2(XLXN_27),
+ .O(XLXN_3));
+ INV XLXI_12 (.I(b2),
+ .O(XLXN_27));
+ INV XLXI_13 (.I(b1),
+ .O(XLXN_28));
+ OR2 XLXI_14 (.I0(XLXN_14),
+ .I1(XLXN_12),
+ .O(XLXN_1));
+ AND2 XLXI_15 (.I0(b0),
+ .I1(b1),
+ .O(XLXN_12));
+ AND2 XLXI_16 (.I0(XLXN_16),
+ .I1(XLXN_15),
+ .O(XLXN_14));
endmodule
`timescale 1ns / 1ps
@@ -67,24 +84,24 @@ module Modulo_1_MUSER_Modulo(b0,
input b3;
output result;
- wire XLXN_1;
wire XLXN_2;
wire XLXN_3;
wire XLXN_5;
wire XLXN_6;
wire XLXN_7;
- wire XLXN_18;
- wire XLXN_19;
- wire XLXN_20;
- wire XLXN_21;
- wire XLXN_22;
wire XLXN_23;
wire XLXN_24;
+ wire XLXN_50;
+ wire XLXN_51;
+ wire XLXN_54;
+ wire XLXN_55;
+ wire XLXN_56;
+ wire XLXN_57;
AND3 XLXI_1 (.I0(b1),
.I1(b2),
.I2(b3),
- .O(XLXN_1));
+ .O(XLXN_55));
AND3 XLXI_2 (.I0(XLXN_6),
.I1(XLXN_5),
.I2(b3),
@@ -93,38 +110,38 @@ module Modulo_1_MUSER_Modulo(b0,
.I1(XLXN_7),
.I2(b3),
.O(XLXN_3));
- OR3 XLXI_4 (.I0(XLXN_3),
- .I1(XLXN_2),
- .I2(XLXN_1),
- .O(XLXN_21));
INV XLXI_5 (.I(b1),
.O(XLXN_5));
INV XLXI_6 (.I(b0),
.O(XLXN_6));
INV XLXI_7 (.I(b2),
.O(XLXN_7));
- OR2 XLXI_9 (.I0(XLXN_20),
- .I1(XLXN_21),
- .O(result));
AND4 XLXI_11 (.I0(b0),
.I1(XLXN_24),
.I2(b2),
.I3(XLXN_23),
- .O(XLXN_19));
- OR2 XLXI_12 (.I0(XLXN_19),
- .I1(XLXN_18),
- .O(XLXN_20));
- NAND4 XLXI_13 (.I0(b0),
- .I1(XLXN_22),
- .I2(b2),
- .I3(b3),
- .O(XLXN_18));
- INV XLXI_14 (.I(b1),
- .O(XLXN_22));
+ .O(XLXN_57));
INV XLXI_15 (.I(b3),
.O(XLXN_23));
INV XLXI_16 (.I(b1),
.O(XLXN_24));
+ AND4 XLXI_18 (.I0(XLXN_54),
+ .I1(b1),
+ .I2(XLXN_50),
+ .I3(XLXN_51),
+ .O(XLXN_56));
+ INV XLXI_19 (.I(b2),
+ .O(XLXN_50));
+ INV XLXI_20 (.I(b3),
+ .O(XLXN_51));
+ INV XLXI_21 (.I(b0),
+ .O(XLXN_54));
+ OR5 XLXI_22 (.I0(XLXN_57),
+ .I1(XLXN_56),
+ .I2(XLXN_3),
+ .I3(XLXN_2),
+ .I4(XLXN_55),
+ .O(result));
endmodule
`timescale 1ns / 1ps
diff --git a/Modulo_0.cmd_log b/Modulo_0.cmd_log
index 8677539..c77853d 100755
--- a/Modulo_0.cmd_log
+++ b/Modulo_0.cmd_log
@@ -1,2 +1,6 @@
sch2sym -intstyle ise -family spartan6 -refsym Modulo_0 {X:/My Documents/ec311/lab1/Modulo_0.sch} {X:/My Documents/ec311/lab1/Modulo_0.sym}
sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_0 /home/michael/Documents/School/EC311/lab1/Modulo_0.sch /home/michael/Documents/School/EC311/lab1/Modulo_0.sym
+sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_0 {X:/My Documents/ec311/ec311-lab1/Modulo_0.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_0.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_0 {X:/My Documents/ec311/ec311-lab1/Modulo_0.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_0.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_0 {X:/My Documents/ec311/ec311-lab1/Modulo_0.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_0.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_0 {X:/My Documents/ec311/ec311-lab1/Modulo_0.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_0.sym}
diff --git a/Modulo_0.sch b/Modulo_0.sch
index f060ebf..096f110 100755
--- a/Modulo_0.sch
+++ b/Modulo_0.sch
@@ -9,31 +9,22 @@
<signal name="XLXN_1" />
<signal name="XLXN_3" />
<signal name="XLXN_4" />
- <signal name="XLXN_5" />
<signal name="b2" />
<signal name="b1" />
<signal name="b0" />
<signal name="result" />
<signal name="b3" />
+ <signal name="XLXN_12" />
+ <signal name="XLXN_14" />
+ <signal name="XLXN_15" />
+ <signal name="XLXN_16" />
+ <signal name="XLXN_27" />
+ <signal name="XLXN_28" />
<port polarity="Input" name="b2" />
<port polarity="Input" name="b1" />
<port polarity="Input" name="b0" />
<port polarity="Output" name="result" />
<port polarity="Input" name="b3" />
- <blockdef name="xnor2">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="64" y1="-64" y2="-64" x1="0" />
- <line x2="60" y1="-128" y2="-128" x1="0" />
- <arc ex="44" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
- <arc ex="64" ey="-144" sx="64" sy="-48" r="56" cx="32" cy="-96" />
- <line x2="64" y1="-144" y2="-144" x1="128" />
- <line x2="64" y1="-48" y2="-48" x1="128" />
- <arc ex="128" ey="-144" sx="208" sy="-96" r="88" cx="132" cy="-56" />
- <arc ex="208" ey="-96" sx="128" sy="-48" r="88" cx="132" cy="-136" />
- <circle r="8" cx="220" cy="-96" />
- <line x2="256" y1="-96" y2="-96" x1="228" />
- <line x2="60" y1="-28" y2="-28" x1="60" />
- </blockdef>
<blockdef name="and2">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
@@ -44,18 +35,6 @@
<line x2="144" y1="-144" y2="-144" x1="64" />
<line x2="64" y1="-48" y2="-144" x1="64" />
</blockdef>
- <blockdef name="nand3">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="64" y1="-64" y2="-64" x1="0" />
- <line x2="64" y1="-128" y2="-128" x1="0" />
- <line x2="64" y1="-192" y2="-192" x1="0" />
- <line x2="216" y1="-128" y2="-128" x1="256" />
- <circle r="12" cx="204" cy="-128" />
- <line x2="144" y1="-176" y2="-176" x1="64" />
- <line x2="64" y1="-80" y2="-80" x1="144" />
- <arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
- <line x2="64" y1="-64" y2="-192" x1="64" />
- </blockdef>
<blockdef name="or2">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-64" x1="0" />
@@ -76,39 +55,70 @@
<line x2="64" y1="0" y2="-64" x1="64" />
<circle r="16" cx="144" cy="-32" />
</blockdef>
- <block symbolname="xnor2" name="XLXI_1">
- <blockpin signalname="b0" name="I0" />
- <blockpin signalname="b1" name="I1" />
- <blockpin signalname="XLXN_1" name="O" />
- </block>
+ <blockdef name="and3">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-64" y2="-64" x1="0" />
+ <line x2="64" y1="-128" y2="-128" x1="0" />
+ <line x2="64" y1="-192" y2="-192" x1="0" />
+ <line x2="192" y1="-128" y2="-128" x1="256" />
+ <line x2="144" y1="-176" y2="-176" x1="64" />
+ <line x2="64" y1="-80" y2="-80" x1="144" />
+ <arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
+ <line x2="64" y1="-64" y2="-192" x1="64" />
+ </blockdef>
<block symbolname="and2" name="XLXI_2">
<blockpin signalname="XLXN_1" name="I0" />
<blockpin signalname="b2" name="I1" />
<blockpin signalname="XLXN_4" name="O" />
</block>
- <block symbolname="nand3" name="XLXI_3">
- <blockpin signalname="XLXN_5" name="I0" />
- <blockpin signalname="b1" name="I1" />
- <blockpin signalname="b2" name="I2" />
- <blockpin signalname="XLXN_3" name="O" />
- </block>
<block symbolname="or2" name="XLXI_4">
<blockpin signalname="XLXN_4" name="I0" />
<blockpin signalname="XLXN_3" name="I1" />
<blockpin signalname="result" name="O" />
</block>
- <block symbolname="inv" name="XLXI_5">
+ <block symbolname="inv" name="XLXI_9">
+ <blockpin signalname="b1" name="I" />
+ <blockpin signalname="XLXN_15" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_10">
<blockpin signalname="b0" name="I" />
- <blockpin signalname="XLXN_5" name="O" />
+ <blockpin signalname="XLXN_16" name="O" />
+ </block>
+ <block symbolname="and3" name="XLXI_11">
+ <blockpin signalname="b0" name="I0" />
+ <blockpin signalname="XLXN_28" name="I1" />
+ <blockpin signalname="XLXN_27" name="I2" />
+ <blockpin signalname="XLXN_3" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_12">
+ <blockpin signalname="b2" name="I" />
+ <blockpin signalname="XLXN_27" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_13">
+ <blockpin signalname="b1" name="I" />
+ <blockpin signalname="XLXN_28" name="O" />
+ </block>
+ <block symbolname="or2" name="XLXI_14">
+ <blockpin signalname="XLXN_14" name="I0" />
+ <blockpin signalname="XLXN_12" name="I1" />
+ <blockpin signalname="XLXN_1" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_15">
+ <blockpin signalname="b0" name="I0" />
+ <blockpin signalname="b1" name="I1" />
+ <blockpin signalname="XLXN_12" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_16">
+ <blockpin signalname="XLXN_16" name="I0" />
+ <blockpin signalname="XLXN_15" name="I1" />
+ <blockpin signalname="XLXN_14" name="O" />
</block>
</netlist>
<sheet sheetnum="1" width="3520" height="2720">
- <instance x="1648" y="1728" name="XLXI_1" orien="R0" />
<branch name="XLXN_1">
<wire x2="1936" y1="1632" y2="1632" x1="1904" />
</branch>
<instance x="1936" y="1696" name="XLXI_2" orien="R0" />
- <instance x="1808" y="1328" name="XLXI_3" orien="R0" />
<instance x="2288" y="1472" name="XLXI_4" orien="R0" />
<branch name="XLXN_3">
<wire x2="2176" y1="1200" y2="1200" x1="2064" />
@@ -120,34 +130,16 @@
<wire x2="2240" y1="1408" y2="1600" x1="2240" />
<wire x2="2288" y1="1408" y2="1408" x1="2240" />
</branch>
- <branch name="XLXN_5">
- <wire x2="1808" y1="1264" y2="1264" x1="1776" />
- </branch>
- <instance x="1552" y="1296" name="XLXI_5" orien="R0" />
- <branch name="b2">
- <wire x2="1808" y1="1136" y2="1136" x1="1776" />
- </branch>
- <iomarker fontsize="28" x="1776" y="1136" name="b2" orien="R180" />
- <branch name="b1">
- <wire x2="1808" y1="1200" y2="1200" x1="1776" />
- </branch>
- <iomarker fontsize="28" x="1776" y="1200" name="b1" orien="R180" />
<branch name="b0">
<wire x2="1552" y1="1264" y2="1264" x1="1520" />
+ <wire x2="1776" y1="1264" y2="1264" x1="1552" />
+ <wire x2="1808" y1="1264" y2="1264" x1="1776" />
</branch>
<iomarker fontsize="28" x="1520" y="1264" name="b0" orien="R180" />
<branch name="b2">
<wire x2="1936" y1="1568" y2="1568" x1="1904" />
</branch>
<iomarker fontsize="28" x="1904" y="1568" name="b2" orien="R180" />
- <branch name="b1">
- <wire x2="1648" y1="1600" y2="1600" x1="1616" />
- </branch>
- <iomarker fontsize="28" x="1616" y="1600" name="b1" orien="R180" />
- <branch name="b0">
- <wire x2="1648" y1="1664" y2="1664" x1="1616" />
- </branch>
- <iomarker fontsize="28" x="1616" y="1664" name="b0" orien="R180" />
<branch name="result">
<wire x2="2576" y1="1376" y2="1376" x1="2544" />
</branch>
@@ -156,5 +148,63 @@
<wire x2="2608" y1="1024" y2="1024" x1="1712" />
</branch>
<iomarker fontsize="28" x="1712" y="1024" name="b3" orien="R180" />
+ <branch name="XLXN_12">
+ <wire x2="1648" y1="1600" y2="1600" x1="1616" />
+ </branch>
+ <branch name="XLXN_14">
+ <wire x2="1648" y1="1664" y2="1664" x1="1568" />
+ <wire x2="1568" y1="1664" y2="1696" x1="1568" />
+ <wire x2="1712" y1="1696" y2="1696" x1="1568" />
+ <wire x2="1712" y1="1696" y2="1760" x1="1712" />
+ <wire x2="1712" y1="1760" y2="1760" x1="1648" />
+ </branch>
+ <branch name="XLXN_15">
+ <wire x2="1392" y1="1728" y2="1728" x1="1360" />
+ </branch>
+ <instance x="1136" y="1760" name="XLXI_9" orien="R0" />
+ <branch name="XLXN_16">
+ <wire x2="1392" y1="1792" y2="1792" x1="1360" />
+ </branch>
+ <instance x="1136" y="1824" name="XLXI_10" orien="R0" />
+ <branch name="b0">
+ <wire x2="1120" y1="1552" y2="1552" x1="1088" />
+ <wire x2="1120" y1="1552" y2="1632" x1="1120" />
+ <wire x2="1360" y1="1632" y2="1632" x1="1120" />
+ <wire x2="1120" y1="1632" y2="1792" x1="1120" />
+ <wire x2="1136" y1="1792" y2="1792" x1="1120" />
+ </branch>
+ <iomarker fontsize="28" x="1088" y="1488" name="b1" orien="R180" />
+ <iomarker fontsize="28" x="1088" y="1552" name="b0" orien="R180" />
+ <branch name="b1">
+ <wire x2="1136" y1="1600" y2="1600" x1="1040" />
+ <wire x2="1040" y1="1600" y2="1728" x1="1040" />
+ <wire x2="1136" y1="1728" y2="1728" x1="1040" />
+ <wire x2="1120" y1="1488" y2="1488" x1="1088" />
+ <wire x2="1136" y1="1488" y2="1488" x1="1120" />
+ <wire x2="1344" y1="1488" y2="1488" x1="1136" />
+ <wire x2="1344" y1="1488" y2="1568" x1="1344" />
+ <wire x2="1360" y1="1568" y2="1568" x1="1344" />
+ <wire x2="1136" y1="1488" y2="1600" x1="1136" />
+ </branch>
+ <instance x="1808" y="1328" name="XLXI_11" orien="R0" />
+ <branch name="XLXN_27">
+ <wire x2="1808" y1="1136" y2="1136" x1="1776" />
+ </branch>
+ <instance x="1552" y="1168" name="XLXI_12" orien="R0" />
+ <branch name="XLXN_28">
+ <wire x2="1808" y1="1200" y2="1200" x1="1776" />
+ </branch>
+ <instance x="1552" y="1232" name="XLXI_13" orien="R0" />
+ <branch name="b2">
+ <wire x2="1552" y1="1136" y2="1136" x1="1520" />
+ </branch>
+ <branch name="b1">
+ <wire x2="1552" y1="1200" y2="1200" x1="1520" />
+ </branch>
+ <iomarker fontsize="28" x="1520" y="1200" name="b1" orien="R180" />
+ <iomarker fontsize="28" x="1520" y="1136" name="b2" orien="R180" />
+ <instance x="1648" y="1728" name="XLXI_14" orien="R0" />
+ <instance x="1360" y="1696" name="XLXI_15" orien="R0" />
+ <instance x="1392" y="1856" name="XLXI_16" orien="R0" />
</sheet>
</drawing> \ No newline at end of file
diff --git a/Modulo_0.sym b/Modulo_0.sym
index ed2353e..c12e4f0 100755
--- a/Modulo_0.sym
+++ b/Modulo_0.sym
@@ -1,24 +1,24 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="Modulo_0">
- <symboltype>BLOCK</symboltype>
- <timestamp>2012-2-16T0:29:48</timestamp>
- <pin polarity="Input" x="0" y="-224" name="b2" />
- <pin polarity="Input" x="0" y="-160" name="b1" />
- <pin polarity="Input" x="0" y="-96" name="b0" />
- <pin polarity="Input" x="0" y="-32" name="b3" />
- <pin polarity="Output" x="384" y="-224" name="result" />
- <graph>
- <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b2" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b1" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b0" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b3" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </graph>
-</symbol>
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="Modulo_0">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-17T0:51:57</timestamp>
+ <pin polarity="Input" x="0" y="-224" name="b2" />
+ <pin polarity="Input" x="0" y="-160" name="b1" />
+ <pin polarity="Input" x="0" y="-96" name="b0" />
+ <pin polarity="Input" x="0" y="-32" name="b3" />
+ <pin polarity="Output" x="384" y="-224" name="result" />
+ <graph>
+ <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b2" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b1" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b3" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </graph>
+</symbol>
diff --git a/Modulo_0.vf b/Modulo_0.vf
index 0b8eb41..c0c56d3 100755
--- a/Modulo_0.vf
+++ b/Modulo_0.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Modulo_0.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:07
+// /___/ /\ Timestamp : 02/16/2012 19:52:31
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Modulo_0.vf" -w "X:/My Documents/ec311/lab1/Modulo_0.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Modulo_0.vf" -w "X:/My Documents/ec311/ec311-lab1/Modulo_0.sch"
//Design Name: Modulo_0
//Device: spartan6
//Purpose:
@@ -35,21 +35,38 @@ module Modulo_0(b0,
wire XLXN_1;
wire XLXN_3;
wire XLXN_4;
- wire XLXN_5;
+ wire XLXN_12;
+ wire XLXN_14;
+ wire XLXN_15;
+ wire XLXN_16;
+ wire XLXN_27;
+ wire XLXN_28;
- XNOR2 XLXI_1 (.I0(b0),
- .I1(b1),
- .O(XLXN_1));
AND2 XLXI_2 (.I0(XLXN_1),
.I1(b2),
.O(XLXN_4));
- NAND3 XLXI_3 (.I0(XLXN_5),
- .I1(b1),
- .I2(b2),
- .O(XLXN_3));
OR2 XLXI_4 (.I0(XLXN_4),
.I1(XLXN_3),
.O(result));
- INV XLXI_5 (.I(b0),
- .O(XLXN_5));
+ INV XLXI_9 (.I(b1),
+ .O(XLXN_15));
+ INV XLXI_10 (.I(b0),
+ .O(XLXN_16));
+ AND3 XLXI_11 (.I0(b0),
+ .I1(XLXN_28),
+ .I2(XLXN_27),
+ .O(XLXN_3));
+ INV XLXI_12 (.I(b2),
+ .O(XLXN_27));
+ INV XLXI_13 (.I(b1),
+ .O(XLXN_28));
+ OR2 XLXI_14 (.I0(XLXN_14),
+ .I1(XLXN_12),
+ .O(XLXN_1));
+ AND2 XLXI_15 (.I0(b0),
+ .I1(b1),
+ .O(XLXN_12));
+ AND2 XLXI_16 (.I0(XLXN_16),
+ .I1(XLXN_15),
+ .O(XLXN_14));
endmodule
diff --git a/Modulo_1.cmd_log b/Modulo_1.cmd_log
index 26beaf7..f539342 100755
--- a/Modulo_1.cmd_log
+++ b/Modulo_1.cmd_log
@@ -1,2 +1,5 @@
sch2sym -intstyle ise -family spartan6 -refsym Modulo_1 {X:/My Documents/ec311/lab1/Modulo_1.sch} {X:/My Documents/ec311/lab1/Modulo_1.sym}
sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_1 /home/michael/Documents/School/EC311/lab1/Modulo_1.sch /home/michael/Documents/School/EC311/lab1/Modulo_1.sym
+sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_1 {X:/My Documents/ec311/ec311-lab1/Modulo_1.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_1.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_1 {X:/My Documents/ec311/ec311-lab1/Modulo_1.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_1.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_1 {X:/My Documents/ec311/ec311-lab1/Modulo_1.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_1.sym}
diff --git a/Modulo_1.jhd b/Modulo_1.jhd
index 435b81c..189c159 100755
--- a/Modulo_1.jhd
+++ b/Modulo_1.jhd
@@ -1 +1 @@
-MODULE Modulo_1
+MODULE Modulo_1
diff --git a/Modulo_1.sch b/Modulo_1.sch
index dd65a0b..9a67697 100755
--- a/Modulo_1.sch
+++ b/Modulo_1.sch
@@ -1,295 +1,300 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<drawing version="7">
- <attr value="spartan6" name="DeviceFamilyName">
- <trait delete="all:0" />
- <trait editname="all:0" />
- <trait edittrait="all:0" />
- </attr>
- <netlist>
- <signal name="XLXN_1" />
- <signal name="XLXN_2" />
- <signal name="XLXN_3" />
- <signal name="XLXN_5" />
- <signal name="XLXN_6" />
- <signal name="XLXN_7" />
- <signal name="XLXN_21" />
- <signal name="b3" />
- <signal name="b2" />
- <signal name="b1" />
- <signal name="b0" />
- <signal name="result" />
- <signal name="XLXN_18" />
- <signal name="XLXN_22" />
- <signal name="XLXN_31" />
- <signal name="XLXN_19" />
- <signal name="XLXN_23" />
- <signal name="XLXN_24" />
- <signal name="XLXN_46" />
- <port polarity="Input" name="b3" />
- <port polarity="Input" name="b2" />
- <port polarity="Input" name="b1" />
- <port polarity="Input" name="b0" />
- <port polarity="Output" name="result" />
- <blockdef name="and3">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="64" y1="-64" y2="-64" x1="0" />
- <line x2="64" y1="-128" y2="-128" x1="0" />
- <line x2="64" y1="-192" y2="-192" x1="0" />
- <line x2="192" y1="-128" y2="-128" x1="256" />
- <line x2="144" y1="-176" y2="-176" x1="64" />
- <line x2="64" y1="-80" y2="-80" x1="144" />
- <arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
- <line x2="64" y1="-64" y2="-192" x1="64" />
- </blockdef>
- <blockdef name="or3">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="48" y1="-64" y2="-64" x1="0" />
- <line x2="72" y1="-128" y2="-128" x1="0" />
- <line x2="48" y1="-192" y2="-192" x1="0" />
- <line x2="192" y1="-128" y2="-128" x1="256" />
- <arc ex="192" ey="-128" sx="112" sy="-80" r="88" cx="116" cy="-168" />
- <arc ex="48" ey="-176" sx="48" sy="-80" r="56" cx="16" cy="-128" />
- <line x2="48" y1="-64" y2="-80" x1="48" />
- <line x2="48" y1="-192" y2="-176" x1="48" />
- <line x2="48" y1="-80" y2="-80" x1="112" />
- <arc ex="112" ey="-176" sx="192" sy="-128" r="88" cx="116" cy="-88" />
- <line x2="48" y1="-176" y2="-176" x1="112" />
- </blockdef>
- <blockdef name="inv">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="64" y1="-32" y2="-32" x1="0" />
- <line x2="160" y1="-32" y2="-32" x1="224" />
- <line x2="128" y1="-64" y2="-32" x1="64" />
- <line x2="64" y1="-32" y2="0" x1="128" />
- <line x2="64" y1="0" y2="-64" x1="64" />
- <circle r="16" cx="144" cy="-32" />
- </blockdef>
- <blockdef name="and4">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="64" y1="-112" y2="-112" x1="144" />
- <arc ex="144" ey="-208" sx="144" sy="-112" r="48" cx="144" cy="-160" />
- <line x2="144" y1="-208" y2="-208" x1="64" />
- <line x2="64" y1="-64" y2="-256" x1="64" />
- <line x2="192" y1="-160" y2="-160" x1="256" />
- <line x2="64" y1="-256" y2="-256" x1="0" />
- <line x2="64" y1="-192" y2="-192" x1="0" />
- <line x2="64" y1="-128" y2="-128" x1="0" />
- <line x2="64" y1="-64" y2="-64" x1="0" />
- </blockdef>
- <blockdef name="nand4">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="64" y1="-64" y2="-64" x1="0" />
- <line x2="64" y1="-128" y2="-128" x1="0" />
- <line x2="64" y1="-192" y2="-192" x1="0" />
- <line x2="64" y1="-256" y2="-256" x1="0" />
- <line x2="216" y1="-160" y2="-160" x1="256" />
- <circle r="12" cx="204" cy="-160" />
- <line x2="64" y1="-64" y2="-256" x1="64" />
- <line x2="144" y1="-208" y2="-208" x1="64" />
- <arc ex="144" ey="-208" sx="144" sy="-112" r="48" cx="144" cy="-160" />
- <line x2="64" y1="-112" y2="-112" x1="144" />
- </blockdef>
- <block symbolname="and3" name="XLXI_1">
- <blockpin signalname="b1" name="I0" />
- <blockpin signalname="b2" name="I1" />
- <blockpin signalname="b3" name="I2" />
- <blockpin signalname="XLXN_1" name="O" />
- </block>
- <block symbolname="and3" name="XLXI_2">
- <blockpin signalname="XLXN_6" name="I0" />
- <blockpin signalname="XLXN_5" name="I1" />
- <blockpin signalname="b3" name="I2" />
- <blockpin signalname="XLXN_2" name="O" />
- </block>
- <block symbolname="and3" name="XLXI_3">
- <blockpin signalname="b0" name="I0" />
- <blockpin signalname="XLXN_7" name="I1" />
- <blockpin signalname="b3" name="I2" />
- <blockpin signalname="XLXN_3" name="O" />
- </block>
- <block symbolname="or3" name="XLXI_4">
- <blockpin signalname="XLXN_3" name="I0" />
- <blockpin signalname="XLXN_2" name="I1" />
- <blockpin signalname="XLXN_1" name="I2" />
- <blockpin signalname="XLXN_21" name="O" />
- </block>
- <block symbolname="inv" name="XLXI_5">
- <blockpin signalname="b1" name="I" />
- <blockpin signalname="XLXN_5" name="O" />
- </block>
- <block symbolname="inv" name="XLXI_6">
- <blockpin signalname="b0" name="I" />
- <blockpin signalname="XLXN_6" name="O" />
- </block>
- <block symbolname="inv" name="XLXI_7">
- <blockpin signalname="b2" name="I" />
- <blockpin signalname="XLXN_7" name="O" />
- </block>
- <block symbolname="or3" name="XLXI_17">
- <blockpin signalname="XLXN_46" name="I0" />
- <blockpin signalname="XLXN_31" name="I1" />
- <blockpin signalname="XLXN_21" name="I2" />
- <blockpin signalname="result" name="O" />
- </block>
- <block symbolname="nand4" name="XLXI_13">
- <blockpin signalname="b0" name="I0" />
- <blockpin signalname="XLXN_22" name="I1" />
- <blockpin signalname="b2" name="I2" />
- <blockpin signalname="b3" name="I3" />
- <blockpin signalname="XLXN_31" name="O" />
- </block>
- <block symbolname="inv" name="XLXI_14">
- <blockpin signalname="b1" name="I" />
- <blockpin signalname="XLXN_22" name="O" />
- </block>
- <block symbolname="and4" name="XLXI_11">
- <blockpin signalname="b0" name="I0" />
- <blockpin signalname="XLXN_24" name="I1" />
- <blockpin signalname="b2" name="I2" />
- <blockpin signalname="XLXN_23" name="I3" />
- <blockpin signalname="XLXN_46" name="O" />
- </block>
- <block symbolname="inv" name="XLXI_15">
- <blockpin signalname="b3" name="I" />
- <blockpin signalname="XLXN_23" name="O" />
- </block>
- <block symbolname="inv" name="XLXI_16">
- <blockpin signalname="b1" name="I" />
- <blockpin signalname="XLXN_24" name="O" />
- </block>
- </netlist>
- <sheet sheetnum="1" width="3520" height="2720">
- <branch name="XLXN_1">
- <wire x2="1888" y1="928" y2="928" x1="1696" />
- <wire x2="1888" y1="928" y2="1104" x1="1888" />
- </branch>
- <branch name="XLXN_2">
- <wire x2="1888" y1="1168" y2="1168" x1="1696" />
- </branch>
- <branch name="XLXN_3">
- <wire x2="1888" y1="1392" y2="1392" x1="1696" />
- <wire x2="1888" y1="1232" y2="1392" x1="1888" />
- </branch>
- <branch name="XLXN_5">
- <wire x2="1440" y1="1168" y2="1168" x1="1408" />
- </branch>
- <branch name="XLXN_6">
- <wire x2="1440" y1="1232" y2="1232" x1="1408" />
- </branch>
- <branch name="XLXN_7">
- <wire x2="1440" y1="1392" y2="1392" x1="1408" />
- </branch>
- <instance x="1440" y="1056" name="XLXI_1" orien="R0" />
- <instance x="1440" y="1296" name="XLXI_2" orien="R0" />
- <instance x="1440" y="1520" name="XLXI_3" orien="R0" />
- <instance x="1888" y="1296" name="XLXI_4" orien="R0" />
- <instance x="1184" y="1200" name="XLXI_5" orien="R0" />
- <instance x="1184" y="1264" name="XLXI_6" orien="R0" />
- <branch name="b2">
- <wire x2="1184" y1="1392" y2="1392" x1="1168" />
- </branch>
- <instance x="1184" y="1424" name="XLXI_7" orien="R0" />
- <branch name="b0">
- <wire x2="1440" y1="1456" y2="1456" x1="1424" />
- </branch>
- <branch name="XLXN_21">
- <wire x2="2272" y1="1168" y2="1168" x1="2144" />
- <wire x2="2272" y1="1168" y2="1344" x1="2272" />
- <wire x2="2400" y1="1344" y2="1344" x1="2272" />
- </branch>
- <branch name="b3">
- <wire x2="1440" y1="864" y2="864" x1="1408" />
- </branch>
- <iomarker fontsize="28" x="1408" y="864" name="b3" orien="R180" />
- <branch name="b2">
- <wire x2="1440" y1="928" y2="928" x1="1408" />
- </branch>
- <iomarker fontsize="28" x="1408" y="928" name="b2" orien="R180" />
- <branch name="b1">
- <wire x2="1440" y1="992" y2="992" x1="1408" />
- </branch>
- <iomarker fontsize="28" x="1408" y="992" name="b1" orien="R180" />
- <branch name="b3">
- <wire x2="1440" y1="1104" y2="1104" x1="1408" />
- </branch>
- <iomarker fontsize="28" x="1408" y="1104" name="b3" orien="R180" />
- <branch name="b1">
- <wire x2="1184" y1="1168" y2="1168" x1="1152" />
- </branch>
- <iomarker fontsize="28" x="1152" y="1168" name="b1" orien="R180" />
- <branch name="b0">
- <wire x2="1184" y1="1232" y2="1232" x1="1152" />
- </branch>
- <iomarker fontsize="28" x="1152" y="1232" name="b0" orien="R180" />
- <branch name="b3">
- <wire x2="1440" y1="1328" y2="1328" x1="1408" />
- </branch>
- <iomarker fontsize="28" x="1408" y="1328" name="b3" orien="R180" />
- <iomarker fontsize="28" x="1168" y="1392" name="b2" orien="R180" />
- <iomarker fontsize="28" x="1424" y="1456" name="b0" orien="R180" />
- <branch name="result">
- <wire x2="2688" y1="1408" y2="1408" x1="2656" />
- </branch>
- <iomarker fontsize="28" x="2688" y="1408" name="result" orien="R0" />
- <instance x="2400" y="1536" name="XLXI_17" orien="R0" />
- <branch name="XLXN_22">
- <wire x2="1824" y1="1632" y2="1632" x1="1792" />
- </branch>
- <branch name="b3">
- <wire x2="1824" y1="1504" y2="1504" x1="1792" />
- </branch>
- <branch name="b2">
- <wire x2="1824" y1="1568" y2="1568" x1="1792" />
- </branch>
- <branch name="b1">
- <wire x2="1568" y1="1632" y2="1632" x1="1536" />
- </branch>
- <branch name="b0">
- <wire x2="1824" y1="1696" y2="1696" x1="1792" />
- </branch>
- <instance x="1824" y="1760" name="XLXI_13" orien="R0" />
- <instance x="1568" y="1664" name="XLXI_14" orien="R0" />
- <iomarker fontsize="28" x="1792" y="1504" name="b3" orien="R180" />
- <iomarker fontsize="28" x="1792" y="1568" name="b2" orien="R180" />
- <iomarker fontsize="28" x="1536" y="1632" name="b1" orien="R180" />
- <iomarker fontsize="28" x="1792" y="1696" name="b0" orien="R180" />
- <branch name="XLXN_31">
- <wire x2="2240" y1="1600" y2="1600" x1="2080" />
- <wire x2="2400" y1="1408" y2="1408" x1="2240" />
- <wire x2="2240" y1="1408" y2="1600" x1="2240" />
- </branch>
- <branch name="XLXN_23">
- <wire x2="2016" y1="1856" y2="1856" x1="1984" />
- </branch>
- <branch name="XLXN_24">
- <wire x2="2016" y1="1984" y2="1984" x1="1984" />
- </branch>
- <branch name="b3">
- <wire x2="1760" y1="1856" y2="1856" x1="1728" />
- </branch>
- <branch name="b2">
- <wire x2="2016" y1="1920" y2="1920" x1="1984" />
- </branch>
- <branch name="b1">
- <wire x2="1760" y1="1984" y2="1984" x1="1728" />
- </branch>
- <branch name="b0">
- <wire x2="2016" y1="2048" y2="2048" x1="1984" />
- </branch>
- <instance x="2016" y="2112" name="XLXI_11" orien="R0" />
- <instance x="1760" y="1888" name="XLXI_15" orien="R0" />
- <instance x="1760" y="2016" name="XLXI_16" orien="R0" />
- <iomarker fontsize="28" x="1728" y="1856" name="b3" orien="R180" />
- <iomarker fontsize="28" x="1984" y="1920" name="b2" orien="R180" />
- <iomarker fontsize="28" x="1728" y="1984" name="b1" orien="R180" />
- <iomarker fontsize="28" x="1984" y="2048" name="b0" orien="R180" />
- <branch name="XLXN_46">
- <wire x2="2336" y1="1952" y2="1952" x1="2272" />
- <wire x2="2336" y1="1808" y2="1952" x1="2336" />
- <wire x2="2416" y1="1808" y2="1808" x1="2336" />
- <wire x2="2400" y1="1472" y2="1632" x1="2400" />
- <wire x2="2416" y1="1632" y2="1632" x1="2400" />
- <wire x2="2416" y1="1632" y2="1808" x1="2416" />
- </branch>
- </sheet>
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+ <attr value="spartan6" name="DeviceFamilyName">
+ <trait delete="all:0" />
+ <trait editname="all:0" />
+ <trait edittrait="all:0" />
+ </attr>
+ <netlist>
+ <signal name="XLXN_1" />
+ <signal name="XLXN_2" />
+ <signal name="XLXN_3" />
+ <signal name="XLXN_5" />
+ <signal name="XLXN_6" />
+ <signal name="XLXN_7" />
+ <signal name="b3" />
+ <signal name="b2" />
+ <signal name="b1" />
+ <signal name="b0" />
+ <signal name="result" />
+ <signal name="XLXN_23" />
+ <signal name="XLXN_24" />
+ <signal name="XLXN_50" />
+ <signal name="XLXN_51" />
+ <signal name="XLXN_54" />
+ <signal name="XLXN_55" />
+ <signal name="XLXN_56" />
+ <signal name="XLXN_57" />
+ <port polarity="Input" name="b3" />
+ <port polarity="Input" name="b2" />
+ <port polarity="Input" name="b1" />
+ <port polarity="Input" name="b0" />
+ <port polarity="Output" name="result" />
+ <blockdef name="and3">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-64" y2="-64" x1="0" />
+ <line x2="64" y1="-128" y2="-128" x1="0" />
+ <line x2="64" y1="-192" y2="-192" x1="0" />
+ <line x2="192" y1="-128" y2="-128" x1="256" />
+ <line x2="144" y1="-176" y2="-176" x1="64" />
+ <line x2="64" y1="-80" y2="-80" x1="144" />
+ <arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
+ <line x2="64" y1="-64" y2="-192" x1="64" />
+ </blockdef>
+ <blockdef name="inv">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-32" y2="-32" x1="0" />
+ <line x2="160" y1="-32" y2="-32" x1="224" />
+ <line x2="128" y1="-64" y2="-32" x1="64" />
+ <line x2="64" y1="-32" y2="0" x1="128" />
+ <line x2="64" y1="0" y2="-64" x1="64" />
+ <circle r="16" cx="144" cy="-32" />
+ </blockdef>
+ <blockdef name="and4">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-112" y2="-112" x1="144" />
+ <arc ex="144" ey="-208" sx="144" sy="-112" r="48" cx="144" cy="-160" />
+ <line x2="144" y1="-208" y2="-208" x1="64" />
+ <line x2="64" y1="-64" y2="-256" x1="64" />
+ <line x2="192" y1="-160" y2="-160" x1="256" />
+ <line x2="64" y1="-256" y2="-256" x1="0" />
+ <line x2="64" y1="-192" y2="-192" x1="0" />
+ <line x2="64" y1="-128" y2="-128" x1="0" />
+ <line x2="64" y1="-64" y2="-64" x1="0" />
+ </blockdef>
+ <blockdef name="or5">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="48" y1="-64" y2="-64" x1="0" />
+ <line x2="48" y1="-128" y2="-128" x1="0" />
+ <line x2="72" y1="-192" y2="-192" x1="0" />
+ <line x2="48" y1="-256" y2="-256" x1="0" />
+ <line x2="48" y1="-320" y2="-320" x1="0" />
+ <line x2="192" y1="-192" y2="-192" x1="256" />
+ <arc ex="192" ey="-192" sx="112" sy="-144" r="88" cx="116" cy="-232" />
+ <line x2="48" y1="-240" y2="-240" x1="112" />
+ <line x2="48" y1="-144" y2="-144" x1="112" />
+ <line x2="48" y1="-64" y2="-144" x1="48" />
+ <line x2="48" y1="-320" y2="-240" x1="48" />
+ <arc ex="112" ey="-240" sx="192" sy="-192" r="88" cx="116" cy="-152" />
+ <arc ex="48" ey="-240" sx="48" sy="-144" r="56" cx="16" cy="-192" />
+ </blockdef>
+ <block symbolname="and3" name="XLXI_1">
+ <blockpin signalname="b1" name="I0" />
+ <blockpin signalname="b2" name="I1" />
+ <blockpin signalname="b3" name="I2" />
+ <blockpin signalname="XLXN_55" name="O" />
+ </block>
+ <block symbolname="and3" name="XLXI_2">
+ <blockpin signalname="XLXN_6" name="I0" />
+ <blockpin signalname="XLXN_5" name="I1" />
+ <blockpin signalname="b3" name="I2" />
+ <blockpin signalname="XLXN_2" name="O" />
+ </block>
+ <block symbolname="and3" name="XLXI_3">
+ <blockpin signalname="b0" name="I0" />
+ <blockpin signalname="XLXN_7" name="I1" />
+ <blockpin signalname="b3" name="I2" />
+ <blockpin signalname="XLXN_3" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_5">
+ <blockpin signalname="b1" name="I" />
+ <blockpin signalname="XLXN_5" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_6">
+ <blockpin signalname="b0" name="I" />
+ <blockpin signalname="XLXN_6" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_7">
+ <blockpin signalname="b2" name="I" />
+ <blockpin signalname="XLXN_7" name="O" />
+ </block>
+ <block symbolname="and4" name="XLXI_11">
+ <blockpin signalname="b0" name="I0" />
+ <blockpin signalname="XLXN_24" name="I1" />
+ <blockpin signalname="b2" name="I2" />
+ <blockpin signalname="XLXN_23" name="I3" />
+ <blockpin signalname="XLXN_57" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_15">
+ <blockpin signalname="b3" name="I" />
+ <blockpin signalname="XLXN_23" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_16">
+ <blockpin signalname="b1" name="I" />
+ <blockpin signalname="XLXN_24" name="O" />
+ </block>
+ <block symbolname="and4" name="XLXI_18">
+ <blockpin signalname="XLXN_54" name="I0" />
+ <blockpin signalname="b1" name="I1" />
+ <blockpin signalname="XLXN_50" name="I2" />
+ <blockpin signalname="XLXN_51" name="I3" />
+ <blockpin signalname="XLXN_56" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_19">
+ <blockpin signalname="b2" name="I" />
+ <blockpin signalname="XLXN_50" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_20">
+ <blockpin signalname="b3" name="I" />
+ <blockpin signalname="XLXN_51" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_21">
+ <blockpin signalname="b0" name="I" />
+ <blockpin signalname="XLXN_54" name="O" />
+ </block>
+ <block symbolname="or5" name="XLXI_22">
+ <blockpin signalname="XLXN_57" name="I0" />
+ <blockpin signalname="XLXN_56" name="I1" />
+ <blockpin signalname="XLXN_3" name="I2" />
+ <blockpin signalname="XLXN_2" name="I3" />
+ <blockpin signalname="XLXN_55" name="I4" />
+ <blockpin signalname="result" name="O" />
+ </block>
+ </netlist>
+ <sheet sheetnum="1" width="3520" height="2720">
+ <branch name="XLXN_2">
+ <wire x2="1888" y1="1168" y2="1168" x1="1696" />
+ <wire x2="2144" y1="1168" y2="1168" x1="1888" />
+ <wire x2="2144" y1="1168" y2="1344" x1="2144" />
+ <wire x2="2400" y1="1344" y2="1344" x1="2144" />
+ </branch>
+ <branch name="XLXN_3">
+ <wire x2="1888" y1="1392" y2="1392" x1="1696" />
+ <wire x2="1888" y1="1232" y2="1248" x1="1888" />
+ <wire x2="1888" y1="1248" y2="1392" x1="1888" />
+ <wire x2="2128" y1="1232" y2="1232" x1="1888" />
+ <wire x2="2128" y1="1232" y2="1408" x1="2128" />
+ <wire x2="2400" y1="1408" y2="1408" x1="2128" />
+ </branch>
+ <branch name="XLXN_5">
+ <wire x2="1440" y1="1168" y2="1168" x1="1408" />
+ </branch>
+ <branch name="XLXN_6">
+ <wire x2="1440" y1="1232" y2="1232" x1="1408" />
+ </branch>
+ <branch name="XLXN_7">
+ <wire x2="1424" y1="1392" y2="1392" x1="1408" />
+ <wire x2="1440" y1="1392" y2="1392" x1="1424" />
+ </branch>
+ <instance x="1440" y="1056" name="XLXI_1" orien="R0" />
+ <instance x="1440" y="1296" name="XLXI_2" orien="R0" />
+ <instance x="1440" y="1520" name="XLXI_3" orien="R0" />
+ <instance x="1184" y="1200" name="XLXI_5" orien="R0" />
+ <instance x="1184" y="1264" name="XLXI_6" orien="R0" />
+ <branch name="b2">
+ <wire x2="1184" y1="1392" y2="1392" x1="1168" />
+ </branch>
+ <instance x="1184" y="1424" name="XLXI_7" orien="R0" />
+ <branch name="b0">
+ <wire x2="1440" y1="1456" y2="1456" x1="1424" />
+ </branch>
+ <branch name="b3">
+ <wire x2="1440" y1="864" y2="864" x1="1408" />
+ </branch>
+ <iomarker fontsize="28" x="1408" y="864" name="b3" orien="R180" />
+ <branch name="b2">
+ <wire x2="1440" y1="928" y2="928" x1="1408" />
+ </branch>
+ <iomarker fontsize="28" x="1408" y="928" name="b2" orien="R180" />
+ <branch name="b1">
+ <wire x2="1440" y1="992" y2="992" x1="1408" />
+ </branch>
+ <iomarker fontsize="28" x="1408" y="992" name="b1" orien="R180" />
+ <branch name="b3">
+ <wire x2="1440" y1="1104" y2="1104" x1="1408" />
+ </branch>
+ <iomarker fontsize="28" x="1408" y="1104" name="b3" orien="R180" />
+ <branch name="b1">
+ <wire x2="1184" y1="1168" y2="1168" x1="1152" />
+ </branch>
+ <iomarker fontsize="28" x="1152" y="1168" name="b1" orien="R180" />
+ <branch name="b0">
+ <wire x2="1184" y1="1232" y2="1232" x1="1152" />
+ </branch>
+ <iomarker fontsize="28" x="1152" y="1232" name="b0" orien="R180" />
+ <branch name="b3">
+ <wire x2="1424" y1="1328" y2="1328" x1="1408" />
+ <wire x2="1440" y1="1328" y2="1328" x1="1424" />
+ </branch>
+ <iomarker fontsize="28" x="1408" y="1328" name="b3" orien="R180" />
+ <iomarker fontsize="28" x="1168" y="1392" name="b2" orien="R180" />
+ <iomarker fontsize="28" x="1424" y="1456" name="b0" orien="R180" />
+ <branch name="result">
+ <wire x2="2688" y1="1408" y2="1408" x1="2656" />
+ </branch>
+ <iomarker fontsize="28" x="2688" y="1408" name="result" orien="R0" />
+ <branch name="b1">
+ <wire x2="1552" y1="1632" y2="1632" x1="1536" />
+ <wire x2="1568" y1="1632" y2="1632" x1="1552" />
+ <wire x2="1792" y1="1632" y2="1632" x1="1568" />
+ <wire x2="1824" y1="1632" y2="1632" x1="1792" />
+ </branch>
+ <iomarker fontsize="28" x="1536" y="1632" name="b1" orien="R180" />
+ <branch name="XLXN_23">
+ <wire x2="2016" y1="1856" y2="1856" x1="1984" />
+ </branch>
+ <branch name="XLXN_24">
+ <wire x2="2016" y1="1984" y2="1984" x1="1984" />
+ </branch>
+ <branch name="b3">
+ <wire x2="1760" y1="1856" y2="1856" x1="1728" />
+ </branch>
+ <branch name="b2">
+ <wire x2="2016" y1="1920" y2="1920" x1="1984" />
+ </branch>
+ <branch name="b1">
+ <wire x2="1760" y1="1984" y2="1984" x1="1728" />
+ </branch>
+ <branch name="b0">
+ <wire x2="2016" y1="2048" y2="2048" x1="1984" />
+ </branch>
+ <instance x="2016" y="2112" name="XLXI_11" orien="R0" />
+ <instance x="1760" y="1888" name="XLXI_15" orien="R0" />
+ <instance x="1760" y="2016" name="XLXI_16" orien="R0" />
+ <iomarker fontsize="28" x="1728" y="1856" name="b3" orien="R180" />
+ <iomarker fontsize="28" x="1984" y="1920" name="b2" orien="R180" />
+ <iomarker fontsize="28" x="1728" y="1984" name="b1" orien="R180" />
+ <iomarker fontsize="28" x="1984" y="2048" name="b0" orien="R180" />
+ <instance x="1824" y="1760" name="XLXI_18" orien="R0" />
+ <branch name="XLXN_50">
+ <wire x2="1824" y1="1568" y2="1568" x1="1792" />
+ </branch>
+ <instance x="1568" y="1600" name="XLXI_19" orien="R0" />
+ <branch name="XLXN_51">
+ <wire x2="1824" y1="1504" y2="1504" x1="1792" />
+ </branch>
+ <instance x="1568" y="1536" name="XLXI_20" orien="R0" />
+ <branch name="b3">
+ <wire x2="1568" y1="1504" y2="1504" x1="1536" />
+ </branch>
+ <iomarker fontsize="28" x="1536" y="1504" name="b3" orien="R180" />
+ <branch name="b2">
+ <wire x2="1568" y1="1568" y2="1568" x1="1536" />
+ </branch>
+ <iomarker fontsize="28" x="1536" y="1568" name="b2" orien="R180" />
+ <branch name="XLXN_54">
+ <wire x2="1824" y1="1696" y2="1696" x1="1792" />
+ </branch>
+ <instance x="1568" y="1728" name="XLXI_21" orien="R0" />
+ <branch name="b0">
+ <wire x2="1568" y1="1696" y2="1696" x1="1536" />
+ </branch>
+ <iomarker fontsize="28" x="1536" y="1696" name="b0" orien="R180" />
+ <instance x="2400" y="1600" name="XLXI_22" orien="R0" />
+ <branch name="XLXN_55">
+ <wire x2="1888" y1="928" y2="928" x1="1696" />
+ <wire x2="1888" y1="928" y2="1104" x1="1888" />
+ <wire x2="2400" y1="1104" y2="1104" x1="1888" />
+ <wire x2="2400" y1="1104" y2="1280" x1="2400" />
+ </branch>
+ <branch name="XLXN_56">
+ <wire x2="2240" y1="1600" y2="1600" x1="2080" />
+ <wire x2="2240" y1="1472" y2="1600" x1="2240" />
+ <wire x2="2400" y1="1472" y2="1472" x1="2240" />
+ </branch>
+ <branch name="XLXN_57">
+ <wire x2="2400" y1="1952" y2="1952" x1="2272" />
+ <wire x2="2400" y1="1536" y2="1952" x1="2400" />
+ </branch>
+ </sheet>
</drawing> \ No newline at end of file
diff --git a/Modulo_1.sym b/Modulo_1.sym
index cff6acb..42ecca1 100755
--- a/Modulo_1.sym
+++ b/Modulo_1.sym
@@ -1,24 +1,24 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="Modulo_1">
- <symboltype>BLOCK</symboltype>
- <timestamp>2012-2-16T0:29:44</timestamp>
- <pin polarity="Input" x="0" y="-224" name="b3" />
- <pin polarity="Input" x="0" y="-160" name="b2" />
- <pin polarity="Input" x="0" y="-96" name="b1" />
- <pin polarity="Input" x="0" y="-32" name="b0" />
- <pin polarity="Output" x="384" y="-224" name="result" />
- <graph>
- <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b3" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b2" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b1" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b0" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </graph>
-</symbol>
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="Modulo_1">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-17T0:43:13</timestamp>
+ <pin polarity="Input" x="0" y="-224" name="b3" />
+ <pin polarity="Input" x="0" y="-160" name="b2" />
+ <pin polarity="Input" x="0" y="-96" name="b1" />
+ <pin polarity="Input" x="0" y="-32" name="b0" />
+ <pin polarity="Output" x="384" y="-224" name="result" />
+ <graph>
+ <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b3" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b2" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b1" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b0" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </graph>
+</symbol>
diff --git a/Modulo_1.vf b/Modulo_1.vf
index 8232c5f..5f6247d 100755
--- a/Modulo_1.vf
+++ b/Modulo_1.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Modulo_1.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:10
+// /___/ /\ Timestamp : 02/16/2012 19:44:03
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Modulo_1.vf" -w "X:/My Documents/ec311/lab1/Modulo_1.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Modulo_1.vf" -w "X:/My Documents/ec311/ec311-lab1/Modulo_1.sch"
//Design Name: Modulo_1
//Device: spartan6
//Purpose:
@@ -32,24 +32,24 @@ module Modulo_1(b0,
input b3;
output result;
- wire XLXN_1;
wire XLXN_2;
wire XLXN_3;
wire XLXN_5;
wire XLXN_6;
wire XLXN_7;
- wire XLXN_18;
- wire XLXN_19;
- wire XLXN_20;
- wire XLXN_21;
- wire XLXN_22;
wire XLXN_23;
wire XLXN_24;
+ wire XLXN_50;
+ wire XLXN_51;
+ wire XLXN_54;
+ wire XLXN_55;
+ wire XLXN_56;
+ wire XLXN_57;
AND3 XLXI_1 (.I0(b1),
.I1(b2),
.I2(b3),
- .O(XLXN_1));
+ .O(XLXN_55));
AND3 XLXI_2 (.I0(XLXN_6),
.I1(XLXN_5),
.I2(b3),
@@ -58,36 +58,36 @@ module Modulo_1(b0,
.I1(XLXN_7),
.I2(b3),
.O(XLXN_3));
- OR3 XLXI_4 (.I0(XLXN_3),
- .I1(XLXN_2),
- .I2(XLXN_1),
- .O(XLXN_21));
INV XLXI_5 (.I(b1),
.O(XLXN_5));
INV XLXI_6 (.I(b0),
.O(XLXN_6));
INV XLXI_7 (.I(b2),
.O(XLXN_7));
- OR2 XLXI_9 (.I0(XLXN_20),
- .I1(XLXN_21),
- .O(result));
AND4 XLXI_11 (.I0(b0),
.I1(XLXN_24),
.I2(b2),
.I3(XLXN_23),
- .O(XLXN_19));
- OR2 XLXI_12 (.I0(XLXN_19),
- .I1(XLXN_18),
- .O(XLXN_20));
- NAND4 XLXI_13 (.I0(b0),
- .I1(XLXN_22),
- .I2(b2),
- .I3(b3),
- .O(XLXN_18));
- INV XLXI_14 (.I(b1),
- .O(XLXN_22));
+ .O(XLXN_57));
INV XLXI_15 (.I(b3),
.O(XLXN_23));
INV XLXI_16 (.I(b1),
.O(XLXN_24));
+ AND4 XLXI_18 (.I0(XLXN_54),
+ .I1(b1),
+ .I2(XLXN_50),
+ .I3(XLXN_51),
+ .O(XLXN_56));
+ INV XLXI_19 (.I(b2),
+ .O(XLXN_50));
+ INV XLXI_20 (.I(b3),
+ .O(XLXN_51));
+ INV XLXI_21 (.I(b0),
+ .O(XLXN_54));
+ OR5 XLXI_22 (.I0(XLXN_57),
+ .I1(XLXN_56),
+ .I2(XLXN_3),
+ .I3(XLXN_2),
+ .I4(XLXN_55),
+ .O(result));
endmodule
diff --git a/Modulo_3.cmd_log b/Modulo_3.cmd_log
index 0734386..bd30288 100755
--- a/Modulo_3.cmd_log
+++ b/Modulo_3.cmd_log
@@ -1,2 +1,4 @@
sch2sym -intstyle ise -family spartan6 -refsym Modulo_3 {X:/My Documents/ec311/lab1/Modulo_3.sch} {X:/My Documents/ec311/lab1/Modulo_3.sym}
sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_3 /home/michael/Documents/School/EC311/lab1/Modulo_3.sch /home/michael/Documents/School/EC311/lab1/Modulo_3.sym
+sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_3 {X:/My Documents/ec311/ec311-lab1/Modulo_3.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_3.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_3 {X:/My Documents/ec311/ec311-lab1/Modulo_3.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_3.sym}
diff --git a/Modulo_3.schlog b/Modulo_3.schlog
new file mode 100755
index 0000000..69e4688
--- /dev/null
+++ b/Modulo_3.schlog
@@ -0,0 +1,2 @@
+select figure at 1561 1090 8 -branches -sn=1
+select figure at 1554 1281 8 -branches -sn=1
diff --git a/Modulo_3.sym b/Modulo_3.sym
index de3738d..63f2cb1 100755
--- a/Modulo_3.sym
+++ b/Modulo_3.sym
@@ -1,24 +1,24 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="Modulo_3">
- <symboltype>BLOCK</symboltype>
- <timestamp>2012-2-16T0:29:41</timestamp>
- <pin polarity="Input" x="0" y="-224" name="b3" />
- <pin polarity="Input" x="0" y="-160" name="b0" />
- <pin polarity="Input" x="0" y="-96" name="b1" />
- <pin polarity="Input" x="0" y="-32" name="b2" />
- <pin polarity="Output" x="384" y="-224" name="result" />
- <graph>
- <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b3" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b0" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b1" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b2" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </graph>
-</symbol>
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="Modulo_3">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-17T0:37:33</timestamp>
+ <pin polarity="Input" x="0" y="-224" name="b3" />
+ <pin polarity="Input" x="0" y="-160" name="b0" />
+ <pin polarity="Input" x="0" y="-96" name="b1" />
+ <pin polarity="Input" x="0" y="-32" name="b2" />
+ <pin polarity="Output" x="384" y="-224" name="result" />
+ <graph>
+ <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b3" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b1" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b2" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </graph>
+</symbol>
diff --git a/Modulo_3.vf b/Modulo_3.vf
index eef4bc0..50f1c0d 100755
--- a/Modulo_3.vf
+++ b/Modulo_3.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Modulo_3.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:10
+// /___/ /\ Timestamp : 02/16/2012 18:40:31
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Modulo_3.vf" -w "X:/My Documents/ec311/lab1/Modulo_3.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Modulo_3.vf" -w "X:/My Documents/ec311/ec311-lab1/Modulo_3.sch"
//Design Name: Modulo_3
//Device: spartan6
//Purpose:
diff --git a/Negate.cmd_log b/Negate.cmd_log
index f6426a6..28d7294 100755
--- a/Negate.cmd_log
+++ b/Negate.cmd_log
@@ -1,2 +1,6 @@
sch2sym -intstyle ise -family spartan6 -refsym Negate {X:/My Documents/ec311/lab1/Negate.sch} {X:/My Documents/ec311/lab1/Negate.sym}
sch2sym -intstyle ise -family spartan6 -w -refsym Negate /home/michael/Documents/School/EC311/lab1/Negate.sch /home/michael/Documents/School/EC311/lab1/Negate.sym
+sch2sym -intstyle ise -family spartan6 -w -refsym Negate {X:/My Documents/ec311/ec311-lab1/Negate.sch} {X:/My Documents/ec311/ec311-lab1/Negate.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Negate {X:/My Documents/ec311/ec311-lab1/Negate.sch} {X:/My Documents/ec311/ec311-lab1/Negate.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Negate {X:/My Documents/ec311/ec311-lab1/Negate.sch} {X:/My Documents/ec311/ec311-lab1/Negate.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Negate {X:/My Documents/ec311/ec311-lab1/Negate.sch} {X:/My Documents/ec311/ec311-lab1/Negate.sym}
diff --git a/Negate.jhd b/Negate.jhd
index 1fc293d..2436bdf 100755
--- a/Negate.jhd
+++ b/Negate.jhd
@@ -1,9 +1,9 @@
-MODULE Negate
- SUBMODULE Negate_0
- INSTANCE XLXI_8
- SUBMODULE Negate_1
- INSTANCE XLXI_9
- SUBMODULE Negate_2
- INSTANCE XLXI_10
- SUBMODULE Negate_3
- INSTANCE XLXI_12
+MODULE Negate
+ SUBMODULE Negate_0
+ INSTANCE XLXI_8
+ SUBMODULE Negate_1
+ INSTANCE XLXI_9
+ SUBMODULE Negate_2
+ INSTANCE XLXI_10
+ SUBMODULE Negate_3
+ INSTANCE XLXI_12
diff --git a/Negate.sch b/Negate.sch
index e61f5b1..5d0ac8c 100755
--- a/Negate.sch
+++ b/Negate.sch
@@ -1,170 +1,170 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<drawing version="7">
- <attr value="spartan6" name="DeviceFamilyName">
- <trait delete="all:0" />
- <trait editname="all:0" />
- <trait edittrait="all:0" />
- </attr>
- <netlist>
- <signal name="b0" />
- <signal name="b2" />
- <signal name="b3" />
- <signal name="b1" />
- <signal name="out2" />
- <signal name="out1" />
- <signal name="out0" />
- <signal name="out3" />
- <port polarity="Input" name="b0" />
- <port polarity="Input" name="b2" />
- <port polarity="Input" name="b3" />
- <port polarity="Input" name="b1" />
- <port polarity="Output" name="out2" />
- <port polarity="Output" name="out1" />
- <port polarity="Output" name="out0" />
- <port polarity="Output" name="out3" />
- <blockdef name="Negate_0">
- <timestamp>2012-2-16T0:44:2</timestamp>
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </blockdef>
- <blockdef name="Negate_1">
- <timestamp>2012-2-16T0:43:59</timestamp>
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </blockdef>
- <blockdef name="Negate_2">
- <timestamp>2012-2-16T0:43:56</timestamp>
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </blockdef>
- <blockdef name="Negate_3">
- <timestamp>2012-2-16T0:43:52</timestamp>
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </blockdef>
- <block symbolname="Negate_0" name="XLXI_8">
- <blockpin signalname="b0" name="b0" />
- <blockpin signalname="b1" name="b1" />
- <blockpin signalname="b2" name="b2" />
- <blockpin signalname="b3" name="b3" />
- <blockpin signalname="out0" name="result" />
- </block>
- <block symbolname="Negate_2" name="XLXI_10">
- <blockpin signalname="b2" name="b2" />
- <blockpin signalname="b3" name="b3" />
- <blockpin signalname="b0" name="b0" />
- <blockpin signalname="b1" name="b1" />
- <blockpin signalname="out2" name="result" />
- </block>
- <block symbolname="Negate_1" name="XLXI_9">
- <blockpin signalname="b0" name="b0" />
- <blockpin signalname="b1" name="b1" />
- <blockpin signalname="b2" name="b2" />
- <blockpin signalname="b3" name="b3" />
- <blockpin signalname="out1" name="result" />
- </block>
- <block symbolname="Negate_3" name="XLXI_12">
- <blockpin signalname="b3" name="b3" />
- <blockpin signalname="b2" name="b0" />
- <blockpin signalname="b1" name="b1" />
- <blockpin signalname="b0" name="b2" />
- <blockpin signalname="out3" name="result" />
- </block>
- </netlist>
- <sheet sheetnum="1" width="3520" height="2720">
- <instance x="1248" y="1216" name="XLXI_8" orien="R0">
- </instance>
- <instance x="1248" y="1888" name="XLXI_10" orien="R0">
- </instance>
- <branch name="b0">
- <wire x2="1232" y1="992" y2="992" x1="864" />
- <wire x2="1248" y1="992" y2="992" x1="1232" />
- <wire x2="1232" y1="992" y2="1328" x1="1232" />
- <wire x2="1248" y1="1328" y2="1328" x1="1232" />
- <wire x2="1232" y1="1328" y2="1664" x1="1232" />
- <wire x2="1248" y1="1664" y2="1664" x1="1232" />
- <wire x2="1232" y1="1664" y2="2256" x1="1232" />
- <wire x2="1248" y1="2256" y2="2256" x1="1232" />
- </branch>
- <branch name="b2">
- <wire x2="1200" y1="1136" y2="1136" x1="864" />
- <wire x2="1200" y1="1136" y2="1456" x1="1200" />
- <wire x2="1248" y1="1456" y2="1456" x1="1200" />
- <wire x2="1200" y1="1456" y2="1792" x1="1200" />
- <wire x2="1248" y1="1792" y2="1792" x1="1200" />
- <wire x2="1200" y1="1792" y2="2128" x1="1200" />
- <wire x2="1248" y1="2128" y2="2128" x1="1200" />
- <wire x2="1248" y1="1120" y2="1120" x1="1200" />
- <wire x2="1200" y1="1120" y2="1136" x1="1200" />
- </branch>
- <instance x="1248" y="1552" name="XLXI_9" orien="R0">
- </instance>
- <branch name="b1">
- <wire x2="1168" y1="1072" y2="1072" x1="864" />
- <wire x2="1168" y1="1072" y2="1392" x1="1168" />
- <wire x2="1248" y1="1392" y2="1392" x1="1168" />
- <wire x2="1168" y1="1392" y2="1728" x1="1168" />
- <wire x2="1248" y1="1728" y2="1728" x1="1168" />
- <wire x2="1168" y1="1728" y2="2192" x1="1168" />
- <wire x2="1248" y1="2192" y2="2192" x1="1168" />
- <wire x2="1248" y1="1056" y2="1056" x1="1168" />
- <wire x2="1168" y1="1056" y2="1072" x1="1168" />
- </branch>
- <iomarker fontsize="28" x="864" y="992" name="b0" orien="R180" />
- <iomarker fontsize="28" x="864" y="1072" name="b1" orien="R180" />
- <iomarker fontsize="28" x="864" y="1184" name="b3" orien="R180" />
- <iomarker fontsize="28" x="864" y="1136" name="b2" orien="R180" />
- <instance x="1248" y="2288" name="XLXI_12" orien="R0">
- </instance>
- <branch name="b3">
- <wire x2="1184" y1="1184" y2="1184" x1="864" />
- <wire x2="1248" y1="1184" y2="1184" x1="1184" />
- <wire x2="1184" y1="1184" y2="1520" x1="1184" />
- <wire x2="1248" y1="1520" y2="1520" x1="1184" />
- <wire x2="1184" y1="1520" y2="1856" x1="1184" />
- <wire x2="1248" y1="1856" y2="1856" x1="1184" />
- <wire x2="1184" y1="1856" y2="2064" x1="1184" />
- <wire x2="1248" y1="2064" y2="2064" x1="1184" />
- </branch>
- <branch name="out2">
- <wire x2="1696" y1="1664" y2="1664" x1="1632" />
- <wire x2="1696" y1="1664" y2="1680" x1="1696" />
- <wire x2="1840" y1="1680" y2="1680" x1="1696" />
- </branch>
- <branch name="out1">
- <wire x2="1696" y1="1328" y2="1328" x1="1632" />
- <wire x2="1696" y1="1328" y2="1344" x1="1696" />
- <wire x2="1840" y1="1344" y2="1344" x1="1696" />
- </branch>
- <branch name="out0">
- <wire x2="1696" y1="992" y2="992" x1="1632" />
- <wire x2="1696" y1="992" y2="1008" x1="1696" />
- <wire x2="1840" y1="1008" y2="1008" x1="1696" />
- </branch>
- <branch name="out3">
- <wire x2="1824" y1="2064" y2="2064" x1="1632" />
- <wire x2="1856" y1="2000" y2="2000" x1="1824" />
- <wire x2="1824" y1="2000" y2="2064" x1="1824" />
- </branch>
- <iomarker fontsize="28" x="1840" y="1008" name="out0" orien="R0" />
- <iomarker fontsize="28" x="1840" y="1344" name="out1" orien="R0" />
- <iomarker fontsize="28" x="1840" y="1680" name="out2" orien="R0" />
- <iomarker fontsize="28" x="1856" y="2000" name="out3" orien="R0" />
- </sheet>
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+ <attr value="spartan6" name="DeviceFamilyName">
+ <trait delete="all:0" />
+ <trait editname="all:0" />
+ <trait edittrait="all:0" />
+ </attr>
+ <netlist>
+ <signal name="b0" />
+ <signal name="b2" />
+ <signal name="b3" />
+ <signal name="b1" />
+ <signal name="out2" />
+ <signal name="out1" />
+ <signal name="out0" />
+ <signal name="out3" />
+ <port polarity="Input" name="b0" />
+ <port polarity="Input" name="b2" />
+ <port polarity="Input" name="b3" />
+ <port polarity="Input" name="b1" />
+ <port polarity="Output" name="out2" />
+ <port polarity="Output" name="out1" />
+ <port polarity="Output" name="out0" />
+ <port polarity="Output" name="out3" />
+ <blockdef name="Negate_0">
+ <timestamp>2012-2-16T23:39:45</timestamp>
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </blockdef>
+ <blockdef name="Negate_1">
+ <timestamp>2012-2-16T23:39:49</timestamp>
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </blockdef>
+ <blockdef name="Negate_2">
+ <timestamp>2012-2-16T23:53:56</timestamp>
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ <rect width="256" x="64" y="-256" height="320" />
+ </blockdef>
+ <blockdef name="Negate_3">
+ <timestamp>2012-2-16T23:39:56</timestamp>
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </blockdef>
+ <block symbolname="Negate_0" name="XLXI_8">
+ <blockpin signalname="b0" name="b0" />
+ <blockpin signalname="b1" name="b1" />
+ <blockpin signalname="b2" name="b2" />
+ <blockpin signalname="b3" name="b3" />
+ <blockpin signalname="out0" name="result" />
+ </block>
+ <block symbolname="Negate_2" name="XLXI_10">
+ <blockpin signalname="b2" name="b2" />
+ <blockpin signalname="b3" name="b3" />
+ <blockpin signalname="b0" name="b0" />
+ <blockpin signalname="b1" name="b1" />
+ <blockpin signalname="out2" name="result" />
+ </block>
+ <block symbolname="Negate_1" name="XLXI_9">
+ <blockpin signalname="b0" name="b0" />
+ <blockpin signalname="b1" name="b1" />
+ <blockpin signalname="b2" name="b2" />
+ <blockpin signalname="b3" name="b3" />
+ <blockpin signalname="out1" name="result" />
+ </block>
+ <block symbolname="Negate_3" name="XLXI_12">
+ <blockpin signalname="b3" name="b3" />
+ <blockpin signalname="b2" name="b0" />
+ <blockpin signalname="b1" name="b1" />
+ <blockpin signalname="b0" name="b2" />
+ <blockpin signalname="out3" name="result" />
+ </block>
+ </netlist>
+ <sheet sheetnum="1" width="3520" height="2720">
+ <instance x="1248" y="1216" name="XLXI_8" orien="R0">
+ </instance>
+ <instance x="1248" y="1888" name="XLXI_10" orien="R0">
+ </instance>
+ <branch name="b0">
+ <wire x2="1232" y1="992" y2="992" x1="864" />
+ <wire x2="1248" y1="992" y2="992" x1="1232" />
+ <wire x2="1232" y1="992" y2="1328" x1="1232" />
+ <wire x2="1248" y1="1328" y2="1328" x1="1232" />
+ <wire x2="1232" y1="1328" y2="1664" x1="1232" />
+ <wire x2="1248" y1="1664" y2="1664" x1="1232" />
+ <wire x2="1232" y1="1664" y2="2256" x1="1232" />
+ <wire x2="1248" y1="2256" y2="2256" x1="1232" />
+ </branch>
+ <branch name="b2">
+ <wire x2="1200" y1="1136" y2="1136" x1="864" />
+ <wire x2="1200" y1="1136" y2="1456" x1="1200" />
+ <wire x2="1248" y1="1456" y2="1456" x1="1200" />
+ <wire x2="1200" y1="1456" y2="1792" x1="1200" />
+ <wire x2="1248" y1="1792" y2="1792" x1="1200" />
+ <wire x2="1200" y1="1792" y2="2128" x1="1200" />
+ <wire x2="1248" y1="2128" y2="2128" x1="1200" />
+ <wire x2="1248" y1="1120" y2="1120" x1="1200" />
+ <wire x2="1200" y1="1120" y2="1136" x1="1200" />
+ </branch>
+ <instance x="1248" y="1552" name="XLXI_9" orien="R0">
+ </instance>
+ <branch name="b1">
+ <wire x2="1168" y1="1072" y2="1072" x1="864" />
+ <wire x2="1168" y1="1072" y2="1392" x1="1168" />
+ <wire x2="1248" y1="1392" y2="1392" x1="1168" />
+ <wire x2="1168" y1="1392" y2="1728" x1="1168" />
+ <wire x2="1248" y1="1728" y2="1728" x1="1168" />
+ <wire x2="1168" y1="1728" y2="2192" x1="1168" />
+ <wire x2="1248" y1="2192" y2="2192" x1="1168" />
+ <wire x2="1248" y1="1056" y2="1056" x1="1168" />
+ <wire x2="1168" y1="1056" y2="1072" x1="1168" />
+ </branch>
+ <iomarker fontsize="28" x="864" y="992" name="b0" orien="R180" />
+ <iomarker fontsize="28" x="864" y="1072" name="b1" orien="R180" />
+ <iomarker fontsize="28" x="864" y="1184" name="b3" orien="R180" />
+ <iomarker fontsize="28" x="864" y="1136" name="b2" orien="R180" />
+ <instance x="1248" y="2288" name="XLXI_12" orien="R0">
+ </instance>
+ <branch name="b3">
+ <wire x2="1184" y1="1184" y2="1184" x1="864" />
+ <wire x2="1248" y1="1184" y2="1184" x1="1184" />
+ <wire x2="1184" y1="1184" y2="1520" x1="1184" />
+ <wire x2="1248" y1="1520" y2="1520" x1="1184" />
+ <wire x2="1184" y1="1520" y2="1856" x1="1184" />
+ <wire x2="1248" y1="1856" y2="1856" x1="1184" />
+ <wire x2="1184" y1="1856" y2="2064" x1="1184" />
+ <wire x2="1248" y1="2064" y2="2064" x1="1184" />
+ </branch>
+ <branch name="out2">
+ <wire x2="1696" y1="1664" y2="1664" x1="1632" />
+ <wire x2="1696" y1="1664" y2="1680" x1="1696" />
+ <wire x2="1840" y1="1680" y2="1680" x1="1696" />
+ </branch>
+ <branch name="out1">
+ <wire x2="1696" y1="1328" y2="1328" x1="1632" />
+ <wire x2="1696" y1="1328" y2="1344" x1="1696" />
+ <wire x2="1840" y1="1344" y2="1344" x1="1696" />
+ </branch>
+ <branch name="out0">
+ <wire x2="1696" y1="992" y2="992" x1="1632" />
+ <wire x2="1696" y1="992" y2="1008" x1="1696" />
+ <wire x2="1840" y1="1008" y2="1008" x1="1696" />
+ </branch>
+ <branch name="out3">
+ <wire x2="1824" y1="2064" y2="2064" x1="1632" />
+ <wire x2="1856" y1="2000" y2="2000" x1="1824" />
+ <wire x2="1824" y1="2000" y2="2064" x1="1824" />
+ </branch>
+ <iomarker fontsize="28" x="1840" y="1008" name="out0" orien="R0" />
+ <iomarker fontsize="28" x="1840" y="1344" name="out1" orien="R0" />
+ <iomarker fontsize="28" x="1840" y="1680" name="out2" orien="R0" />
+ <iomarker fontsize="28" x="1856" y="2000" name="out3" orien="R0" />
+ </sheet>
</drawing> \ No newline at end of file
diff --git a/Negate.schlog b/Negate.schlog
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/Negate.schlog
diff --git a/Negate.sym b/Negate.sym
index 7528c93..7492348 100755
--- a/Negate.sym
+++ b/Negate.sym
@@ -1,33 +1,33 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="Negate">
- <symboltype>BLOCK</symboltype>
- <timestamp>2012-2-16T0:44:17</timestamp>
- <pin polarity="Input" x="0" y="-224" name="b0" />
- <pin polarity="Input" x="0" y="-160" name="b2" />
- <pin polarity="Input" x="0" y="-96" name="b3" />
- <pin polarity="Input" x="0" y="-32" name="b1" />
- <pin polarity="Output" x="384" y="-224" name="out2" />
- <pin polarity="Output" x="384" y="-160" name="out1" />
- <pin polarity="Output" x="384" y="-96" name="out0" />
- <pin polarity="Output" x="384" y="-32" name="out3" />
- <graph>
- <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b0" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b2" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b3" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b1" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin out2" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin out1" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin out0" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin out3" />
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- <line x2="384" y1="-160" y2="-160" x1="320" />
- <line x2="384" y1="-96" y2="-96" x1="320" />
- <line x2="384" y1="-32" y2="-32" x1="320" />
- </graph>
-</symbol>
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="Negate">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-16T23:54:10</timestamp>
+ <pin polarity="Input" x="0" y="-224" name="b0" />
+ <pin polarity="Input" x="0" y="-160" name="b2" />
+ <pin polarity="Input" x="0" y="-96" name="b3" />
+ <pin polarity="Input" x="0" y="-32" name="b1" />
+ <pin polarity="Output" x="384" y="-224" name="out2" />
+ <pin polarity="Output" x="384" y="-160" name="out1" />
+ <pin polarity="Output" x="384" y="-96" name="out0" />
+ <pin polarity="Output" x="384" y="-32" name="out3" />
+ <graph>
+ <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b2" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b3" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b1" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin out2" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin out1" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin out0" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin out3" />
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ <line x2="384" y1="-160" y2="-160" x1="320" />
+ <line x2="384" y1="-96" y2="-96" x1="320" />
+ <line x2="384" y1="-32" y2="-32" x1="320" />
+ </graph>
+</symbol>
diff --git a/Negate.vf b/Negate.vf
index 2f68f03..eb96691 100755
--- a/Negate.vf
+++ b/Negate.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Negate.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:10
+// /___/ /\ Timestamp : 02/16/2012 18:54:27
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate.vf" -w "X:/My Documents/ec311/lab1/Negate.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Negate.vf" -w "X:/My Documents/ec311/ec311-lab1/Negate.sch"
//Design Name: Negate
//Device: spartan6
//Purpose:
@@ -33,17 +33,17 @@ module Negate_3_MUSER_Negate(b0,
output result;
wire XLXN_8;
- wire XLXN_9;
+ wire XLXN_10;
- OR3 XLXI_5 (.I0(b2),
- .I1(b1),
- .I2(b0),
- .O(XLXN_9));
- NAND2 XLXI_9 (.I0(XLXN_8),
- .I1(b3),
- .O(result));
- INV XLXI_12 (.I(XLXN_9),
+ OR3 XLXI_14 (.I0(b2),
+ .I1(b1),
+ .I2(b0),
.O(XLXN_8));
+ INV XLXI_15 (.I(b3),
+ .O(XLXN_10));
+ AND2 XLXI_16 (.I0(XLXN_8),
+ .I1(XLXN_10),
+ .O(result));
endmodule
`timescale 1ns / 1ps
@@ -101,33 +101,38 @@ module Negate_2_MUSER_Negate(b0,
input b3;
output result;
- wire XLXN_7;
- wire XLXN_9;
- wire XLXN_10;
- wire XLXN_12;
- wire XLXN_16;
- wire XLXN_17;
+ wire XLXN_35;
+ wire XLXN_37;
+ wire XLXN_40;
+ wire XLXN_41;
+ wire XLXN_44;
+ wire XLXN_47;
+ wire XLXN_49;
- AND2 XLXI_1 (.I0(XLXN_7),
- .I1(b3),
- .O(XLXN_9));
- AND3 XLXI_2 (.I0(b2),
- .I1(XLXN_16),
- .I2(XLXN_17),
- .O(XLXN_10));
- OR2 XLXI_3 (.I0(XLXN_10),
- .I1(XLXN_9),
+ OR4 XLXI_8 (.I0(XLXN_37),
+ .I1(XLXN_41),
+ .I2(XLXN_40),
+ .I3(XLXN_35),
.O(result));
- OR3 XLXI_4 (.I0(XLXN_12),
- .I1(b1),
- .I2(b0),
- .O(XLXN_7));
- INV XLXI_5 (.I(b2),
- .O(XLXN_12));
- INV XLXI_6 (.I(b1),
- .O(XLXN_16));
- INV XLXI_7 (.I(b0),
- .O(XLXN_17));
+ AND2 XLXI_9 (.I0(XLXN_44),
+ .I1(b3),
+ .O(XLXN_35));
+ AND2 XLXI_10 (.I0(b1),
+ .I1(XLXN_44),
+ .O(XLXN_41));
+ AND2 XLXI_11 (.I0(b0),
+ .I1(XLXN_44),
+ .O(XLXN_40));
+ INV XLXI_14 (.I(b2),
+ .O(XLXN_44));
+ AND3 XLXI_15 (.I0(XLXN_47),
+ .I1(XLXN_49),
+ .I2(b2),
+ .O(XLXN_37));
+ INV XLXI_16 (.I(b1),
+ .O(XLXN_49));
+ INV XLXI_17 (.I(b0),
+ .O(XLXN_47));
endmodule
`timescale 1ns / 1ps
diff --git a/Negate_0.cmd_log b/Negate_0.cmd_log
index c334167..757de99 100755
--- a/Negate_0.cmd_log
+++ b/Negate_0.cmd_log
@@ -1,2 +1,4 @@
sch2sym -intstyle ise -family spartan6 -refsym Negate_0 {X:/My Documents/ec311/lab1/Negate_0.sch} {X:/My Documents/ec311/lab1/Negate_0.sym}
sch2sym -intstyle ise -family spartan6 -w -refsym Negate_0 /home/michael/Documents/School/EC311/lab1/Negate_0.sch /home/michael/Documents/School/EC311/lab1/Negate_0.sym
+sch2sym -intstyle ise -family spartan6 -w -refsym Negate_0 {X:/My Documents/ec311/ec311-lab1/Negate_0.sch} {X:/My Documents/ec311/ec311-lab1/Negate_0.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Negate_0 {X:/My Documents/ec311/ec311-lab1/Negate_0.sch} {X:/My Documents/ec311/ec311-lab1/Negate_0.sym}
diff --git a/Negate_0.sym b/Negate_0.sym
index 06adc0f..b101625 100755
--- a/Negate_0.sym
+++ b/Negate_0.sym
@@ -1,24 +1,24 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="Negate_0">
- <symboltype>BLOCK</symboltype>
- <timestamp>2012-2-16T0:44:2</timestamp>
- <pin polarity="Input" x="0" y="-224" name="b0" />
- <pin polarity="Input" x="0" y="-160" name="b1" />
- <pin polarity="Input" x="0" y="-96" name="b2" />
- <pin polarity="Input" x="0" y="-32" name="b3" />
- <pin polarity="Output" x="384" y="-224" name="result" />
- <graph>
- <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b0" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b1" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b2" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b3" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </graph>
-</symbol>
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="Negate_0">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-16T23:39:45</timestamp>
+ <pin polarity="Input" x="0" y="-224" name="b0" />
+ <pin polarity="Input" x="0" y="-160" name="b1" />
+ <pin polarity="Input" x="0" y="-96" name="b2" />
+ <pin polarity="Input" x="0" y="-32" name="b3" />
+ <pin polarity="Output" x="384" y="-224" name="result" />
+ <graph>
+ <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b1" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b2" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b3" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </graph>
+</symbol>
diff --git a/Negate_0.vf b/Negate_0.vf
index 4ea3c60..3bdfa8b 100755
--- a/Negate_0.vf
+++ b/Negate_0.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Negate_0.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:09
+// /___/ /\ Timestamp : 02/16/2012 18:40:37
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate_0.vf" -w "X:/My Documents/ec311/lab1/Negate_0.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Negate_0.vf" -w "X:/My Documents/ec311/ec311-lab1/Negate_0.sch"
//Design Name: Negate_0
//Device: spartan6
//Purpose:
diff --git a/Negate_1.cmd_log b/Negate_1.cmd_log
index 8255945..c566d5e 100755
--- a/Negate_1.cmd_log
+++ b/Negate_1.cmd_log
@@ -1,2 +1,4 @@
sch2sym -intstyle ise -family spartan6 -refsym Negate_1 {X:/My Documents/ec311/lab1/Negate_1.sch} {X:/My Documents/ec311/lab1/Negate_1.sym}
sch2sym -intstyle ise -family spartan6 -w -refsym Negate_1 /home/michael/Documents/School/EC311/lab1/Negate_1.sch /home/michael/Documents/School/EC311/lab1/Negate_1.sym
+sch2sym -intstyle ise -family spartan6 -w -refsym Negate_1 {X:/My Documents/ec311/ec311-lab1/Negate_1.sch} {X:/My Documents/ec311/ec311-lab1/Negate_1.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Negate_1 {X:/My Documents/ec311/ec311-lab1/Negate_1.sch} {X:/My Documents/ec311/ec311-lab1/Negate_1.sym}
diff --git a/Negate_1.sym b/Negate_1.sym
index bd9722a..c530133 100755
--- a/Negate_1.sym
+++ b/Negate_1.sym
@@ -1,24 +1,24 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="Negate_1">
- <symboltype>BLOCK</symboltype>
- <timestamp>2012-2-16T0:43:59</timestamp>
- <pin polarity="Input" x="0" y="-224" name="b0" />
- <pin polarity="Input" x="0" y="-160" name="b1" />
- <pin polarity="Input" x="0" y="-96" name="b2" />
- <pin polarity="Input" x="0" y="-32" name="b3" />
- <pin polarity="Output" x="384" y="-224" name="result" />
- <graph>
- <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b0" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b1" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b2" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b3" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </graph>
-</symbol>
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="Negate_1">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-16T23:39:49</timestamp>
+ <pin polarity="Input" x="0" y="-224" name="b0" />
+ <pin polarity="Input" x="0" y="-160" name="b1" />
+ <pin polarity="Input" x="0" y="-96" name="b2" />
+ <pin polarity="Input" x="0" y="-32" name="b3" />
+ <pin polarity="Output" x="384" y="-224" name="result" />
+ <graph>
+ <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b1" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b2" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b3" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </graph>
+</symbol>
diff --git a/Negate_1.vf b/Negate_1.vf
index 23a40c7..664d073 100755
--- a/Negate_1.vf
+++ b/Negate_1.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Negate_1.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:09
+// /___/ /\ Timestamp : 02/16/2012 18:40:35
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate_1.vf" -w "X:/My Documents/ec311/lab1/Negate_1.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Negate_1.vf" -w "X:/My Documents/ec311/ec311-lab1/Negate_1.sch"
//Design Name: Negate_1
//Device: spartan6
//Purpose:
diff --git a/Negate_2.cmd_log b/Negate_2.cmd_log
index c69baf9..eb4f0b5 100755
--- a/Negate_2.cmd_log
+++ b/Negate_2.cmd_log
@@ -1,2 +1,6 @@
sch2sym -intstyle ise -family spartan6 -refsym Negate_2 {X:/My Documents/ec311/lab1/Negate_2.sch} {X:/My Documents/ec311/lab1/Negate_2.sym}
sch2sym -intstyle ise -family spartan6 -w -refsym Negate_2 /home/michael/Documents/School/EC311/lab1/Negate_2.sch /home/michael/Documents/School/EC311/lab1/Negate_2.sym
+sch2sym -intstyle ise -family spartan6 -w -refsym Negate_2 {X:/My Documents/ec311/ec311-lab1/Negate_2.sch} {X:/My Documents/ec311/ec311-lab1/Negate_2.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Negate_2 {X:/My Documents/ec311/ec311-lab1/Negate_2.sch} {X:/My Documents/ec311/ec311-lab1/Negate_2.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Negate_2 {X:/My Documents/ec311/ec311-lab1/Negate_2.sch} {X:/My Documents/ec311/ec311-lab1/Negate_2.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Negate_2 {X:/My Documents/ec311/ec311-lab1/Negate_2.sch} {X:/My Documents/ec311/ec311-lab1/Negate_2.sym}
diff --git a/Negate_2.jhd b/Negate_2.jhd
index 237044d..ae25d66 100755
--- a/Negate_2.jhd
+++ b/Negate_2.jhd
@@ -1 +1 @@
-MODULE Negate_2
+MODULE Negate_2
diff --git a/Negate_2.sch b/Negate_2.sch
index 2aa228c..5d7d5a3 100755
--- a/Negate_2.sch
+++ b/Negate_2.sch
@@ -1,179 +1,192 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<drawing version="7">
- <attr value="spartan6" name="DeviceFamilyName">
- <trait delete="all:0" />
- <trait editname="all:0" />
- <trait edittrait="all:0" />
- </attr>
- <netlist>
- <signal name="result" />
- <signal name="b2" />
- <signal name="XLXN_35" />
- <signal name="XLXN_37" />
- <signal name="XLXN_40" />
- <signal name="XLXN_41" />
- <signal name="XLXN_43" />
- <signal name="XLXN_44" />
- <signal name="XLXN_45" />
- <signal name="XLXN_46" />
- <signal name="XLXN_48" />
- <signal name="XLXN_49" />
- <signal name="XLXN_50" />
- <signal name="b3" />
- <signal name="b0" />
- <signal name="b1" />
- <signal name="XLXN_58" />
- <signal name="XLXN_59" />
- <signal name="XLXN_60" />
- <signal name="XLXN_61" />
- <port polarity="Output" name="result" />
- <port polarity="Input" name="b2" />
- <port polarity="Input" name="b3" />
- <port polarity="Input" name="b0" />
- <port polarity="Input" name="b1" />
- <blockdef name="and2">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="64" y1="-64" y2="-64" x1="0" />
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- <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
- <line x2="64" y1="-48" y2="-48" x1="144" />
- <line x2="144" y1="-144" y2="-144" x1="64" />
- <line x2="64" y1="-48" y2="-144" x1="64" />
- </blockdef>
- <blockdef name="or4">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="48" y1="-64" y2="-64" x1="0" />
- <line x2="64" y1="-128" y2="-128" x1="0" />
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- <line x2="48" y1="-256" y2="-256" x1="0" />
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- <line x2="48" y1="-112" y2="-112" x1="112" />
- <line x2="48" y1="-256" y2="-208" x1="48" />
- <line x2="48" y1="-64" y2="-112" x1="48" />
- <arc ex="48" ey="-208" sx="48" sy="-112" r="56" cx="16" cy="-160" />
- <arc ex="192" ey="-160" sx="112" sy="-112" r="88" cx="116" cy="-200" />
- </blockdef>
- <blockdef name="nand3">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="64" y1="-64" y2="-64" x1="0" />
- <line x2="64" y1="-128" y2="-128" x1="0" />
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- <arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
- <line x2="64" y1="-64" y2="-192" x1="64" />
- </blockdef>
- <blockdef name="inv">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="64" y1="-32" y2="-32" x1="0" />
- <line x2="160" y1="-32" y2="-32" x1="224" />
- <line x2="128" y1="-64" y2="-32" x1="64" />
- <line x2="64" y1="-32" y2="0" x1="128" />
- <line x2="64" y1="0" y2="-64" x1="64" />
- <circle r="16" cx="144" cy="-32" />
- </blockdef>
- <block symbolname="or4" name="XLXI_8">
- <blockpin signalname="XLXN_37" name="I0" />
- <blockpin signalname="XLXN_41" name="I1" />
- <blockpin signalname="XLXN_40" name="I2" />
- <blockpin signalname="XLXN_35" name="I3" />
- <blockpin signalname="result" name="O" />
- </block>
- <block symbolname="and2" name="XLXI_9">
- <blockpin signalname="XLXN_44" name="I0" />
- <blockpin signalname="b3" name="I1" />
- <blockpin signalname="XLXN_35" name="O" />
- </block>
- <block symbolname="and2" name="XLXI_10">
- <blockpin signalname="b1" name="I0" />
- <blockpin signalname="XLXN_44" name="I1" />
- <blockpin signalname="XLXN_41" name="O" />
- </block>
- <block symbolname="and2" name="XLXI_11">
- <blockpin signalname="b0" name="I0" />
- <blockpin signalname="XLXN_44" name="I1" />
- <blockpin signalname="XLXN_40" name="O" />
- </block>
- <block symbolname="nand3" name="XLXI_12">
- <blockpin signalname="b1" name="I0" />
- <blockpin signalname="b0" name="I1" />
- <blockpin signalname="XLXN_44" name="I2" />
- <blockpin signalname="XLXN_37" name="O" />
- </block>
- <block symbolname="inv" name="XLXI_14">
- <blockpin signalname="b2" name="I" />
- <blockpin signalname="XLXN_44" name="O" />
- </block>
- </netlist>
- <sheet sheetnum="1" width="3520" height="2720">
- <branch name="result">
- <wire x2="2240" y1="960" y2="960" x1="2208" />
- </branch>
- <iomarker fontsize="28" x="2240" y="960" name="result" orien="R0" />
- <instance x="1952" y="1120" name="XLXI_8" orien="R0" />
- <instance x="1680" y="848" name="XLXI_9" orien="R0" />
- <branch name="XLXN_35">
- <wire x2="1952" y1="752" y2="752" x1="1936" />
- <wire x2="1952" y1="752" y2="864" x1="1952" />
- </branch>
- <branch name="XLXN_40">
- <wire x2="1952" y1="928" y2="928" x1="1920" />
- </branch>
- <instance x="1664" y="1024" name="XLXI_11" orien="R0" />
- <instance x="1376" y="816" name="XLXI_14" orien="R0" />
- <branch name="XLXN_44">
- <wire x2="1616" y1="784" y2="784" x1="1600" />
- <wire x2="1680" y1="784" y2="784" x1="1616" />
- <wire x2="1616" y1="784" y2="896" x1="1616" />
- <wire x2="1664" y1="896" y2="896" x1="1616" />
- <wire x2="1616" y1="896" y2="1056" x1="1616" />
- <wire x2="1648" y1="1056" y2="1056" x1="1616" />
- <wire x2="1616" y1="1056" y2="1056" x1="1600" />
- <wire x2="1600" y1="1056" y2="1248" x1="1600" />
- <wire x2="1632" y1="1248" y2="1248" x1="1600" />
- </branch>
- <branch name="XLXN_41">
- <wire x2="1904" y1="992" y2="1088" x1="1904" />
- <wire x2="1952" y1="992" y2="992" x1="1904" />
- </branch>
- <branch name="XLXN_37">
- <wire x2="1936" y1="1312" y2="1312" x1="1888" />
- <wire x2="1952" y1="1056" y2="1056" x1="1936" />
- <wire x2="1936" y1="1056" y2="1312" x1="1936" />
- </branch>
- <instance x="1648" y="1184" name="XLXI_10" orien="R0" />
- <instance x="1632" y="1440" name="XLXI_12" orien="R0" />
- <branch name="b3">
- <wire x2="1680" y1="720" y2="720" x1="1616" />
- </branch>
- <iomarker fontsize="28" x="1616" y="720" name="b3" orien="R180" />
- <iomarker fontsize="28" x="1312" y="784" name="b2" orien="R180" />
- <branch name="b2">
- <wire x2="1376" y1="784" y2="784" x1="1312" />
- </branch>
- <iomarker fontsize="28" x="1408" y="1056" name="b0" orien="R180" />
- <branch name="b1">
- <wire x2="1488" y1="1136" y2="1136" x1="1424" />
- <wire x2="1568" y1="1136" y2="1136" x1="1488" />
- <wire x2="1568" y1="1136" y2="1376" x1="1568" />
- <wire x2="1632" y1="1376" y2="1376" x1="1568" />
- <wire x2="1568" y1="1120" y2="1136" x1="1568" />
- <wire x2="1648" y1="1120" y2="1120" x1="1568" />
- </branch>
- <iomarker fontsize="28" x="1424" y="1136" name="b1" orien="R180" />
- <branch name="b0">
- <wire x2="1440" y1="1056" y2="1056" x1="1408" />
- <wire x2="1440" y1="960" y2="1056" x1="1440" />
- <wire x2="1536" y1="960" y2="960" x1="1440" />
- <wire x2="1664" y1="960" y2="960" x1="1536" />
- <wire x2="1536" y1="960" y2="1120" x1="1536" />
- <wire x2="1536" y1="1120" y2="1312" x1="1536" />
- <wire x2="1632" y1="1312" y2="1312" x1="1536" />
- </branch>
- </sheet>
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+ <attr value="spartan6" name="DeviceFamilyName">
+ <trait delete="all:0" />
+ <trait editname="all:0" />
+ <trait edittrait="all:0" />
+ </attr>
+ <netlist>
+ <signal name="result" />
+ <signal name="b2" />
+ <signal name="XLXN_35" />
+ <signal name="XLXN_37" />
+ <signal name="XLXN_40" />
+ <signal name="XLXN_41" />
+ <signal name="XLXN_44" />
+ <signal name="b3" />
+ <signal name="b0" />
+ <signal name="b1" />
+ <signal name="XLXN_47" />
+ <signal name="XLXN_48" />
+ <signal name="XLXN_49" />
+ <signal name="XLXN_50" />
+ <port polarity="Output" name="result" />
+ <port polarity="Input" name="b2" />
+ <port polarity="Input" name="b3" />
+ <port polarity="Input" name="b0" />
+ <port polarity="Input" name="b1" />
+ <blockdef name="and2">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-64" y2="-64" x1="0" />
+ <line x2="64" y1="-128" y2="-128" x1="0" />
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+ <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
+ <line x2="64" y1="-48" y2="-48" x1="144" />
+ <line x2="144" y1="-144" y2="-144" x1="64" />
+ <line x2="64" y1="-48" y2="-144" x1="64" />
+ </blockdef>
+ <blockdef name="or4">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="48" y1="-64" y2="-64" x1="0" />
+ <line x2="64" y1="-128" y2="-128" x1="0" />
+ <line x2="64" y1="-192" y2="-192" x1="0" />
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+ <arc ex="112" ey="-208" sx="192" sy="-160" r="88" cx="116" cy="-120" />
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+ <line x2="48" y1="-256" y2="-208" x1="48" />
+ <line x2="48" y1="-64" y2="-112" x1="48" />
+ <arc ex="48" ey="-208" sx="48" sy="-112" r="56" cx="16" cy="-160" />
+ <arc ex="192" ey="-160" sx="112" sy="-112" r="88" cx="116" cy="-200" />
+ </blockdef>
+ <blockdef name="inv">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-32" y2="-32" x1="0" />
+ <line x2="160" y1="-32" y2="-32" x1="224" />
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+ <line x2="64" y1="0" y2="-64" x1="64" />
+ <circle r="16" cx="144" cy="-32" />
+ </blockdef>
+ <blockdef name="and3">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-64" y2="-64" x1="0" />
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+ <arc ex="144" ey="-176" sx="144" sy="-80" r="48" cx="144" cy="-128" />
+ <line x2="64" y1="-64" y2="-192" x1="64" />
+ </blockdef>
+ <block symbolname="or4" name="XLXI_8">
+ <blockpin signalname="XLXN_37" name="I0" />
+ <blockpin signalname="XLXN_41" name="I1" />
+ <blockpin signalname="XLXN_40" name="I2" />
+ <blockpin signalname="XLXN_35" name="I3" />
+ <blockpin signalname="result" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_9">
+ <blockpin signalname="XLXN_44" name="I0" />
+ <blockpin signalname="b3" name="I1" />
+ <blockpin signalname="XLXN_35" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_10">
+ <blockpin signalname="b1" name="I0" />
+ <blockpin signalname="XLXN_44" name="I1" />
+ <blockpin signalname="XLXN_41" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_11">
+ <blockpin signalname="b0" name="I0" />
+ <blockpin signalname="XLXN_44" name="I1" />
+ <blockpin signalname="XLXN_40" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_14">
+ <blockpin signalname="b2" name="I" />
+ <blockpin signalname="XLXN_44" name="O" />
+ </block>
+ <block symbolname="and3" name="XLXI_15">
+ <blockpin signalname="XLXN_47" name="I0" />
+ <blockpin signalname="XLXN_49" name="I1" />
+ <blockpin signalname="b2" name="I2" />
+ <blockpin signalname="XLXN_37" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_16">
+ <blockpin signalname="b1" name="I" />
+ <blockpin signalname="XLXN_49" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_17">
+ <blockpin signalname="b0" name="I" />
+ <blockpin signalname="XLXN_47" name="O" />
+ </block>
+ </netlist>
+ <sheet sheetnum="1" width="3520" height="2720">
+ <branch name="result">
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+ </branch>
+ <iomarker fontsize="28" x="2240" y="960" name="result" orien="R0" />
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+ </branch>
+ <instance x="1664" y="1024" name="XLXI_11" orien="R0" />
+ <instance x="1376" y="816" name="XLXI_14" orien="R0" />
+ <branch name="XLXN_41">
+ <wire x2="1904" y1="992" y2="1088" x1="1904" />
+ <wire x2="1952" y1="992" y2="992" x1="1904" />
+ </branch>
+ <branch name="XLXN_37">
+ <wire x2="1936" y1="1312" y2="1312" x1="1888" />
+ <wire x2="1952" y1="1056" y2="1056" x1="1936" />
+ <wire x2="1936" y1="1056" y2="1312" x1="1936" />
+ </branch>
+ <instance x="1648" y="1184" name="XLXI_10" orien="R0" />
+ <branch name="b3">
+ <wire x2="1680" y1="720" y2="720" x1="1616" />
+ </branch>
+ <iomarker fontsize="28" x="1616" y="720" name="b3" orien="R180" />
+ <iomarker fontsize="28" x="1312" y="784" name="b2" orien="R180" />
+ <branch name="b2">
+ <wire x2="1360" y1="896" y2="896" x1="1280" />
+ <wire x2="1280" y1="896" y2="1248" x1="1280" />
+ <wire x2="1632" y1="1248" y2="1248" x1="1280" />
+ <wire x2="1360" y1="784" y2="784" x1="1312" />
+ <wire x2="1376" y1="784" y2="784" x1="1360" />
+ <wire x2="1360" y1="784" y2="896" x1="1360" />
+ </branch>
+ <iomarker fontsize="28" x="1408" y="1056" name="b0" orien="R180" />
+ <instance x="1632" y="1440" name="XLXI_15" orien="R0" />
+ <branch name="b0">
+ <wire x2="1312" y1="1008" y2="1376" x1="1312" />
+ <wire x2="1376" y1="1376" y2="1376" x1="1312" />
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+ <wire x2="1440" y1="1056" y2="1056" x1="1408" />
+ <wire x2="1440" y1="960" y2="1008" x1="1440" />
+ <wire x2="1664" y1="960" y2="960" x1="1440" />
+ </branch>
+ <branch name="XLXN_44">
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+ <wire x2="1616" y1="896" y2="1056" x1="1616" />
+ <wire x2="1648" y1="1056" y2="1056" x1="1616" />
+ </branch>
+ <branch name="b1">
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+ <wire x2="1648" y1="1120" y2="1120" x1="1568" />
+ <wire x2="1568" y1="1120" y2="1136" x1="1568" />
+ </branch>
+ <iomarker fontsize="28" x="1200" y="1136" name="b1" orien="R180" />
+ <branch name="XLXN_47">
+ <wire x2="1632" y1="1376" y2="1376" x1="1600" />
+ </branch>
+ <instance x="1376" y="1408" name="XLXI_17" orien="R0" />
+ <branch name="XLXN_49">
+ <wire x2="1632" y1="1312" y2="1312" x1="1600" />
+ </branch>
+ <instance x="1376" y="1344" name="XLXI_16" orien="R0" />
+ </sheet>
</drawing> \ No newline at end of file
diff --git a/Negate_2.sym b/Negate_2.sym
index 6763b85..92fd357 100755
--- a/Negate_2.sym
+++ b/Negate_2.sym
@@ -1,24 +1,24 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="Negate_2">
- <symboltype>BLOCK</symboltype>
- <timestamp>2012-2-16T0:43:56</timestamp>
- <pin polarity="Input" x="0" y="-96" name="b2" />
- <pin polarity="Input" x="0" y="-32" name="b3" />
- <pin polarity="Input" x="0" y="-224" name="b0" />
- <pin polarity="Input" x="0" y="-160" name="b1" />
- <pin polarity="Output" x="384" y="-224" name="result" />
- <graph>
- <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b2" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b3" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b0" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b1" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </graph>
-</symbol>
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="Negate_2">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-16T23:53:56</timestamp>
+ <pin polarity="Input" x="0" y="-96" name="b2" />
+ <pin polarity="Input" x="0" y="-32" name="b3" />
+ <pin polarity="Input" x="0" y="-224" name="b0" />
+ <pin polarity="Input" x="0" y="-160" name="b1" />
+ <pin polarity="Output" x="384" y="-224" name="result" />
+ <graph>
+ <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b2" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b3" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b1" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ <rect width="256" x="64" y="-256" height="320" />
+ </graph>
+</symbol>
diff --git a/Negate_2.vf b/Negate_2.vf
index 6ce41b2..b2302b8 100755
--- a/Negate_2.vf
+++ b/Negate_2.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Negate_2.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:09
+// /___/ /\ Timestamp : 02/16/2012 18:54:27
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate_2.vf" -w "X:/My Documents/ec311/lab1/Negate_2.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Negate_2.vf" -w "X:/My Documents/ec311/ec311-lab1/Negate_2.sch"
//Design Name: Negate_2
//Device: spartan6
//Purpose:
@@ -32,31 +32,36 @@ module Negate_2(b0,
input b3;
output result;
- wire XLXN_7;
- wire XLXN_9;
- wire XLXN_10;
- wire XLXN_12;
- wire XLXN_16;
- wire XLXN_17;
+ wire XLXN_35;
+ wire XLXN_37;
+ wire XLXN_40;
+ wire XLXN_41;
+ wire XLXN_44;
+ wire XLXN_47;
+ wire XLXN_49;
- AND2 XLXI_1 (.I0(XLXN_7),
- .I1(b3),
- .O(XLXN_9));
- AND3 XLXI_2 (.I0(b2),
- .I1(XLXN_16),
- .I2(XLXN_17),
- .O(XLXN_10));
- OR2 XLXI_3 (.I0(XLXN_10),
- .I1(XLXN_9),
+ OR4 XLXI_8 (.I0(XLXN_37),
+ .I1(XLXN_41),
+ .I2(XLXN_40),
+ .I3(XLXN_35),
.O(result));
- OR3 XLXI_4 (.I0(XLXN_12),
- .I1(b1),
- .I2(b0),
- .O(XLXN_7));
- INV XLXI_5 (.I(b2),
- .O(XLXN_12));
- INV XLXI_6 (.I(b1),
- .O(XLXN_16));
- INV XLXI_7 (.I(b0),
- .O(XLXN_17));
+ AND2 XLXI_9 (.I0(XLXN_44),
+ .I1(b3),
+ .O(XLXN_35));
+ AND2 XLXI_10 (.I0(b1),
+ .I1(XLXN_44),
+ .O(XLXN_41));
+ AND2 XLXI_11 (.I0(b0),
+ .I1(XLXN_44),
+ .O(XLXN_40));
+ INV XLXI_14 (.I(b2),
+ .O(XLXN_44));
+ AND3 XLXI_15 (.I0(XLXN_47),
+ .I1(XLXN_49),
+ .I2(b2),
+ .O(XLXN_37));
+ INV XLXI_16 (.I(b1),
+ .O(XLXN_49));
+ INV XLXI_17 (.I(b0),
+ .O(XLXN_47));
endmodule
diff --git a/Negate_3.cmd_log b/Negate_3.cmd_log
index 3df4b90..253b96d 100755
--- a/Negate_3.cmd_log
+++ b/Negate_3.cmd_log
@@ -1,2 +1,4 @@
sch2sym -intstyle ise -family spartan6 -refsym Negate_3 {X:/My Documents/ec311/lab1/Negate_3.sch} {X:/My Documents/ec311/lab1/Negate_3.sym}
sch2sym -intstyle ise -family spartan6 -w -refsym Negate_3 /home/michael/Documents/School/EC311/lab1/Negate_3.sch /home/michael/Documents/School/EC311/lab1/Negate_3.sym
+sch2sym -intstyle ise -family spartan6 -w -refsym Negate_3 {X:/My Documents/ec311/ec311-lab1/Negate_3.sch} {X:/My Documents/ec311/ec311-lab1/Negate_3.sym}
+sch2sym -intstyle ise -family spartan6 -w -refsym Negate_3 {X:/My Documents/ec311/ec311-lab1/Negate_3.sch} {X:/My Documents/ec311/ec311-lab1/Negate_3.sym}
diff --git a/Negate_3.jhd b/Negate_3.jhd
index a943761..8ba0414 100755
--- a/Negate_3.jhd
+++ b/Negate_3.jhd
@@ -1 +1 @@
-MODULE Negate_3
+MODULE Negate_3
diff --git a/Negate_3.sch b/Negate_3.sch
index 7568688..01b6d13 100755
--- a/Negate_3.sch
+++ b/Negate_3.sch
@@ -1,89 +1,105 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<drawing version="7">
- <attr value="spartan6" name="DeviceFamilyName">
- <trait delete="all:0" />
- <trait editname="all:0" />
- <trait edittrait="all:0" />
- </attr>
- <netlist>
- <signal name="XLXN_8" />
- <signal name="result" />
- <signal name="b3" />
- <signal name="b0" />
- <signal name="b1" />
- <signal name="b2" />
- <port polarity="Output" name="result" />
- <port polarity="Input" name="b3" />
- <port polarity="Input" name="b0" />
- <port polarity="Input" name="b1" />
- <port polarity="Input" name="b2" />
- <blockdef name="nand2">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="64" y1="-64" y2="-64" x1="0" />
- <line x2="64" y1="-128" y2="-128" x1="0" />
- <line x2="216" y1="-96" y2="-96" x1="256" />
- <circle r="12" cx="204" cy="-96" />
- <line x2="64" y1="-48" y2="-144" x1="64" />
- <line x2="144" y1="-144" y2="-144" x1="64" />
- <line x2="64" y1="-48" y2="-48" x1="144" />
- <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
- </blockdef>
- <blockdef name="nor3">
- <timestamp>2000-1-1T10:10:10</timestamp>
- <line x2="48" y1="-64" y2="-64" x1="0" />
- <line x2="72" y1="-128" y2="-128" x1="0" />
- <line x2="48" y1="-192" y2="-192" x1="0" />
- <line x2="216" y1="-128" y2="-128" x1="256" />
- <circle r="12" cx="204" cy="-128" />
- <line x2="48" y1="-64" y2="-80" x1="48" />
- <line x2="48" y1="-192" y2="-176" x1="48" />
- <line x2="48" y1="-80" y2="-80" x1="112" />
- <line x2="48" y1="-176" y2="-176" x1="112" />
- <arc ex="48" ey="-176" sx="48" sy="-80" r="56" cx="16" cy="-128" />
- <arc ex="192" ey="-128" sx="112" sy="-80" r="88" cx="116" cy="-168" />
- <arc ex="112" ey="-176" sx="192" sy="-128" r="88" cx="116" cy="-88" />
- </blockdef>
- <block symbolname="nand2" name="XLXI_9">
- <blockpin signalname="XLXN_8" name="I0" />
- <blockpin signalname="b3" name="I1" />
- <blockpin signalname="result" name="O" />
- </block>
- <block symbolname="nor3" name="XLXI_13">
- <blockpin signalname="b2" name="I0" />
- <blockpin signalname="b1" name="I1" />
- <blockpin signalname="b0" name="I2" />
- <blockpin signalname="XLXN_8" name="O" />
- </block>
- </netlist>
- <sheet sheetnum="1" width="3520" height="2720">
- <branch name="result">
- <wire x2="2240" y1="848" y2="848" x1="2224" />
- </branch>
- <iomarker fontsize="28" x="2240" y="848" name="result" orien="R0" />
- <iomarker fontsize="28" x="1680" y="816" name="b3" orien="R180" />
- <instance x="1968" y="944" name="XLXI_9" orien="R0" />
- <branch name="b3">
- <wire x2="1968" y1="816" y2="816" x1="1680" />
- </branch>
- <branch name="XLXN_8">
- <wire x2="1968" y1="880" y2="880" x1="1904" />
- <wire x2="1904" y1="880" y2="896" x1="1904" />
- <wire x2="1952" y1="896" y2="896" x1="1904" />
- <wire x2="1952" y1="896" y2="976" x1="1952" />
- <wire x2="1952" y1="976" y2="976" x1="1920" />
- </branch>
- <instance x="1664" y="1104" name="XLXI_13" orien="R0" />
- <branch name="b0">
- <wire x2="1664" y1="912" y2="912" x1="1632" />
- </branch>
- <branch name="b1">
- <wire x2="1664" y1="976" y2="976" x1="1632" />
- </branch>
- <branch name="b2">
- <wire x2="1664" y1="1040" y2="1040" x1="1632" />
- </branch>
- <iomarker fontsize="28" x="1632" y="912" name="b0" orien="R180" />
- <iomarker fontsize="28" x="1632" y="976" name="b1" orien="R180" />
- <iomarker fontsize="28" x="1632" y="1040" name="b2" orien="R180" />
- </sheet>
+<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+ <attr value="spartan6" name="DeviceFamilyName">
+ <trait delete="all:0" />
+ <trait editname="all:0" />
+ <trait edittrait="all:0" />
+ </attr>
+ <netlist>
+ <signal name="XLXN_8" />
+ <signal name="result" />
+ <signal name="b3" />
+ <signal name="b0" />
+ <signal name="b1" />
+ <signal name="b2" />
+ <signal name="XLXN_10" />
+ <port polarity="Output" name="result" />
+ <port polarity="Input" name="b3" />
+ <port polarity="Input" name="b0" />
+ <port polarity="Input" name="b1" />
+ <port polarity="Input" name="b2" />
+ <blockdef name="or3">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="48" y1="-64" y2="-64" x1="0" />
+ <line x2="72" y1="-128" y2="-128" x1="0" />
+ <line x2="48" y1="-192" y2="-192" x1="0" />
+ <line x2="192" y1="-128" y2="-128" x1="256" />
+ <arc ex="192" ey="-128" sx="112" sy="-80" r="88" cx="116" cy="-168" />
+ <arc ex="48" ey="-176" sx="48" sy="-80" r="56" cx="16" cy="-128" />
+ <line x2="48" y1="-64" y2="-80" x1="48" />
+ <line x2="48" y1="-192" y2="-176" x1="48" />
+ <line x2="48" y1="-80" y2="-80" x1="112" />
+ <arc ex="112" ey="-176" sx="192" sy="-128" r="88" cx="116" cy="-88" />
+ <line x2="48" y1="-176" y2="-176" x1="112" />
+ </blockdef>
+ <blockdef name="inv">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-32" y2="-32" x1="0" />
+ <line x2="160" y1="-32" y2="-32" x1="224" />
+ <line x2="128" y1="-64" y2="-32" x1="64" />
+ <line x2="64" y1="-32" y2="0" x1="128" />
+ <line x2="64" y1="0" y2="-64" x1="64" />
+ <circle r="16" cx="144" cy="-32" />
+ </blockdef>
+ <blockdef name="and2">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-64" y2="-64" x1="0" />
+ <line x2="64" y1="-128" y2="-128" x1="0" />
+ <line x2="192" y1="-96" y2="-96" x1="256" />
+ <arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
+ <line x2="64" y1="-48" y2="-48" x1="144" />
+ <line x2="144" y1="-144" y2="-144" x1="64" />
+ <line x2="64" y1="-48" y2="-144" x1="64" />
+ </blockdef>
+ <block symbolname="or3" name="XLXI_14">
+ <blockpin signalname="b2" name="I0" />
+ <blockpin signalname="b1" name="I1" />
+ <blockpin signalname="b0" name="I2" />
+ <blockpin signalname="XLXN_8" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_15">
+ <blockpin signalname="b3" name="I" />
+ <blockpin signalname="XLXN_10" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_16">
+ <blockpin signalname="XLXN_8" name="I0" />
+ <blockpin signalname="XLXN_10" name="I1" />
+ <blockpin signalname="result" name="O" />
+ </block>
+ </netlist>
+ <sheet sheetnum="1" width="3520" height="2720">
+ <iomarker fontsize="28" x="1680" y="816" name="b3" orien="R180" />
+ <branch name="b3">
+ <wire x2="1808" y1="816" y2="816" x1="1680" />
+ </branch>
+ <branch name="XLXN_8">
+ <wire x2="1904" y1="880" y2="896" x1="1904" />
+ <wire x2="1952" y1="896" y2="896" x1="1904" />
+ <wire x2="1952" y1="896" y2="976" x1="1952" />
+ <wire x2="2064" y1="880" y2="880" x1="1904" />
+ <wire x2="1952" y1="976" y2="976" x1="1920" />
+ </branch>
+ <branch name="b0">
+ <wire x2="1664" y1="912" y2="912" x1="1632" />
+ </branch>
+ <branch name="b1">
+ <wire x2="1664" y1="976" y2="976" x1="1632" />
+ </branch>
+ <branch name="b2">
+ <wire x2="1664" y1="1040" y2="1040" x1="1632" />
+ </branch>
+ <iomarker fontsize="28" x="1632" y="912" name="b0" orien="R180" />
+ <iomarker fontsize="28" x="1632" y="976" name="b1" orien="R180" />
+ <iomarker fontsize="28" x="1632" y="1040" name="b2" orien="R180" />
+ <instance x="1664" y="1104" name="XLXI_14" orien="R0" />
+ <instance x="1808" y="848" name="XLXI_15" orien="R0" />
+ <branch name="result">
+ <wire x2="2400" y1="848" y2="848" x1="2320" />
+ </branch>
+ <branch name="XLXN_10">
+ <wire x2="2064" y1="816" y2="816" x1="2032" />
+ </branch>
+ <instance x="2064" y="944" name="XLXI_16" orien="R0" />
+ <iomarker fontsize="28" x="2400" y="848" name="result" orien="R0" />
+ </sheet>
</drawing> \ No newline at end of file
diff --git a/Negate_3.sym b/Negate_3.sym
index 3a12c24..f222519 100755
--- a/Negate_3.sym
+++ b/Negate_3.sym
@@ -1,24 +1,24 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<symbol version="7" name="Negate_3">
- <symboltype>BLOCK</symboltype>
- <timestamp>2012-2-16T0:43:52</timestamp>
- <pin polarity="Input" x="0" y="-224" name="b3" />
- <pin polarity="Input" x="0" y="-160" name="b0" />
- <pin polarity="Input" x="0" y="-96" name="b1" />
- <pin polarity="Input" x="0" y="-32" name="b2" />
- <pin polarity="Output" x="384" y="-224" name="result" />
- <graph>
- <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b3" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b0" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b1" />
- <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b2" />
- <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
- <rect width="256" x="64" y="-256" height="256" />
- <line x2="0" y1="-224" y2="-224" x1="64" />
- <line x2="0" y1="-160" y2="-160" x1="64" />
- <line x2="0" y1="-96" y2="-96" x1="64" />
- <line x2="0" y1="-32" y2="-32" x1="64" />
- <line x2="384" y1="-224" y2="-224" x1="320" />
- </graph>
-</symbol>
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="Negate_3">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-16T23:39:56</timestamp>
+ <pin polarity="Input" x="0" y="-224" name="b3" />
+ <pin polarity="Input" x="0" y="-160" name="b0" />
+ <pin polarity="Input" x="0" y="-96" name="b1" />
+ <pin polarity="Input" x="0" y="-32" name="b2" />
+ <pin polarity="Output" x="384" y="-224" name="result" />
+ <graph>
+ <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin b3" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin b0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin b1" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin b2" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin result" />
+ <rect width="256" x="64" y="-256" height="256" />
+ <line x2="0" y1="-224" y2="-224" x1="64" />
+ <line x2="0" y1="-160" y2="-160" x1="64" />
+ <line x2="0" y1="-96" y2="-96" x1="64" />
+ <line x2="0" y1="-32" y2="-32" x1="64" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ </graph>
+</symbol>
diff --git a/Negate_3.vf b/Negate_3.vf
index 7205c3a..4b821ca 100755
--- a/Negate_3.vf
+++ b/Negate_3.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Negate_3.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:08
+// /___/ /\ Timestamp : 02/16/2012 19:22:52
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate_3.vf" -w "X:/My Documents/ec311/lab1/Negate_3.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Negate_3.vf" -w "X:/My Documents/ec311/ec311-lab1/Negate_3.sch"
//Design Name: Negate_3
//Device: spartan6
//Purpose:
@@ -33,15 +33,15 @@ module Negate_3(b0,
output result;
wire XLXN_8;
- wire XLXN_9;
+ wire XLXN_10;
- OR3 XLXI_5 (.I0(b2),
- .I1(b1),
- .I2(b0),
- .O(XLXN_9));
- NAND2 XLXI_9 (.I0(XLXN_8),
- .I1(b3),
- .O(result));
- INV XLXI_12 (.I(XLXN_9),
+ OR3 XLXI_14 (.I0(b2),
+ .I1(b1),
+ .I2(b0),
.O(XLXN_8));
+ INV XLXI_15 (.I(b3),
+ .O(XLXN_10));
+ AND2 XLXI_16 (.I0(XLXN_8),
+ .I1(XLXN_10),
+ .O(result));
endmodule
diff --git a/_ngo/netlist.lst b/_ngo/netlist.lst
index c77d9e2..8d387ea 100755
--- a/_ngo/netlist.lst
+++ b/_ngo/netlist.lst
@@ -1,2 +1,2 @@
-X:\My Documents\ec311\lab1\ALU.ngc 1329336939
+X:\My Documents\ec311\ec311-lab1\ALU.ngc 1329439965
OK
diff --git a/_xmsgs/bitgen.xmsgs b/_xmsgs/bitgen.xmsgs
index 78d5ffb..6581d17 100755
--- a/_xmsgs/bitgen.xmsgs
+++ b/_xmsgs/bitgen.xmsgs
@@ -5,7 +5,7 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
-<msg type="info" file="Bitgen" num="278" delta="new" >Setting the Persist option to &quot;Yes&quot; with the CONFIG_MODE constraint value &quot;<arg fmt="%s" index="1">UnSpecified</arg>&quot; will result in the 8-bit SelectMap port being persisted.
+<msg type="info" file="Bitgen" num="278" delta="old" >Setting the Persist option to &quot;Yes&quot; with the CONFIG_MODE constraint value &quot;<arg fmt="%s" index="1">UnSpecified</arg>&quot; will result in the 8-bit SelectMap port being persisted.
</msg>
</messages>
diff --git a/_xmsgs/map.xmsgs b/_xmsgs/map.xmsgs
index b32095a..4ecf2a7 100755
--- a/_xmsgs/map.xmsgs
+++ b/_xmsgs/map.xmsgs
@@ -5,22 +5,22 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
-<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.
+<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg>
-<msg type="info" file="LIT" num="244" delta="new" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
+<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>
-<msg type="info" file="Pack" num="1716" delta="new" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
+<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg>
-<msg type="info" file="Pack" num="1720" delta="new" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
+<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg>
-<msg type="info" file="Map" num="215" delta="new" >The Interim Design Summary has been generated in the MAP Report (.mrp).
+<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
-<msg type="info" file="Pack" num="1650" delta="new" >Map created a placed design.
+<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
</msg>
</messages>
diff --git a/_xmsgs/par.xmsgs b/_xmsgs/par.xmsgs
index 848b12c..5f1f5f1 100755
--- a/_xmsgs/par.xmsgs
+++ b/_xmsgs/par.xmsgs
@@ -5,10 +5,10 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
-<msg type="info" file="Par" num="282" delta="new" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
+<msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
</msg>
-<msg type="info" file="Par" num="459" delta="new" >The Clock Report is not displayed in the non timing-driven mode.
+<msg type="info" file="Par" num="459" delta="old" >The Clock Report is not displayed in the non timing-driven mode.
</msg>
</messages>
diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs
index 2211003..ee464b0 100755
--- a/_xmsgs/pn_parser.xmsgs
+++ b/_xmsgs/pn_parser.xmsgs
@@ -1,12 +1,12 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- IMPORTANT: This is an internal file that has been generated -->
-<!-- by the Xilinx ISE software. Any direct editing or -->
-<!-- changes made to this file may result in unpredictable -->
-<!-- behavior or data corruption. It is strongly advised that -->
-<!-- users do not edit the contents of this file. -->
-<!-- -->
-<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
-
-<messages>
-</messages>
-
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated -->
+<!-- by the Xilinx ISE software. Any direct editing or -->
+<!-- changes made to this file may result in unpredictable -->
+<!-- behavior or data corruption. It is strongly advised that -->
+<!-- users do not edit the contents of this file. -->
+<!-- -->
+<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+
+<messages>
+</messages>
+
diff --git a/_xmsgs/trce.xmsgs b/_xmsgs/trce.xmsgs
index 120dfa1..80cb2e4 100755
--- a/_xmsgs/trce.xmsgs
+++ b/_xmsgs/trce.xmsgs
@@ -5,11 +5,11 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
-<msg type="info" file="Timing" num="2698" delta="new" >No timing constraints found, doing default enumeration.</msg>
+<msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg>
-<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
+<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
-<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
+<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
</messages>
diff --git a/alu.bgn b/alu.bgn
index f3ad255..6d6d984 100755
--- a/alu.bgn
+++ b/alu.bgn
@@ -5,7 +5,7 @@ C:\Xilinx\13.3\ISE_DS\ISE\.
"ALU" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3
Opened constraints file ALU.pcf.
-Wed Feb 15 15:16:39 2012
+Thu Feb 16 19:53:39 2012
C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:JtagClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g Persist:Yes -m -g ReadBack -g DonePipe:No -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 ALU.ncd
diff --git a/alu.bit b/alu.bit
index a9ad5c0..4b4dd13 100755
--- a/alu.bit
+++ b/alu.bit
Binary files differ
diff --git a/alu.drc b/alu.drc
index 39644f9..f6dcace 100755
--- a/alu.drc
+++ b/alu.drc
@@ -1,7 +1,7 @@
Release 13.3 Drc O.76xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
-Wed Feb 15 15:16:39 2012
+Thu Feb 16 19:53:39 2012
drc -z ALU.ncd ALU.pcf
diff --git a/alu.msd b/alu.msd
index b05823c..48c0ca2 100755
--- a/alu.msd
+++ b/alu.msd
@@ -4,7 +4,7 @@ Design name: ALU.ncd;UserID=0xFFFFFFFF
Architecture: spartan6
Part: 6slx16csg324
Type: mask
-Date: Wed Feb 15 15:16:40 2012
+Date: Thu Feb 16 19:53:41 2012
Bits: 3711248
1111111111111111
1111111111111111
diff --git a/alu.msk b/alu.msk
index 4f0c2a8..000ece4 100755
--- a/alu.msk
+++ b/alu.msk
Binary files differ
diff --git a/alu.rbb b/alu.rbb
index 7cf8d8e..e027349 100755
--- a/alu.rbb
+++ b/alu.rbb
Binary files differ
diff --git a/alu.rbd b/alu.rbd
index f52b655..342558b 100755
--- a/alu.rbd
+++ b/alu.rbd
@@ -4,7 +4,7 @@ Design name: ALU.ncd;UserID=0xFFFFFFFF
Architecture: spartan6
Part: 6slx16csg324
Type: readback
-Date: Wed Feb 15 15:16:40 2012
+Date: Thu Feb 16 19:53:41 2012
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diff --git a/impact_impact.xwbt b/impact_impact.xwbt
index 597ede0..533b0c2 100755
--- a/impact_impact.xwbt
+++ b/impact_impact.xwbt
@@ -1,8 +1,8 @@
INTSTYLE=impact
-INFILE=X:\My Documents\ec311\lab1\impact.xsl
-OUTFILE=X:\My Documents\ec311\lab1\impact.xsl
+INFILE=X:\My Documents\ec311\ec311-lab1\impact.xsl
+OUTFILE=X:\My Documents\ec311\ec311-lab1\impact.xsl
FAMILY=Single
PART=Single
-WORKINGDIR=X:\My Documents\ec311\lab1
+WORKINGDIR=X:\My Documents\ec311\ec311-lab1
LICENSE=iMPACT
USER_INFO=iMPACT
diff --git a/iseconfig/ALU.xreport b/iseconfig/ALU.xreport
index dbe97f4..20fba66 100755
--- a/iseconfig/ALU.xreport
+++ b/iseconfig/ALU.xreport
@@ -1,11 +1,11 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
- <DateModified>2012-02-15T19:01:09</DateModified>
+ <DateModified>2012-02-16T18:37:40</DateModified>
<ModuleName>ALU</ModuleName>
- <SummaryTimeStamp>Unknown</SummaryTimeStamp>
- <SavedFilePath>/home/michael/Documents/School/EC311/lab1/iseconfig/ALU.xreport</SavedFilePath>
- <ImplementationReportsDirectory>/home/michael/Documents/School/EC311/lab1/</ImplementationReportsDirectory>
+ <SummaryTimeStamp>2012-02-16T18:30:33</SummaryTimeStamp>
+ <SavedFilePath>X:/My Documents/ec311/ec311-lab1/iseconfig/ALU.xreport</SavedFilePath>
+ <ImplementationReportsDirectory>X:/My Documents/ec311/ec311-lab1\</ImplementationReportsDirectory>
<DateInitialized>2012-02-15T14:52:54</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
diff --git a/iseconfig/lab1.projectmgr b/iseconfig/lab1.projectmgr
index 6dc197a..2b2f3c6 100755
--- a/iseconfig/lab1.projectmgr
+++ b/iseconfig/lab1.projectmgr
@@ -1,79 +1,77 @@
-<?xml version='1.0' encoding='utf-8'?>
-<!--This is an ISE project configuration file.-->
-<!--It holds project specific layout data for the projectmgr plugin.-->
-<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
-<Project version="2" owner="projectmgr" name="lab1" >
- <!--This is an ISE project configuration file.-->
- <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
- <ClosedNodes>
- <ClosedNodesVersion>2</ClosedNodesVersion>
- <ClosedNode>/ALU X:|My Documents|ec311|lab1|ALU.sch/XLXI_1 - Divide</ClosedNode>
- <ClosedNode>/ALU X:|My Documents|ec311|lab1|ALU.sch/XLXI_2 - Modulo</ClosedNode>
- <ClosedNode>/ALU X:|My Documents|ec311|lab1|ALU.sch/XLXI_3 - Negate</ClosedNode>
- </ClosedNodes>
- <SelectedItems>
- <SelectedItem>ALU (/home/michael/Documents/School/EC311/lab1/ALU.sch)</SelectedItem>
- </SelectedItems>
- <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
- <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
- <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000150000000020000000000000000000000000200000064ffffffff000000810000000300000002000001500000000100000003000000000000000100000003</ViewHeaderState>
- <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
- <CurrentItem>ALU (/home/michael/Documents/School/EC311/lab1/ALU.sch)</CurrentItem>
- </ItemView>
- <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
- <ClosedNodes>
- <ClosedNodesVersion>1</ClosedNodesVersion>
- </ClosedNodes>
- <SelectedItems>
- <SelectedItem>Update All Schematic Files</SelectedItem>
- </SelectedItems>
- <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
- <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
- <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState>
- <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
- <CurrentItem>Update All Schematic Files</CurrentItem>
- </ItemView>
- <ItemView guiview="File" >
- <ClosedNodes>
- <ClosedNodesVersion>1</ClosedNodesVersion>
- </ClosedNodes>
- <SelectedItems>
- <SelectedItem>Modulo_1.sch</SelectedItem>
- </SelectedItems>
- <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
- <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
- <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000287000000040101000100000000000000000000000064ffffffff0000008100000000000000040000008300000001000000000000002400000001000000000000006600000001000000000000017a0000000100000000</ViewHeaderState>
- <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
- <CurrentItem>Modulo_1.sch</CurrentItem>
- </ItemView>
- <ItemView guiview="Library" >
- <ClosedNodes>
- <ClosedNodesVersion>1</ClosedNodesVersion>
- <ClosedNode>work</ClosedNode>
- </ClosedNodes>
- <SelectedItems/>
- <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
- <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
- <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000117000000010001000100000000000000000000000064ffffffff000000810000000000000001000001170000000100000000</ViewHeaderState>
- <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
- <CurrentItem>work</CurrentItem>
- </ItemView>
- <ItemView engineview="SynthesisOnly" sourcetype="DESUT_SCHEMATIC" guiview="Process" >
- <ClosedNodes>
- <ClosedNodesVersion>1</ClosedNodesVersion>
- <ClosedNode>Implement Design/Map</ClosedNode>
- <ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
- <ClosedNode>Implement Design/Translate</ClosedNode>
- </ClosedNodes>
- <SelectedItems>
- <SelectedItem></SelectedItem>
- </SelectedItems>
- <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
- <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
- <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000173000000010000000100000000000000000000000064ffffffff000000810000000000000001000001730000000100000000</ViewHeaderState>
- <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
- <CurrentItem></CurrentItem>
- </ItemView>
- <SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
- <CurrentView>Implementation</CurrentView>
-</Project>
+<?xml version='1.0' encoding='utf-8'?>
+<!--This is an ISE project configuration file.-->
+<!--It holds project specific layout data for the projectmgr plugin.-->
+<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
+<Project version="2" owner="projectmgr" name="lab1" >
+ <!--This is an ISE project configuration file.-->
+ <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
+ <ClosedNodes>
+ <ClosedNodesVersion>2</ClosedNodesVersion>
+ <ClosedNode>/ALU X:|My Documents|ec311|lab1|ALU.sch/XLXI_1 - Divide</ClosedNode>
+ <ClosedNode>/ALU X:|My Documents|ec311|lab1|ALU.sch/XLXI_2 - Modulo</ClosedNode>
+ <ClosedNode>/ALU X:|My Documents|ec311|lab1|ALU.sch/XLXI_3 - Negate</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems>
+ <SelectedItem>ALU (X:/My Documents/ec311/ec311-lab1/ALU.sch)</SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000012b000000020000000000000000000000000200000064ffffffff0000008100000003000000020000012b0000000100000003000000000000000100000003</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
+ <CurrentItem>ALU (X:/My Documents/ec311/ec311-lab1/ALU.sch)</CurrentItem>
+ </ItemView>
+ <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ </ClosedNodes>
+ <SelectedItems>
+ <SelectedItem>Update All Schematic Files</SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000140000000010000000100000000000000000000000064ffffffff000000810000000000000001000001400000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>Update All Schematic Files</CurrentItem>
+ </ItemView>
+ <ItemView guiview="File" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ </ClosedNodes>
+ <SelectedItems/>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000171000000040101000100000000000000000000000064ffffffff000000810000000000000004000000830000000100000000000000240000000100000000000000660000000100000000000000640000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>Modulo_0.sch</CurrentItem>
+ </ItemView>
+ <ItemView guiview="Library" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ <ClosedNode>work</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems/>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000140000000010001000100000000000000000000000064ffffffff000000810000000000000001000001400000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>work</CurrentItem>
+ </ItemView>
+ <ItemView engineview="SynthesisOnly" sourcetype="DESUT_SCHEMATIC" guiview="Process" >
+ <ClosedNodes>
+ <ClosedNodesVersion>1</ClosedNodesVersion>
+ <ClosedNode>Implement Design/Map</ClosedNode>
+ <ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
+ <ClosedNode>Implement Design/Translate</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems>
+ <SelectedItem>Generate Programming File</SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >9</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000012f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000012f0000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>Generate Programming File</CurrentItem>
+ </ItemView>
+ <SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
+ <CurrentView>Implementation</CurrentView>
+</Project>
diff --git a/lab1.gise b/lab1.gise
index 054a65f..68616f9 100755
--- a/lab1.gise
+++ b/lab1.gise
@@ -36,6 +36,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ALU.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="ALU.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="ALU.stx"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="ALU.sym" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="ALU.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="ALU.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="ALU.twx" xil_pn:subbranch="Par"/>
@@ -44,6 +45,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="ALU.vf"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="ALU.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="ALU.xst"/>
+ <file xil_pn:fileType="FILE_HTML" xil_pn:name="ALU_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="ALU_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="ALU_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="ALU_map.mrp" xil_pn:subbranch="Map"/>
@@ -98,6 +100,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="alu.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_MSK" xil_pn:name="alu.msk"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="sev_seg_disp.vf"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
@@ -115,11 +118,9 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1329336928" xil_pn:in_ck="-1529285955265280609" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1120318093780454153" xil_pn:start_ts="1329336925">
+ <transform xil_pn:end_ts="1329439954" xil_pn:in_ck="-1529285955265280609" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1120318093780454153" xil_pn:start_ts="1329439949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
- <status xil_pn:value="OutOfDateForInputs"/>
- <status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="ALU.vf"/>
<outfile xil_pn:name="Divide.vf"/>
<outfile xil_pn:name="Divide_0.vf"/>
@@ -152,18 +153,15 @@
<transform xil_pn:end_ts="1329336928" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="1106364426758808884" xil_pn:start_ts="1329336928">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
- <status xil_pn:value="OutOfDateForPredecessor"/>
</transform>
<transform xil_pn:end_ts="1329336928" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4186483203912133424" xil_pn:start_ts="1329336928">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
- <status xil_pn:value="OutOfDateForPredecessor"/>
</transform>
- <transform xil_pn:end_ts="1329336941" xil_pn:in_ck="-5492412754742126177" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-819365665305975787" xil_pn:start_ts="1329336928">
+ <transform xil_pn:end_ts="1329439966" xil_pn:in_ck="-5492412754742126177" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-819365665305975787" xil_pn:start_ts="1329439954">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
- <status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="ALU.jhd"/>
@@ -179,25 +177,22 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
- <transform xil_pn:end_ts="1329336941" xil_pn:in_ck="87022295022" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="3734212952555236" xil_pn:start_ts="1329336941">
+ <transform xil_pn:end_ts="1329434300" xil_pn:in_ck="87022295022" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="3734212952555236" xil_pn:start_ts="1329434300">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
- <status xil_pn:value="OutOfDateForPredecessor"/>
</transform>
- <transform xil_pn:end_ts="1329336948" xil_pn:in_ck="958840011568711062" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1233222934028612217" xil_pn:start_ts="1329336941">
+ <transform xil_pn:end_ts="1329439973" xil_pn:in_ck="958840011568711062" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1233222934028612217" xil_pn:start_ts="1329439966">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
- <status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="ALU.bld"/>
<outfile xil_pn:name="ALU.ngd"/>
<outfile xil_pn:name="ALU_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
- <transform xil_pn:end_ts="1329336962" xil_pn:in_ck="958840054187154039" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1463976855095865663" xil_pn:start_ts="1329336948">
+ <transform xil_pn:end_ts="1329439986" xil_pn:in_ck="958840054187154039" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1463976855095865663" xil_pn:start_ts="1329439973">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
- <status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="ALU.pcf"/>
@@ -210,10 +205,9 @@
<outfile xil_pn:name="ALU_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
- <transform xil_pn:end_ts="1329336993" xil_pn:in_ck="5688090717086154096" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1178055513630676559" xil_pn:start_ts="1329336962">
+ <transform xil_pn:end_ts="1329440014" xil_pn:in_ck="5688090717086154096" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1178055513630676559" xil_pn:start_ts="1329439986">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
- <status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="ALU.ncd"/>
<outfile xil_pn:name="ALU.pad"/>
<outfile xil_pn:name="ALU.par"/>
@@ -225,12 +219,9 @@
<outfile xil_pn:name="ALU_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
- <transform xil_pn:end_ts="1329337024" xil_pn:in_ck="87022287397" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="8036697451854927384" xil_pn:start_ts="1329336993">
+ <transform xil_pn:end_ts="1329440044" xil_pn:in_ck="87022287397" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="8036697451854927384" xil_pn:start_ts="1329440014">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
- <status xil_pn:value="OutOfDateForPredecessor"/>
- <status xil_pn:value="OutOfDateForOutputs"/>
- <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="ALU.ut"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="alu.bgn"/>
@@ -241,15 +232,21 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
- <transform xil_pn:end_ts="1329337061" xil_pn:in_ck="129639531599" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="2682241697568822907" xil_pn:start_ts="1329337061">
+ <transform xil_pn:end_ts="1329434416" xil_pn:in_ck="129639531599" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="2682241697568822907" xil_pn:start_ts="1329434416">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
- <status xil_pn:value="OutOfDateForPredecessor"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="InputChanged"/>
+ </transform>
+ <transform xil_pn:end_ts="1329434415" xil_pn:in_ck="129639531599" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1329434413">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="InputChanged"/>
</transform>
- <transform xil_pn:end_ts="1329336993" xil_pn:in_ck="958834428552681075" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1329336985">
+ <transform xil_pn:end_ts="1329440014" xil_pn:in_ck="958834428552681075" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1329440006">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
- <status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="ALU.twr"/>
<outfile xil_pn:name="ALU.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
diff --git a/lab1.xise b/lab1.xise
index 5bf0c30..9526429 100755
--- a/lab1.xise
+++ b/lab1.xise
@@ -12,7 +12,7 @@
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
- <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
+ <version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="ALU.sch" xil_pn:type="FILE_SCHEMATIC">
@@ -109,7 +109,7 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -226,7 +226,6 @@
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
diff --git a/pa.fromHdl.tcl b/pa.fromHdl.tcl
index 68516e9..42b9671 100755
--- a/pa.fromHdl.tcl
+++ b/pa.fromHdl.tcl
@@ -1,7 +1,7 @@
# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator
-create_project -name lab1 -dir "X:/My Documents/ec311/lab1/planAhead_run_1" -part xc6slx16csg324-3
+create_project -name lab1 -dir "X:/My Documents/ec311/ec311-lab1/planAhead_run_1" -part xc6slx16csg324-3
set_param project.pinAheadLayout yes
set srcset [get_property srcset [current_run -impl]]
set_property top ALU $srcset
diff --git a/pa.fromNetlist.tcl b/pa.fromNetlist.tcl
index d74db7f..0391841 100755
--- a/pa.fromNetlist.tcl
+++ b/pa.fromNetlist.tcl
@@ -1,10 +1,10 @@
# PlanAhead Launch Script for Post-Synthesis pin planning, created by Project Navigator
-create_project -name lab1 -dir "X:/My Documents/ec311/lab1/planAhead_run_1" -part xc6slx16csg324-3
+create_project -name lab1 -dir "X:/My Documents/ec311/ec311-lab1/planAhead_run_2" -part xc6slx16csg324-3
set_property design_mode GateLvl [get_property srcset [current_run -impl]]
-set_property edif_top_file "X:/My Documents/ec311/lab1/ALU.ngc" [ get_property srcset [ current_run ] ]
-add_files -norecurse { {X:/My Documents/ec311/lab1} }
+set_property edif_top_file "X:/My Documents/ec311/ec311-lab1/ALU.ngc" [ get_property srcset [ current_run ] ]
+add_files -norecurse { {X:/My Documents/ec311/ec311-lab1} }
set_param project.pinAheadLayout yes
set_property target_constrs_file "ALU.ucf" [current_fileset -constrset]
add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]]
diff --git a/par_usage_statistics.html b/par_usage_statistics.html
index 00cf4de..3088792 100755
--- a/par_usage_statistics.html
+++ b/par_usage_statistics.html
@@ -6,20 +6,20 @@
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>63</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>4.6 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>4.6 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>5.4 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>6.1 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>6.2 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>4.7 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>5.5 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>6.3 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>6.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>6.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>6.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>6.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>6.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>6.3 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>25.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>0.5</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>27.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>1.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>37.8</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>5.6</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>38.3</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>5.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
@@ -27,6 +27,6 @@
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0040</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0011</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
diff --git a/planAhead.ngc2edif.log b/planAhead.ngc2edif.log
index 00c1f0a..cf6c2fc 100755
--- a/planAhead.ngc2edif.log
+++ b/planAhead.ngc2edif.log
@@ -9,3 +9,91 @@ Processing design ...
Writing EDIF netlist file ALU.edif ...
ngc2edif: Total memory usage is 78968 kilobytes
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91624 kilobytes
+
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91624 kilobytes
+
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91432 kilobytes
+
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91752 kilobytes
+
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91560 kilobytes
+
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91880 kilobytes
+
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91368 kilobytes
+
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91304 kilobytes
+
diff --git a/planAhead_run_1/lab1.data/cache/ALU_ngc_c04f956c.edif b/planAhead_run_1/lab1.data/cache/ALU_ngc_c04f956c.edif
new file mode 100755
index 0000000..0b84157
--- /dev/null
+++ b/planAhead_run_1/lab1.data/cache/ALU_ngc_c04f956c.edif
@@ -0,0 +1,2404 @@
+(edif ALU
+ (edifVersion 2 0 0)
+ (edifLevel 0)
+ (keywordMap (keywordLevel 0))
+ (status
+ (written
+ (timestamp 2012 2 16 18 17 18)
+ (program "Xilinx ngc2edif" (version "O.76xd"))
+ (author "Xilinx. Inc ")
+ (comment "This EDIF netlist is to be used within supported synthesis tools")
+ (comment "for determining resource/timing estimates of the design component")
+ (comment "represented by this netlist.")
+ (comment "Command line: -mdp2sp -w -secure ALU.ngc ALU.edif ")))
+ (external UNISIMS
+ (edifLevel 0)
+ (technology (numberDefinition))
+ (cell GND
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port G
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell VCC
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port P
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell OR3
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell OR2
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell INV
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell AND2
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell AND4
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port I3
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell NOR3
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell AND3
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell NAND4
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port I3
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell NAND3
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell XNOR2
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell OR4
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port I3
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell NAND2
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell LUT6
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port I3
+ (direction INPUT)
+ )
+ (port I4
+ (direction INPUT)
+ )
+ (port I5
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell BUF
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell OR5
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port I3
+ (direction INPUT)
+ )
+ (port I4
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell XOR2
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell IBUF
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell OBUF
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ )
+
+ (library ALU_lib
+ (edifLevel 0)
+ (technology (numberDefinition))
+ (cell (rename M4_1E_HXILINX_ALU_NO3_XLXI_4 "M4_1E_HXILINX_ALU")
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port D0
+ (direction INPUT)
+ )
+ (port D1
+ (direction INPUT)
+ )
+ (port D2
+ (direction INPUT)
+ )
+ (port D3
+ (direction INPUT)
+ )
+ (port E
+ (direction INPUT)
+ )
+ (port S0
+ (direction INPUT)
+ )
+ (port S1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ (contents
+ (instance Mmux_O11
+ (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx"))
+ )
+ (net D0
+ (joined
+ (portRef D0)
+ (portRef I4 (instanceRef Mmux_O11))
+ )
+ )
+ (net D1
+ (joined
+ (portRef D1)
+ (portRef I3 (instanceRef Mmux_O11))
+ )
+ )
+ (net D2
+ (joined
+ (portRef D2)
+ (portRef I5 (instanceRef Mmux_O11))
+ )
+ )
+ (net D3
+ (joined
+ (portRef D3)
+ (portRef I1 (instanceRef Mmux_O11))
+ )
+ )
+ (net S0
+ (joined
+ (portRef S0)
+ (portRef I0 (instanceRef Mmux_O11))
+ )
+ )
+ (net S1
+ (joined
+ (portRef S1)
+ (portRef I2 (instanceRef Mmux_O11))
+ )
+ )
+ (net O
+ (joined
+ (portRef O)
+ (portRef O (instanceRef Mmux_O11))
+ )
+ )
+ )
+ )
+ )
+ (cell (rename M4_1E_HXILINX_ALU_NO2_XLXI_5 "M4_1E_HXILINX_ALU")
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port D0
+ (direction INPUT)
+ )
+ (port D1
+ (direction INPUT)
+ )
+ (port D2
+ (direction INPUT)
+ )
+ (port D3
+ (direction INPUT)
+ )
+ (port E
+ (direction INPUT)
+ )
+ (port S0
+ (direction INPUT)
+ )
+ (port S1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ (contents
+ (instance Mmux_O11
+ (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx"))
+ )
+ (net D0
+ (joined
+ (portRef D0)
+ (portRef I4 (instanceRef Mmux_O11))
+ )
+ )
+ (net D1
+ (joined
+ (portRef D1)
+ (portRef I3 (instanceRef Mmux_O11))
+ )
+ )
+ (net D2
+ (joined
+ (portRef D2)
+ (portRef I5 (instanceRef Mmux_O11))
+ )
+ )
+ (net D3
+ (joined
+ (portRef D3)
+ (portRef I1 (instanceRef Mmux_O11))
+ )
+ )
+ (net S0
+ (joined
+ (portRef S0)
+ (portRef I0 (instanceRef Mmux_O11))
+ )
+ )
+ (net S1
+ (joined
+ (portRef S1)
+ (portRef I2 (instanceRef Mmux_O11))
+ )
+ )
+ (net O
+ (joined
+ (portRef O)
+ (portRef O (instanceRef Mmux_O11))
+ )
+ )
+ )
+ )
+ )
+ (cell (rename M4_1E_HXILINX_ALU_NO1_XLXI_6 "M4_1E_HXILINX_ALU")
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port D0
+ (direction INPUT)
+ )
+ (port D1
+ (direction INPUT)
+ )
+ (port D2
+ (direction INPUT)
+ )
+ (port D3
+ (direction INPUT)
+ )
+ (port E
+ (direction INPUT)
+ )
+ (port S0
+ (direction INPUT)
+ )
+ (port S1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ (contents
+ (instance Mmux_O11
+ (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx"))
+ )
+ (net D0
+ (joined
+ (portRef D0)
+ (portRef I4 (instanceRef Mmux_O11))
+ )
+ )
+ (net D1
+ (joined
+ (portRef D1)
+ (portRef I3 (instanceRef Mmux_O11))
+ )
+ )
+ (net D2
+ (joined
+ (portRef D2)
+ (portRef I5 (instanceRef Mmux_O11))
+ )
+ )
+ (net D3
+ (joined
+ (portRef D3)
+ (portRef I1 (instanceRef Mmux_O11))
+ )
+ )
+ (net S0
+ (joined
+ (portRef S0)
+ (portRef I0 (instanceRef Mmux_O11))
+ )
+ )
+ (net S1
+ (joined
+ (portRef S1)
+ (portRef I2 (instanceRef Mmux_O11))
+ )
+ )
+ (net O
+ (joined
+ (portRef O)
+ (portRef O (instanceRef Mmux_O11))
+ )
+ )
+ )
+ )
+ )
+ (cell (rename M4_1E_HXILINX_ALU_XLXI_7 "M4_1E_HXILINX_ALU")
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port D0
+ (direction INPUT)
+ )
+ (port D1
+ (direction INPUT)
+ )
+ (port D2
+ (direction INPUT)
+ )
+ (port D3
+ (direction INPUT)
+ )
+ (port E
+ (direction INPUT)
+ )
+ (port S0
+ (direction INPUT)
+ )
+ (port S1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ (contents
+ (instance Mmux_O11
+ (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx"))
+ )
+ (net D0
+ (joined
+ (portRef D0)
+ (portRef I4 (instanceRef Mmux_O11))
+ )
+ )
+ (net D1
+ (joined
+ (portRef D1)
+ (portRef I3 (instanceRef Mmux_O11))
+ )
+ )
+ (net D2
+ (joined
+ (portRef D2)
+ (portRef I5 (instanceRef Mmux_O11))
+ )
+ )
+ (net D3
+ (joined
+ (portRef D3)
+ (portRef I1 (instanceRef Mmux_O11))
+ )
+ )
+ (net S0
+ (joined
+ (portRef S0)
+ (portRef I0 (instanceRef Mmux_O11))
+ )
+ )
+ (net S1
+ (joined
+ (portRef S1)
+ (portRef I2 (instanceRef Mmux_O11))
+ )
+ )
+ (net O
+ (joined
+ (portRef O)
+ (portRef O (instanceRef Mmux_O11))
+ )
+ )
+ )
+ )
+ )
+ (cell ALU
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port A
+ (direction INPUT)
+ )
+ (port B
+ (direction INPUT)
+ )
+ (port C
+ (direction INPUT)
+ )
+ (port D
+ (direction INPUT)
+ )
+ (port S0
+ (direction INPUT)
+ )
+ (port S1
+ (direction INPUT)
+ )
+ (port AN0
+ (direction OUTPUT)
+ )
+ (port AN1
+ (direction OUTPUT)
+ )
+ (port AN2
+ (direction OUTPUT)
+ )
+ (port AN3
+ (direction OUTPUT)
+ )
+ (port a_out
+ (direction OUTPUT)
+ )
+ (port b_out
+ (direction OUTPUT)
+ )
+ (port c_out
+ (direction OUTPUT)
+ )
+ (port d_out
+ (direction OUTPUT)
+ )
+ (port e_out
+ (direction OUTPUT)
+ )
+ (port f_out
+ (direction OUTPUT)
+ )
+ (port g_out
+ (direction OUTPUT)
+ )
+ (port sign
+ (direction OUTPUT)
+ )
+ (designator "xc6slx16-3-csg324")
+ (property TYPE (string "ALU") (owner "Xilinx"))
+ (property SHREG_MIN_SIZE (string "2") (owner "Xilinx"))
+ (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx"))
+ (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
+ (property NLW_MACRO_TAG (integer 0) (owner "Xilinx"))
+ (property NLW_MACRO_ALIAS (string "ALU_ALU") (owner "Xilinx"))
+ )
+ (contents
+ (instance XST_GND
+ (viewRef view_1 (cellRef GND (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance XLXI_8
+ (viewRef view_1 (cellRef VCC (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_2 "XLXI_1/XLXI_8/XLXI_2")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_5 "XLXI_1/XLXI_8/XLXI_5")
+ (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_7 "XLXI_1/XLXI_8/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_6 "XLXI_1/XLXI_8/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_4 "XLXI_1/XLXI_8/XLXI_4")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_8 "XLXI_1/XLXI_8/XLXI_8")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_3 "XLXI_1/XLXI_8/XLXI_3")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_9 "XLXI_1/XLXI_8/XLXI_9")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_1 "XLXI_1/XLXI_8/XLXI_1")
+ (viewRef view_1 (cellRef AND4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_9_XLXI_10 "XLXI_1/XLXI_9/XLXI_10")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_9_XLXI_11 "XLXI_1/XLXI_9/XLXI_11")
+ (viewRef view_1 (cellRef NOR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_10_XLXI_2 "XLXI_1/XLXI_10/XLXI_2")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_10_XLXI_3 "XLXI_1/XLXI_10/XLXI_3")
+ (viewRef view_1 (cellRef NOR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_7 "XLXI_1/XLXI_12/XLXI_7")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_4 "XLXI_1/XLXI_12/XLXI_4")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_5 "XLXI_1/XLXI_12/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_3 "XLXI_1/XLXI_12/XLXI_3")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_2 "XLXI_1/XLXI_12/XLXI_2")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_6 "XLXI_1/XLXI_12/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_1 "XLXI_1/XLXI_12/XLXI_1")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_4 "XLXI_2/XLXI_2/XLXI_4")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_2 "XLXI_2/XLXI_2/XLXI_2")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_7 "XLXI_2/XLXI_2/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_5 "XLXI_2/XLXI_2/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_1 "XLXI_2/XLXI_2/XLXI_1")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_6 "XLXI_2/XLXI_2/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_3 "XLXI_2/XLXI_2/XLXI_3")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_4 "XLXI_2/XLXI_1/XLXI_4")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_2 "XLXI_2/XLXI_1/XLXI_2")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_7 "XLXI_2/XLXI_1/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_5 "XLXI_2/XLXI_1/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_1 "XLXI_2/XLXI_1/XLXI_1")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_6 "XLXI_2/XLXI_1/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_3 "XLXI_2/XLXI_1/XLXI_3")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_17 "XLXI_2/XLXI_3/XLXI_17")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_4 "XLXI_2/XLXI_3/XLXI_4")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_15 "XLXI_2/XLXI_3/XLXI_15")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_2 "XLXI_2/XLXI_3/XLXI_2")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_7 "XLXI_2/XLXI_3/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_16 "XLXI_2/XLXI_3/XLXI_16")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_14 "XLXI_2/XLXI_3/XLXI_14")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_5 "XLXI_2/XLXI_3/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_1 "XLXI_2/XLXI_3/XLXI_1")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_13 "XLXI_2/XLXI_3/XLXI_13")
+ (viewRef view_1 (cellRef NAND4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_11 "XLXI_2/XLXI_3/XLXI_11")
+ (viewRef view_1 (cellRef AND4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_6 "XLXI_2/XLXI_3/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_3 "XLXI_2/XLXI_3/XLXI_3")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_4 "XLXI_2/XLXI_4/XLXI_4")
+ (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_2 "XLXI_2/XLXI_4/XLXI_2")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_3 "XLXI_2/XLXI_4/XLXI_3")
+ (viewRef view_1 (cellRef NAND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_5 "XLXI_2/XLXI_4/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_1 "XLXI_2/XLXI_4/XLXI_1")
+ (viewRef view_1 (cellRef XNOR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_8_XLXI_8 "XLXI_3/XLXI_8/XLXI_8")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_8_XLXI_10 "XLXI_3/XLXI_8/XLXI_10")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_8_XLXI_9 "XLXI_3/XLXI_8/XLXI_9")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_8_XLXI_12 "XLXI_3/XLXI_8/XLXI_12")
+ (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_4 "XLXI_3/XLXI_9/XLXI_4")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_3 "XLXI_3/XLXI_9/XLXI_3")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_5 "XLXI_3/XLXI_9/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_6 "XLXI_3/XLXI_9/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_1 "XLXI_3/XLXI_9/XLXI_1")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_7 "XLXI_3/XLXI_9/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_2 "XLXI_3/XLXI_9/XLXI_2")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_8 "XLXI_3/XLXI_10/XLXI_8")
+ (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_9 "XLXI_3/XLXI_10/XLXI_9")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_14 "XLXI_3/XLXI_10/XLXI_14")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_10 "XLXI_3/XLXI_10/XLXI_10")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_12 "XLXI_3/XLXI_10/XLXI_12")
+ (viewRef view_1 (cellRef NAND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_11 "XLXI_3/XLXI_10/XLXI_11")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_12_XLXI_9 "XLXI_3/XLXI_12/XLXI_9")
+ (viewRef view_1 (cellRef NAND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_12_XLXI_13 "XLXI_3/XLXI_12/XLXI_13")
+ (viewRef view_1 (cellRef NOR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance XLXI_7
+ (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_XLXI_7 (libraryRef ALU_lib)))
+ (property HU_SET (string "XLXI_7_3") (owner "Xilinx"))
+ (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
+ (property NLW_MACRO_TAG (integer 1) (owner "Xilinx"))
+ (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_XLXI_7") (owner "Xilinx"))
+ )
+ (instance XLXI_6
+ (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_NO1_XLXI_6 (libraryRef ALU_lib)))
+ (property HU_SET (string "XLXI_6_2") (owner "Xilinx"))
+ (property NLW_UNIQUE_ID (integer 1) (owner "Xilinx"))
+ (property NLW_MACRO_TAG (integer 2) (owner "Xilinx"))
+ (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_NO1_XLXI_6") (owner "Xilinx"))
+ )
+ (instance XLXI_5
+ (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_NO2_XLXI_5 (libraryRef ALU_lib)))
+ (property HU_SET (string "XLXI_5_1") (owner "Xilinx"))
+ (property NLW_UNIQUE_ID (integer 2) (owner "Xilinx"))
+ (property NLW_MACRO_TAG (integer 3) (owner "Xilinx"))
+ (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_NO2_XLXI_5") (owner "Xilinx"))
+ )
+ (instance XLXI_4
+ (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_NO3_XLXI_4 (libraryRef ALU_lib)))
+ (property HU_SET (string "XLXI_4_0") (owner "Xilinx"))
+ (property NLW_UNIQUE_ID (integer 3) (owner "Xilinx"))
+ (property NLW_MACRO_TAG (integer 4) (owner "Xilinx"))
+ (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_NO3_XLXI_4") (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_8 "XLXI_9/XLXI_8")
+ (viewRef view_1 (cellRef BUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_7 "XLXI_9/XLXI_7")
+ (viewRef view_1 (cellRef BUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_6 "XLXI_9/XLXI_6")
+ (viewRef view_1 (cellRef BUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_5 "XLXI_9/XLXI_5")
+ (viewRef view_1 (cellRef BUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_68 "XLXI_9/XLXI_68")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_69 "XLXI_9/XLXI_69")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_71 "XLXI_9/XLXI_71")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_70 "XLXI_9/XLXI_70")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_66 "XLXI_9/XLXI_66")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_73 "XLXI_9/XLXI_73")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_65 "XLXI_9/XLXI_65")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_67 "XLXI_9/XLXI_67")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_53 "XLXI_9/XLXI_53")
+ (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_57 "XLXI_9/XLXI_57")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_43 "XLXI_9/XLXI_43")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_52 "XLXI_9/XLXI_52")
+ (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_49 "XLXI_9/XLXI_49")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_44 "XLXI_9/XLXI_44")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_32 "XLXI_9/XLXI_32")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_60 "XLXI_9/XLXI_60")
+ (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_58 "XLXI_9/XLXI_58")
+ (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_41 "XLXI_9/XLXI_41")
+ (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_72 "XLXI_9/XLXI_72")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_34 "XLXI_9/XLXI_34")
+ (viewRef view_1 (cellRef OR5 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_47 "XLXI_9/XLXI_47")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_40 "XLXI_9/XLXI_40")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_63 "XLXI_9/XLXI_63")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_62 "XLXI_9/XLXI_62")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_50 "XLXI_9/XLXI_50")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_48 "XLXI_9/XLXI_48")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_45 "XLXI_9/XLXI_45")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_39 "XLXI_9/XLXI_39")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_33 "XLXI_9/XLXI_33")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_31 "XLXI_9/XLXI_31")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_61 "XLXI_9/XLXI_61")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_56 "XLXI_9/XLXI_56")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_54 "XLXI_9/XLXI_54")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_51 "XLXI_9/XLXI_51")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_38 "XLXI_9/XLXI_38")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_30 "XLXI_9/XLXI_30")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_64 "XLXI_9/XLXI_64")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_55 "XLXI_9/XLXI_55")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_46 "XLXI_9/XLXI_46")
+ (viewRef view_1 (cellRef XOR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_42 "XLXI_9/XLXI_42")
+ (viewRef view_1 (cellRef XNOR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_37 "XLXI_9/XLXI_37")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_35 "XLXI_9/XLXI_35")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename A_IBUF_renamed_0 "A_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename B_IBUF_renamed_1 "B_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename C_IBUF_renamed_2 "C_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename D_IBUF_renamed_3 "D_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename S0_IBUF_renamed_4 "S0_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename S1_IBUF_renamed_5 "S1_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename AN0_OBUF_renamed_6 "AN0_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename AN1_OBUF_renamed_7 "AN1_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename AN2_OBUF_renamed_8 "AN2_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename AN3_OBUF_renamed_9 "AN3_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename a_out_OBUF_renamed_10 "a_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename b_out_OBUF_renamed_11 "b_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename c_out_OBUF_renamed_12 "c_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename d_out_OBUF_renamed_13 "d_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename e_out_OBUF_renamed_14 "e_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename f_out_OBUF_renamed_15 "f_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename g_out_OBUF_renamed_16 "g_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename sign_OBUF_renamed_17 "sign_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (net A_IBUF
+ (joined
+ (portRef I (instanceRef XLXI_1_XLXI_8_XLXI_7))
+ (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_1))
+ (portRef I1 (instanceRef XLXI_1_XLXI_9_XLXI_10))
+ (portRef I1 (instanceRef XLXI_1_XLXI_10_XLXI_2))
+ (portRef I2 (instanceRef XLXI_2_XLXI_2_XLXI_2))
+ (portRef I2 (instanceRef XLXI_2_XLXI_2_XLXI_1))
+ (portRef I2 (instanceRef XLXI_2_XLXI_2_XLXI_3))
+ (portRef I2 (instanceRef XLXI_2_XLXI_1_XLXI_2))
+ (portRef I2 (instanceRef XLXI_2_XLXI_1_XLXI_1))
+ (portRef I2 (instanceRef XLXI_2_XLXI_1_XLXI_3))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_15))
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_2))
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_1))
+ (portRef I3 (instanceRef XLXI_2_XLXI_3_XLXI_13))
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_3))
+ (portRef I0 (instanceRef XLXI_3_XLXI_8_XLXI_8))
+ (portRef I2 (instanceRef XLXI_3_XLXI_9_XLXI_3))
+ (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_9))
+ (portRef I1 (instanceRef XLXI_3_XLXI_12_XLXI_9))
+ (portRef D0 (instanceRef XLXI_4))
+ (portRef O (instanceRef A_IBUF_renamed_0))
+ )
+ )
+ (net B_IBUF
+ (joined
+ (portRef I (instanceRef XLXI_1_XLXI_8_XLXI_6))
+ (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_4))
+ (portRef I0 (instanceRef XLXI_1_XLXI_9_XLXI_11))
+ (portRef I2 (instanceRef XLXI_1_XLXI_10_XLXI_3))
+ (portRef I (instanceRef XLXI_1_XLXI_12_XLXI_5))
+ (portRef I0 (instanceRef XLXI_1_XLXI_12_XLXI_3))
+ (portRef I0 (instanceRef XLXI_1_XLXI_12_XLXI_2))
+ (portRef I (instanceRef XLXI_2_XLXI_2_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_2_XLXI_1))
+ (portRef I (instanceRef XLXI_2_XLXI_1_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_1))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_1))
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_13))
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_11))
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_2))
+ (portRef I2 (instanceRef XLXI_2_XLXI_4_XLXI_3))
+ (portRef I (instanceRef XLXI_3_XLXI_8_XLXI_10))
+ (portRef I (instanceRef XLXI_3_XLXI_9_XLXI_5))
+ (portRef I (instanceRef XLXI_3_XLXI_10_XLXI_14))
+ (portRef I2 (instanceRef XLXI_3_XLXI_12_XLXI_13))
+ (portRef D0 (instanceRef XLXI_5))
+ (portRef O (instanceRef B_IBUF_renamed_1))
+ )
+ )
+ (net C_IBUF
+ (joined
+ (portRef I (instanceRef XLXI_1_XLXI_8_XLXI_8))
+ (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_3))
+ (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_1))
+ (portRef I1 (instanceRef XLXI_1_XLXI_9_XLXI_11))
+ (portRef I1 (instanceRef XLXI_1_XLXI_10_XLXI_3))
+ (portRef I (instanceRef XLXI_1_XLXI_12_XLXI_6))
+ (portRef I0 (instanceRef XLXI_1_XLXI_12_XLXI_1))
+ (portRef I (instanceRef XLXI_2_XLXI_2_XLXI_5))
+ (portRef I0 (instanceRef XLXI_2_XLXI_2_XLXI_1))
+ (portRef I (instanceRef XLXI_2_XLXI_1_XLXI_5))
+ (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_1))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_16))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_14))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_5))
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_1))
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_3))
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_1))
+ (portRef I (instanceRef XLXI_3_XLXI_8_XLXI_9))
+ (portRef I (instanceRef XLXI_3_XLXI_9_XLXI_6))
+ (portRef I0 (instanceRef XLXI_3_XLXI_9_XLXI_1))
+ (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_10))
+ (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_12))
+ (portRef I1 (instanceRef XLXI_3_XLXI_12_XLXI_13))
+ (portRef D0 (instanceRef XLXI_6))
+ (portRef O (instanceRef C_IBUF_renamed_2))
+ )
+ )
+ (net D_IBUF
+ (joined
+ (portRef I (instanceRef XLXI_1_XLXI_8_XLXI_9))
+ (portRef I3 (instanceRef XLXI_1_XLXI_8_XLXI_1))
+ (portRef I2 (instanceRef XLXI_1_XLXI_9_XLXI_11))
+ (portRef I0 (instanceRef XLXI_1_XLXI_10_XLXI_3))
+ (portRef I (instanceRef XLXI_1_XLXI_12_XLXI_4))
+ (portRef I1 (instanceRef XLXI_1_XLXI_12_XLXI_1))
+ (portRef I (instanceRef XLXI_2_XLXI_2_XLXI_6))
+ (portRef I0 (instanceRef XLXI_2_XLXI_2_XLXI_3))
+ (portRef I (instanceRef XLXI_2_XLXI_1_XLXI_6))
+ (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_3))
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_13))
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_11))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_6))
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_3))
+ (portRef I (instanceRef XLXI_2_XLXI_4_XLXI_5))
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_1))
+ (portRef I1 (instanceRef XLXI_3_XLXI_8_XLXI_12))
+ (portRef I (instanceRef XLXI_3_XLXI_9_XLXI_7))
+ (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_2))
+ (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_12))
+ (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_11))
+ (portRef I0 (instanceRef XLXI_3_XLXI_12_XLXI_13))
+ (portRef D0 (instanceRef XLXI_7))
+ (portRef O (instanceRef D_IBUF_renamed_3))
+ )
+ )
+ (net S0_IBUF
+ (joined
+ (portRef S0 (instanceRef XLXI_7))
+ (portRef S0 (instanceRef XLXI_6))
+ (portRef S0 (instanceRef XLXI_5))
+ (portRef S0 (instanceRef XLXI_4))
+ (portRef O (instanceRef S0_IBUF_renamed_4))
+ )
+ )
+ (net S1_IBUF
+ (joined
+ (portRef S1 (instanceRef XLXI_7))
+ (portRef S1 (instanceRef XLXI_6))
+ (portRef S1 (instanceRef XLXI_5))
+ (portRef S1 (instanceRef XLXI_4))
+ (portRef O (instanceRef S1_IBUF_renamed_5))
+ )
+ )
+ (net XLXN_36
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_7))
+ (portRef D2 (instanceRef XLXI_7))
+ )
+ )
+ (net XLXN_35
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_5))
+ (portRef D2 (instanceRef XLXI_6))
+ )
+ )
+ (net XLXN_34
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_9_XLXI_10))
+ (portRef D2 (instanceRef XLXI_5))
+ )
+ )
+ (net XLXN_33
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_10_XLXI_2))
+ (portRef D2 (instanceRef XLXI_4))
+ )
+ )
+ (net XLXN_37
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_4))
+ (portRef D3 (instanceRef XLXI_7))
+ )
+ )
+ (net XLXN_38
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_17))
+ (portRef D3 (instanceRef XLXI_6))
+ )
+ )
+ (net XLXN_39
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_4))
+ (portRef D3 (instanceRef XLXI_5))
+ )
+ )
+ (net XLXN_41
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_4))
+ (portRef D3 (instanceRef XLXI_4))
+ )
+ )
+ (net XLXN_27
+ (joined
+ (portRef O (instanceRef XLXI_3_XLXI_8_XLXI_12))
+ (portRef D1 (instanceRef XLXI_5))
+ )
+ )
+ (net XLXN_28
+ (joined
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_4))
+ (portRef D1 (instanceRef XLXI_6))
+ )
+ )
+ (net XLXN_31
+ (joined
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_8))
+ (portRef D1 (instanceRef XLXI_7))
+ )
+ )
+ (net XLXN_26
+ (joined
+ (portRef O (instanceRef XLXI_3_XLXI_12_XLXI_9))
+ (portRef D1 (instanceRef XLXI_4))
+ )
+ )
+ (net XLXN_22
+ (joined
+ (portRef O (instanceRef XLXI_4))
+ (portRef I1 (instanceRef XLXI_9_XLXI_35))
+ (portRef I (instanceRef XLXI_9_XLXI_37))
+ (portRef I1 (instanceRef XLXI_9_XLXI_42))
+ (portRef I1 (instanceRef XLXI_9_XLXI_46))
+ (portRef I2 (instanceRef XLXI_9_XLXI_55))
+ (portRef I1 (instanceRef XLXI_9_XLXI_64))
+ )
+ )
+ (net XLXN_23
+ (joined
+ (portRef O (instanceRef XLXI_5))
+ (portRef I0 (instanceRef XLXI_9_XLXI_42))
+ (portRef I0 (instanceRef XLXI_9_XLXI_46))
+ (portRef I0 (instanceRef XLXI_9_XLXI_30))
+ (portRef I (instanceRef XLXI_9_XLXI_38))
+ (portRef I2 (instanceRef XLXI_9_XLXI_51))
+ (portRef I1 (instanceRef XLXI_9_XLXI_54))
+ (portRef I1 (instanceRef XLXI_9_XLXI_56))
+ (portRef I1 (instanceRef XLXI_9_XLXI_61))
+ )
+ )
+ (net XLXN_24
+ (joined
+ (portRef O (instanceRef XLXI_6))
+ (portRef I0 (instanceRef XLXI_9_XLXI_55))
+ (portRef I2 (instanceRef XLXI_9_XLXI_31))
+ (portRef I0 (instanceRef XLXI_9_XLXI_33))
+ (portRef I (instanceRef XLXI_9_XLXI_39))
+ (portRef I2 (instanceRef XLXI_9_XLXI_45))
+ (portRef I1 (instanceRef XLXI_9_XLXI_48))
+ (portRef I0 (instanceRef XLXI_9_XLXI_50))
+ (portRef I1 (instanceRef XLXI_9_XLXI_62))
+ (portRef I1 (instanceRef XLXI_9_XLXI_63))
+ )
+ )
+ (net XLXN_25
+ (joined
+ (portRef O (instanceRef XLXI_7))
+ (portRef I2 (instanceRef XLXI_9_XLXI_30))
+ (portRef I1 (instanceRef XLXI_9_XLXI_51))
+ (portRef I1 (instanceRef XLXI_9_XLXI_31))
+ (portRef I1 (instanceRef XLXI_9_XLXI_45))
+ (portRef I (instanceRef XLXI_9_XLXI_40))
+ (portRef I0 (instanceRef XLXI_9_XLXI_47))
+ )
+ )
+ (net AN0_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_5))
+ (portRef I (instanceRef AN0_OBUF_renamed_6))
+ )
+ )
+ (net AN1_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_6))
+ (portRef I (instanceRef AN1_OBUF_renamed_7))
+ )
+ )
+ (net AN2_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_7))
+ (portRef I (instanceRef AN2_OBUF_renamed_8))
+ )
+ )
+ (net AN3_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_8))
+ (portRef I (instanceRef AN3_OBUF_renamed_9))
+ )
+ )
+ (net a_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_65))
+ (portRef I (instanceRef a_out_OBUF_renamed_10))
+ )
+ )
+ (net b_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_66))
+ (portRef I (instanceRef b_out_OBUF_renamed_11))
+ )
+ )
+ (net c_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_67))
+ (portRef I (instanceRef c_out_OBUF_renamed_12))
+ )
+ )
+ (net d_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_69))
+ (portRef I (instanceRef d_out_OBUF_renamed_13))
+ )
+ )
+ (net e_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_68))
+ (portRef I (instanceRef e_out_OBUF_renamed_14))
+ )
+ )
+ (net f_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_70))
+ (portRef I (instanceRef f_out_OBUF_renamed_15))
+ )
+ )
+ (net g_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_71))
+ (portRef I (instanceRef g_out_OBUF_renamed_16))
+ )
+ )
+ (net sign_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_73))
+ (portRef I (instanceRef sign_OBUF_renamed_17))
+ )
+ )
+ (net XLXN_12
+ (joined
+ (portRef P (instanceRef XLXI_8))
+ (portRef E (instanceRef XLXI_7))
+ (portRef E (instanceRef XLXI_6))
+ (portRef E (instanceRef XLXI_5))
+ (portRef E (instanceRef XLXI_4))
+ (portRef I (instanceRef XLXI_9_XLXI_5))
+ (portRef I (instanceRef XLXI_9_XLXI_6))
+ (portRef I (instanceRef XLXI_9_XLXI_7))
+ )
+ )
+ (net N0
+ (joined
+ (portRef G (instanceRef XST_GND))
+ (portRef I (instanceRef XLXI_9_XLXI_8))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_2 "XLXI_1/XLXI_8/XLXN_2")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_2))
+ (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_4))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_13 "XLXI_1/XLXI_8/XLXN_13")
+ (joined
+ (portRef I2 (instanceRef XLXI_1_XLXI_8_XLXI_2))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_7))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_8 "XLXI_1/XLXI_8/XLXN_8")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_6))
+ (portRef I2 (instanceRef XLXI_1_XLXI_8_XLXI_1))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_4 "XLXI_1/XLXI_8/XLXN_4")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_5))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_4))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_16 "XLXI_1/XLXI_8/XLXN_16")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_2))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_8))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_1 "XLXI_1/XLXI_8/XLXN_1")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_2))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_3))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_17 "XLXI_1/XLXI_8/XLXN_17")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_3))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_9))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_5 "XLXI_1/XLXI_8/XLXN_5")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_5))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_1))
+ )
+ )
+ (net (rename XLXI_1_XLXI_9_XLXN_9 "XLXI_1/XLXI_9/XLXN_9")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_9_XLXI_10))
+ (portRef O (instanceRef XLXI_1_XLXI_9_XLXI_11))
+ )
+ )
+ (net (rename XLXI_1_XLXI_10_XLXN_2 "XLXI_1/XLXI_10/XLXN_2")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_10_XLXI_2))
+ (portRef O (instanceRef XLXI_1_XLXI_10_XLXI_3))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_1 "XLXI_1/XLXI_12/XLXN_1")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_4))
+ (portRef I1 (instanceRef XLXI_1_XLXI_12_XLXI_2))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_2 "XLXI_1/XLXI_12/XLXN_2")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_5))
+ (portRef I2 (instanceRef XLXI_1_XLXI_12_XLXI_1))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_6 "XLXI_1/XLXI_12/XLXN_6")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_12_XLXI_7))
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_3))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_4 "XLXI_1/XLXI_12/XLXN_4")
+ (joined
+ (portRef I2 (instanceRef XLXI_1_XLXI_12_XLXI_7))
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_2))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_3 "XLXI_1/XLXI_12/XLXN_3")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_12_XLXI_3))
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_6))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_5 "XLXI_1/XLXI_12/XLXN_5")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_12_XLXI_7))
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_1))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_2 "XLXI_2/XLXI_2/XLXN_2")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_2_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_2))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_7 "XLXI_2/XLXI_2/XLXN_7")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_2_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_5 "XLXI_2/XLXI_2/XLXN_5")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_2_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_5))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_1 "XLXI_2/XLXI_2/XLXN_1")
+ (joined
+ (portRef I2 (instanceRef XLXI_2_XLXI_2_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_1))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_6 "XLXI_2/XLXI_2/XLXN_6")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_2_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_6))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_3 "XLXI_2/XLXI_2/XLXN_3")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_2_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_2 "XLXI_2/XLXI_1/XLXN_2")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_2))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_7 "XLXI_2/XLXI_1/XLXN_7")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_5 "XLXI_2/XLXI_1/XLXN_5")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_5))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_1 "XLXI_2/XLXI_1/XLXN_1")
+ (joined
+ (portRef I2 (instanceRef XLXI_2_XLXI_1_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_1))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_6 "XLXI_2/XLXI_1/XLXN_6")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_6))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_3 "XLXI_2/XLXI_1/XLXN_3")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_21 "XLXI_2/XLXI_3/XLXN_21")
+ (joined
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_17))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_4))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_23 "XLXI_2/XLXI_3/XLXN_23")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_15))
+ (portRef I3 (instanceRef XLXI_2_XLXI_3_XLXI_11))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_2 "XLXI_2/XLXI_3/XLXN_2")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_2))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_7 "XLXI_2/XLXI_3/XLXN_7")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_24 "XLXI_2/XLXI_3/XLXN_24")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_16))
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_11))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_22 "XLXI_2/XLXI_3/XLXN_22")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_14))
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_13))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_5 "XLXI_2/XLXI_3/XLXN_5")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_5))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_1 "XLXI_2/XLXI_3/XLXN_1")
+ (joined
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_1))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_31 "XLXI_2/XLXI_3/XLXN_31")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_17))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_13))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_46 "XLXI_2/XLXI_3/XLXN_46")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_17))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_11))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_6 "XLXI_2/XLXI_3/XLXN_6")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_6))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_3 "XLXI_2/XLXI_3/XLXN_3")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_4 "XLXI_2/XLXI_4/XLXN_4")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_2))
+ )
+ )
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+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_5 "XLXI_2/XLXI_4/XLXN_5")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_3))
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_5))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_1 "XLXI_2/XLXI_4/XLXN_1")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_1))
+ )
+ )
+ (net (rename XLXI_3_XLXI_8_XLXN_17 "XLXI_3/XLXI_8/XLXN_17")
+ (joined
+ (portRef O (instanceRef XLXI_3_XLXI_8_XLXI_8))
+ (portRef I0 (instanceRef XLXI_3_XLXI_8_XLXI_12))
+ )
+ )
+ (net (rename XLXI_3_XLXI_8_XLXN_15 "XLXI_3/XLXI_8/XLXN_15")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_8_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_8_XLXI_10))
+ )
+ )
+ (net (rename XLXI_3_XLXI_8_XLXN_14 "XLXI_3/XLXI_8/XLXN_14")
+ (joined
+ (portRef I2 (instanceRef XLXI_3_XLXI_8_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_8_XLXI_9))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_3 "XLXI_3/XLXI_9/XLXN_3")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_9_XLXI_4))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_3))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_4 "XLXI_3/XLXI_9/XLXN_4")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_9_XLXI_3))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_5))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_5 "XLXI_3/XLXI_9/XLXN_5")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_3))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_6))
+ (portRef I0 (instanceRef XLXI_3_XLXI_9_XLXI_2))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_2 "XLXI_3/XLXI_9/XLXN_2")
+ (joined
+ (portRef I2 (instanceRef XLXI_3_XLXI_9_XLXI_4))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_1))
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+ )
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+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_1))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_7))
+ )
+ )
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+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_4))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_2))
+ )
+ )
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+ (joined
+ (portRef I3 (instanceRef XLXI_3_XLXI_10_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_9))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_44 "XLXI_3/XLXI_10/XLXN_44")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_9))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_14))
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+ (portRef I2 (instanceRef XLXI_3_XLXI_10_XLXI_12))
+ (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_11))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_41 "XLXI_3/XLXI_10/XLXN_41")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_10))
+ )
+ )
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+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_12))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_40 "XLXI_3/XLXI_10/XLXN_40")
+ (joined
+ (portRef I2 (instanceRef XLXI_3_XLXI_10_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_11))
+ )
+ )
+ (net (rename XLXI_3_XLXI_12_XLXN_8 "XLXI_3/XLXI_12/XLXN_8")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_12_XLXI_9))
+ (portRef O (instanceRef XLXI_3_XLXI_12_XLXI_13))
+ )
+ )
+ (net (rename XLXI_9_XLXN_158 "XLXI_9/XLXN_158")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_53))
+ (portRef I (instanceRef XLXI_9_XLXI_68))
+ )
+ )
+ (net (rename XLXI_9_XLXN_131 "XLXI_9/XLXN_131")
+ (joined
+ (portRef I0 (instanceRef XLXI_9_XLXI_58))
+ (portRef O (instanceRef XLXI_9_XLXI_57))
+ )
+ )
+ (net (rename XLXI_9_XLXN_92 "XLXI_9/XLXN_92")
+ (joined
+ (portRef I2 (instanceRef XLXI_9_XLXI_41))
+ (portRef O (instanceRef XLXI_9_XLXI_43))
+ )
+ )
+ (net (rename XLXI_9_XLXN_156 "XLXI_9/XLXN_156")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_52))
+ (portRef I (instanceRef XLXI_9_XLXI_69))
+ )
+ )
+ (net (rename XLXI_9_XLXN_126 "XLXI_9/XLXN_126")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_49))
+ (portRef I2 (instanceRef XLXI_9_XLXI_52))
+ (portRef I0 (instanceRef XLXI_9_XLXI_53))
+ )
+ )
+ (net (rename XLXI_9_XLXN_93 "XLXI_9/XLXN_93")
+ (joined
+ (portRef I1 (instanceRef XLXI_9_XLXI_41))
+ (portRef O (instanceRef XLXI_9_XLXI_44))
+ )
+ )
+ (net (rename XLXI_9_XLXN_63 "XLXI_9/XLXN_63")
+ (joined
+ (portRef I2 (instanceRef XLXI_9_XLXI_34))
+ (portRef O (instanceRef XLXI_9_XLXI_32))
+ )
+ )
+ (net (rename XLXI_9_XLXN_162 "XLXI_9/XLXN_162")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_60))
+ (portRef I (instanceRef XLXI_9_XLXI_71))
+ )
+ )
+ (net (rename XLXI_9_XLXN_160 "XLXI_9/XLXN_160")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_58))
+ (portRef I (instanceRef XLXI_9_XLXI_70))
+ )
+ )
+ (net (rename XLXI_9_XLXN_151 "XLXI_9/XLXN_151")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_41))
+ (portRef I (instanceRef XLXI_9_XLXI_66))
+ )
+ )
+ (net (rename XLXI_9_XLXN_165 "XLXI_9/XLXN_165")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_72))
+ (portRef I (instanceRef XLXI_9_XLXI_73))
+ )
+ )
+ (net (rename XLXI_9_XLXN_149 "XLXI_9/XLXN_149")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_34))
+ (portRef I (instanceRef XLXI_9_XLXI_65))
+ )
+ )
+ (net (rename XLXI_9_XLXN_155 "XLXI_9/XLXN_155")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_47))
+ (portRef I (instanceRef XLXI_9_XLXI_67))
+ )
+ )
+ (net (rename XLXI_9_D_BAR "XLXI_9/D_BAR")
+ (joined
+ (portRef I0 (instanceRef XLXI_9_XLXI_64))
+ (portRef I0 (instanceRef XLXI_9_XLXI_56))
+ (portRef I1 (instanceRef XLXI_9_XLXI_33))
+ (portRef I0 (instanceRef XLXI_9_XLXI_48))
+ (portRef I0 (instanceRef XLXI_9_XLXI_62))
+ (portRef O (instanceRef XLXI_9_XLXI_40))
+ (portRef I1 (instanceRef XLXI_9_XLXI_32))
+ (portRef I0 (instanceRef XLXI_9_XLXI_49))
+ (portRef I0 (instanceRef XLXI_9_XLXI_43))
+ (portRef I0 (instanceRef XLXI_9_XLXI_57))
+ )
+ )
+ (net (rename XLXI_9_XLXN_147 "XLXI_9/XLXN_147")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_63))
+ (portRef I1 (instanceRef XLXI_9_XLXI_60))
+ )
+ )
+ (net (rename XLXI_9_XLXN_146 "XLXI_9/XLXN_146")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_62))
+ (portRef I2 (instanceRef XLXI_9_XLXI_60))
+ )
+ )
+ (net (rename XLXI_9_XLXN_113 "XLXI_9/XLXN_113")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_50))
+ (portRef I1 (instanceRef XLXI_9_XLXI_52))
+ )
+ )
+ (net (rename XLXI_9_XLXN_125 "XLXI_9/XLXN_125")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_48))
+ (portRef I3 (instanceRef XLXI_9_XLXI_52))
+ (portRef I1 (instanceRef XLXI_9_XLXI_53))
+ )
+ )
+ (net (rename XLXI_9_XLXN_94 "XLXI_9/XLXN_94")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_45))
+ (portRef I0 (instanceRef XLXI_9_XLXI_41))
+ )
+ )
+ (net (rename XLXI_9_C_BAR "XLXI_9/C_BAR")
+ (joined
+ (portRef I1 (instanceRef XLXI_9_XLXI_30))
+ (portRef I0 (instanceRef XLXI_9_XLXI_51))
+ (portRef I0 (instanceRef XLXI_9_XLXI_54))
+ (portRef I0 (instanceRef XLXI_9_XLXI_61))
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+ (portRef I1 (instanceRef XLXI_9_XLXI_47))
+ (portRef I1 (instanceRef XLXI_9_XLXI_44))
+ (portRef I1 (instanceRef XLXI_9_XLXI_43))
+ (portRef I1 (instanceRef XLXI_9_XLXI_57))
+ )
+ )
+ (net (rename XLXI_9_XLXN_64 "XLXI_9/XLXN_64")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_33))
+ (portRef I1 (instanceRef XLXI_9_XLXI_34))
+ )
+ )
+ (net (rename XLXI_9_XLXN_62 "XLXI_9/XLXN_62")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_31))
+ (portRef I3 (instanceRef XLXI_9_XLXI_34))
+ )
+ )
+ (net (rename XLXI_9_XLXN_145 "XLXI_9/XLXN_145")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_61))
+ (portRef I3 (instanceRef XLXI_9_XLXI_60))
+ )
+ )
+ (net (rename XLXI_9_XLXN_130 "XLXI_9/XLXN_130")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_56))
+ (portRef I1 (instanceRef XLXI_9_XLXI_58))
+ )
+ )
+ (net (rename XLXI_9_XLXN_128 "XLXI_9/XLXN_128")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_54))
+ (portRef I3 (instanceRef XLXI_9_XLXI_58))
+ )
+ )
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+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_51))
+ (portRef I0 (instanceRef XLXI_9_XLXI_52))
+ )
+ )
+ (net (rename XLXI_9_B_BAR "XLXI_9/B_BAR")
+ (joined
+ (portRef I0 (instanceRef XLXI_9_XLXI_35))
+ (portRef I1 (instanceRef XLXI_9_XLXI_55))
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+ (portRef I1 (instanceRef XLXI_9_XLXI_50))
+ (portRef I0 (instanceRef XLXI_9_XLXI_63))
+ (portRef I0 (instanceRef XLXI_9_XLXI_32))
+ (portRef I0 (instanceRef XLXI_9_XLXI_44))
+ (portRef I1 (instanceRef XLXI_9_XLXI_49))
+ )
+ )
+ (net (rename XLXI_9_XLXN_61 "XLXI_9/XLXN_61")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_30))
+ (portRef I4 (instanceRef XLXI_9_XLXI_34))
+ )
+ )
+ (net (rename XLXI_9_XLXN_148 "XLXI_9/XLXN_148")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_64))
+ (portRef I0 (instanceRef XLXI_9_XLXI_60))
+ )
+ )
+ (net (rename XLXI_9_XLXN_129 "XLXI_9/XLXN_129")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_55))
+ (portRef I2 (instanceRef XLXI_9_XLXI_58))
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+ )
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+ (joined
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+ (portRef I2 (instanceRef XLXI_9_XLXI_47))
+ )
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+ (joined
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+ (portRef I3 (instanceRef XLXI_9_XLXI_41))
+ )
+ )
+ (net (rename XLXI_9_A_BAR "XLXI_9/A_BAR")
+ (joined
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+ (portRef I2 (instanceRef XLXI_9_XLXI_54))
+ (portRef I2 (instanceRef XLXI_9_XLXI_56))
+ (portRef I0 (instanceRef XLXI_9_XLXI_31))
+ (portRef I0 (instanceRef XLXI_9_XLXI_45))
+ (portRef I (instanceRef XLXI_9_XLXI_72))
+ )
+ )
+ (net (rename XLXI_9_XLXN_65 "XLXI_9/XLXN_65")
+ (joined
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+ (net A
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+ (net B
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+ (portRef B)
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+ (net C
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+ (portRef C)
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+ (net D
+ (joined
+ (portRef D)
+ (portRef I (instanceRef D_IBUF_renamed_3))
+ )
+ )
+ (net S0
+ (joined
+ (portRef S0)
+ (portRef I (instanceRef S0_IBUF_renamed_4))
+ )
+ )
+ (net S1
+ (joined
+ (portRef S1)
+ (portRef I (instanceRef S1_IBUF_renamed_5))
+ )
+ )
+ (net AN0
+ (joined
+ (portRef AN0)
+ (portRef O (instanceRef AN0_OBUF_renamed_6))
+ )
+ )
+ (net AN1
+ (joined
+ (portRef AN1)
+ (portRef O (instanceRef AN1_OBUF_renamed_7))
+ )
+ )
+ (net AN2
+ (joined
+ (portRef AN2)
+ (portRef O (instanceRef AN2_OBUF_renamed_8))
+ )
+ )
+ (net AN3
+ (joined
+ (portRef AN3)
+ (portRef O (instanceRef AN3_OBUF_renamed_9))
+ )
+ )
+ (net a_out
+ (joined
+ (portRef a_out)
+ (portRef O (instanceRef a_out_OBUF_renamed_10))
+ )
+ )
+ (net b_out
+ (joined
+ (portRef b_out)
+ (portRef O (instanceRef b_out_OBUF_renamed_11))
+ )
+ )
+ (net c_out
+ (joined
+ (portRef c_out)
+ (portRef O (instanceRef c_out_OBUF_renamed_12))
+ )
+ )
+ (net d_out
+ (joined
+ (portRef d_out)
+ (portRef O (instanceRef d_out_OBUF_renamed_13))
+ )
+ )
+ (net e_out
+ (joined
+ (portRef e_out)
+ (portRef O (instanceRef e_out_OBUF_renamed_14))
+ )
+ )
+ (net f_out
+ (joined
+ (portRef f_out)
+ (portRef O (instanceRef f_out_OBUF_renamed_15))
+ )
+ )
+ (net g_out
+ (joined
+ (portRef g_out)
+ (portRef O (instanceRef g_out_OBUF_renamed_16))
+ )
+ )
+ (net sign
+ (joined
+ (portRef sign)
+ (portRef O (instanceRef sign_OBUF_renamed_17))
+ )
+ )
+ )
+ )
+ )
+ )
+
+ (design ALU
+ (cellRef ALU
+ (libraryRef ALU_lib)
+ )
+ (property PART (string "xc6slx16-3-csg324") (owner "Xilinx"))
+ )
+)
+
diff --git a/planAhead_run_1/lab1.data/constrs_1/designprops.xml b/planAhead_run_1/lab1.data/constrs_1/designprops.xml
new file mode 100755
index 0000000..ae00c39
--- /dev/null
+++ b/planAhead_run_1/lab1.data/constrs_1/designprops.xml
@@ -0,0 +1,29 @@
+<?xml version="1.0"?>
+<Compat Version="1" Minor="4">
+ <CompatParts>
+ </CompatParts>
+ <ConfigModes>
+ <Mode Id="JTAG"/>
+ </ConfigModes>
+ <PortProps>
+ <Port Name="A" OffChipTerm="NONE"/>
+ <Port Name="B" OffChipTerm="NONE"/>
+ <Port Name="C" OffChipTerm="NONE"/>
+ <Port Name="D" OffChipTerm="NONE"/>
+ <Port Name="S0" OffChipTerm="NONE"/>
+ <Port Name="S1" OffChipTerm="NONE"/>
+ <Port Name="AN0" OffChipTerm="FP_VTT_50"/>
+ <Port Name="AN1" OffChipTerm="FP_VTT_50"/>
+ <Port Name="AN2" OffChipTerm="FP_VTT_50"/>
+ <Port Name="AN3" OffChipTerm="FP_VTT_50"/>
+ <Port Name="a_out" OffChipTerm="FP_VTT_50"/>
+ <Port Name="b_out" OffChipTerm="FP_VTT_50"/>
+ <Port Name="c_out" OffChipTerm="FP_VTT_50"/>
+ <Port Name="d_out" OffChipTerm="FP_VTT_50"/>
+ <Port Name="e_out" OffChipTerm="FP_VTT_50"/>
+ <Port Name="f_out" OffChipTerm="FP_VTT_50"/>
+ <Port Name="g_out" OffChipTerm="FP_VTT_50"/>
+ <Port Name="sign" OffChipTerm="FP_VTT_50"/>
+ </PortProps>
+</Compat>
+
diff --git a/planAhead_run_1/lab1.data/constrs_1/fileset.xml b/planAhead_run_1/lab1.data/constrs_1/fileset.xml
index 80984cf..6fa147b 100755
--- a/planAhead_run_1/lab1.data/constrs_1/fileset.xml
+++ b/planAhead_run_1/lab1.data/constrs_1/fileset.xml
@@ -15,6 +15,26 @@
Val="1"/>
</FileInfo>
</File>
+ <File Path="$PDATADIR/constrs_1/designprops.xml">
+ <FileInfo SFType="CompatPartsDb">
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <File Path="$PDATADIR/constrs_1/usercols.xml">
+ <FileInfo SFType="UserColsDb">
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="TargetConstrsFile"
Val="$PPRDIR/../ALU.ucf"/>
diff --git a/planAhead_run_1/lab1.data/constrs_1/usercols.xml b/planAhead_run_1/lab1.data/constrs_1/usercols.xml
new file mode 100755
index 0000000..b2e369a
--- /dev/null
+++ b/planAhead_run_1/lab1.data/constrs_1/usercols.xml
@@ -0,0 +1,4 @@
+<?xml version="1.0"?>
+<UserColInfo Version="1" Minor="0">
+</UserColInfo>
+
diff --git a/planAhead_run_1/lab1.data/runs/impl_1.psg b/planAhead_run_1/lab1.data/runs/impl_1.psg
new file mode 100755
index 0000000..43196a2
--- /dev/null
+++ b/planAhead_run_1/lab1.data/runs/impl_1.psg
@@ -0,0 +1,18 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+ <StratHandle Name="ISE Defaults" Flow="ISE13">
+ <Desc>ISE Defaults, including packing registers in IOs off</Desc>
+ </StratHandle>
+ <Step Id="ngdbuild">
+ </Step>
+ <Step Id="map">
+ <Option Id="FFPackEnum">3</Option>
+ </Step>
+ <Step Id="par">
+ </Step>
+ <Step Id="trce">
+ </Step>
+ <Step Id="xdl">
+ </Step>
+</Strategy>
+
diff --git a/planAhead_run_1/lab1.data/runs/runs.xml b/planAhead_run_1/lab1.data/runs/runs.xml
new file mode 100755
index 0000000..2651a01
--- /dev/null
+++ b/planAhead_run_1/lab1.data/runs/runs.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="8">
+ <Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc6slx16csg324-3" ConstrsSet="constrs_1" State="current"/>
+</Runs>
+
diff --git a/planAhead_run_1/lab1.data/sources_1/chipscope.xml b/planAhead_run_1/lab1.data/sources_1/chipscope.xml
new file mode 100755
index 0000000..af5cfeb
--- /dev/null
+++ b/planAhead_run_1/lab1.data/sources_1/chipscope.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<ChipScope Version="1" Minor="3">
+ <UnassignedNets>
+ </UnassignedNets>
+</ChipScope>
+
diff --git a/planAhead_run_1/lab1.data/sources_1/fileset.xml b/planAhead_run_1/lab1.data/sources_1/fileset.xml
index 8ada118..c8f890f 100755
--- a/planAhead_run_1/lab1.data/sources_1/fileset.xml
+++ b/planAhead_run_1/lab1.data/sources_1/fileset.xml
@@ -4,8 +4,8 @@
<FileSet Name="sources_1"
Type="DesignSrcs"
RelSrcDir="$PSRCDIR/sources_1">
- <Filter Type="Srcs"/>
- <File Path="$PPRDIR/../Negate_2.vf">
+ <Filter Type="EDIFSrcs"/>
+ <File Path="$PPRDIR/../ALU.ngc">
<FileInfo>
<Attr Name="UsedInSynthesis"
Val="1"/>
@@ -15,58 +15,8 @@
Val="1"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../Negate_1.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Negate_0.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Modulo_3.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Modulo_1.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Modulo_0.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Divide_3.vf">
- <FileInfo>
+ <File Path="$PDATADIR/sources_1/ports.xml">
+ <FileInfo SFType="PortsDb">
<Attr Name="UsedInSynthesis"
Val="1"/>
<Attr Name="UsedInImplementation"
@@ -75,88 +25,8 @@
Val="1"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../Divide_2.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Divide_1.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Divide_0.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../sev_seg_disp.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Negate_3.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Modulo.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Divide.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../ALU.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Negate.vf">
- <FileInfo>
+ <File Path="$PDATADIR/sources_1/chipscope.xml">
+ <FileInfo SFType="ChipscopeDb">
<Attr Name="UsedInSynthesis"
Val="1"/>
<Attr Name="UsedInImplementation"
@@ -167,15 +37,13 @@
</File>
<Config>
<Option Name="DesignMode"
- Val="RTL"/>
+ Val="GateLvl"/>
+ <Option Name="GateLvlMode"
+ Val="EDIF"/>
<Option Name="TopModule"
- Val="Negate"/>
- <Option Name="TopLib"
- Val="work"/>
- <Option Name="TopRTLFile"
- Val="$PPRDIR/../Negate.vf"/>
- <Option Name="TopAutoSet"
- Val="TRUE"/>
+ Val="ALU"/>
+ <Option Name="TopFile"
+ Val="$PPRDIR/../ALU.ngc"/>
</Config>
</FileSet>
</DARoots>
diff --git a/planAhead_run_1/lab1.data/sources_1/ports.xml b/planAhead_run_1/lab1.data/sources_1/ports.xml
new file mode 100755
index 0000000..99a5439
--- /dev/null
+++ b/planAhead_run_1/lab1.data/sources_1/ports.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0"?>
+<Interface Version="1" Minor="1">
+ <Ifc Id="ROOT" Top="1">
+ <Port Id="A" Dir="IN"/>
+ <Port Id="B" Dir="IN"/>
+ <Port Id="C" Dir="IN"/>
+ <Port Id="D" Dir="IN"/>
+ <Port Id="S0" Dir="IN"/>
+ <Port Id="S1" Dir="IN"/>
+ <Port Id="AN0" Dir="OUT"/>
+ <Port Id="AN1" Dir="OUT"/>
+ <Port Id="AN2" Dir="OUT"/>
+ <Port Id="AN3" Dir="OUT"/>
+ <Port Id="a_out" Dir="OUT"/>
+ <Port Id="b_out" Dir="OUT"/>
+ <Port Id="c_out" Dir="OUT"/>
+ <Port Id="d_out" Dir="OUT"/>
+ <Port Id="e_out" Dir="OUT"/>
+ <Port Id="f_out" Dir="OUT"/>
+ <Port Id="g_out" Dir="OUT"/>
+ <Port Id="sign" Dir="OUT"/>
+ </Ifc>
+</Interface>
+
diff --git a/planAhead_run_1/lab1.ppr b/planAhead_run_1/lab1.ppr
index 22481f8..6081e20 100755
--- a/planAhead_run_1/lab1.ppr
+++ b/planAhead_run_1/lab1.ppr
@@ -2,6 +2,7 @@
<Project Version="4" Minor="27">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
+ <RunSet Dir="runs" File="runs.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
<Config>
diff --git a/planAhead_run_1/planAhead.jou b/planAhead_run_1/planAhead.jou
index 245a6d0..1ae8ec4 100755
--- a/planAhead_run_1/planAhead.jou
+++ b/planAhead_run_1/planAhead.jou
@@ -1,12 +1,20 @@
#-----------------------------------------------------------
# PlanAhead v13.3 (64-bit)
# Build 147507 by hdbuild on Tue Oct 4 19:13:50 MDT 2011
-# Start of session at: Wed Feb 15 15:13:16 2012
-# Process ID: 3932
-# Log file: X:/My Documents/ec311/lab1/planAhead_run_1/planAhead.log
-# Journal file: X:/My Documents/ec311/lab1/planAhead_run_1/planAhead.jou
+# Start of session at: Thu Feb 16 18:17:07 2012
+# Process ID: 1252
+# Log file: X:/My Documents/ec311/ec311-lab1/planAhead_run_1/planAhead.log
+# Journal file: X:/My Documents/ec311/ec311-lab1/planAhead_run_1/planAhead.jou
#-----------------------------------------------------------
start_gui
-source {X:/My Documents/ec311/lab1/pa.fromHdl.tcl}
-exit
-stop_gui
+source {X:/My Documents/ec311/ec311-lab1/pa.fromNetlist.tcl}
+startgroup
+set_property loc PAD2 [get_ports A]
+endgroup
+startgroup
+set_property loc PAD30 [get_ports D]
+endgroup
+startgroup
+set_property loc PAD29 [get_ports C]
+endgroup
+save_design
diff --git a/planAhead_run_1/planAhead.log b/planAhead_run_1/planAhead.log
index fda2b18..19f24a3 100755
--- a/planAhead_run_1/planAhead.log
+++ b/planAhead_run_1/planAhead.log
@@ -1,83 +1,48 @@
#-----------------------------------------------------------
# PlanAhead v13.3 (64-bit)
# Build 147507 by hdbuild on Tue Oct 4 19:13:50 MDT 2011
-# Start of session at: Wed Feb 15 15:13:16 2012
-# Process ID: 3932
-# Log file: X:/My Documents/ec311/lab1/planAhead_run_1/planAhead.log
-# Journal file: X:/My Documents/ec311/lab1/planAhead_run_1/planAhead.jou
+# Start of session at: Thu Feb 16 18:17:07 2012
+# Process ID: 1252
+# Log file: X:/My Documents/ec311/ec311-lab1/planAhead_run_1/planAhead.log
+# Journal file: X:/My Documents/ec311/ec311-lab1/planAhead_run_1/planAhead.jou
#-----------------------------------------------------------
INFO: [Common-78] Attempting to get a license: PlanAhead
INFO: [Common-82] Got a license: PlanAhead
INFO: [Device-25] Loading parts and site information from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\arch.xmlParsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
Finished parsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
start_gui
-source {X:/My Documents/ec311/lab1/pa.fromHdl.tcl}
-# create_project -name lab1 -dir "X:/My Documents/ec311/lab1/planAhead_run_1" -part xc6slx16csg324-3
+source {X:/My Documents/ec311/ec311-lab1/pa.fromNetlist.tcl}
+# create_project -name lab1 -dir "X:/My Documents/ec311/ec311-lab1/planAhead_run_1" -part xc6slx16csg324-3
Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
-# set_param project.pinAheadLayout yes
-# set srcset [get_property srcset [current_run -impl]]
-# set_property top ALU $srcset
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "X:/My Documents/ec311/ec311-lab1/ALU.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {X:/My Documents/ec311/ec311-lab1} }
+# set_param project.pinAheadLayout yes
# set_property target_constrs_file "ALU.ucf" [current_fileset -constrset]
-Adding file 'X:\My Documents\ec311\lab1\ALU.ucf' to fileset 'constrs_1'
-CRITICAL WARNING: [Designutils-735] The top module "ALU" specified for this project can not be validated. The current project is using automatic hierarchy update mode, and hence a new suitable replacement top will be automatically selected. If this is not desired, please change the hierarchy update mode to one of the manual compile order modes first, and then set top to any desired value.
-# set hdlfile [add_files [list {Negate_3.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate_2.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate_1.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate_0.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo_3.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo_1.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo_0.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_3.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_2.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_1.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_0.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {sev_seg_disp.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {ALU.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
+Adding file 'X:\My Documents\ec311\ec311-lab1\ALU.ucf' to fileset 'constrs_1'
# add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]]
-# open_rtl_design -part xc6slx16csg324-3
-INFO: [PlanAhead-58] Using Verific elaboration
-Parsing VHDL file "C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify
-Analyzing Verilog file "X:\My Documents\ec311\lab1\Negate.vf" into library work
+# open_netlist_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to part: xc6slx16csg324-3
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91624 kilobytes
+
+Parsing EDIF File [.\planAhead_run_1\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_1\lab1.data\cache\ALU_ngc_c04f956c.edif]
Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
@@ -85,30 +50,26 @@ Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spart
Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
Loading device configuration modes from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/ConfigModes.xml
Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
-Parsing UCF File [X:\My Documents\ec311\lab1\ALU.ucf]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'A' [X:\My Documents\ec311\lab1\ALU.ucf:4]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'AN0' [X:\My Documents\ec311\lab1\ALU.ucf:5]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'AN1' [X:\My Documents\ec311\lab1\ALU.ucf:6]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'AN2' [X:\My Documents\ec311\lab1\ALU.ucf:7]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'AN3' [X:\My Documents\ec311\lab1\ALU.ucf:8]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'B' [X:\My Documents\ec311\lab1\ALU.ucf:9]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'C' [X:\My Documents\ec311\lab1\ALU.ucf:10]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'D' [X:\My Documents\ec311\lab1\ALU.ucf:11]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'S0' [X:\My Documents\ec311\lab1\ALU.ucf:12]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'S1' [X:\My Documents\ec311\lab1\ALU.ucf:13]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'a_out' [X:\My Documents\ec311\lab1\ALU.ucf:14]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'b_out' [X:\My Documents\ec311\lab1\ALU.ucf:15]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'c_out' [X:\My Documents\ec311\lab1\ALU.ucf:16]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'd_out' [X:\My Documents\ec311\lab1\ALU.ucf:17]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'e_out' [X:\My Documents\ec311\lab1\ALU.ucf:18]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'f_out' [X:\My Documents\ec311\lab1\ALU.ucf:19]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'g_out' [X:\My Documents\ec311\lab1\ALU.ucf:20]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'sign' [X:\My Documents\ec311\lab1\ALU.ucf:21]
-Finished Parsing UCF File [X:\My Documents\ec311\lab1\ALU.ucf]
-INFO: [Designutils-20] Invalid constraints found, use command 'write_ucf -constraints invalid <file>' to save all the invalid constraints to a file
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
INFO: [PlanAhead-566] Unisim Transformation Summary:
-No Unisim elements were transformed.open_rtl_design: Time (s): 13.288w. Memory (MB): 788.289p 223.703g
-exit
-stop_gui
-INFO: [PlanAhead-261] Exiting PlanAhead...
-INFO: [Common-83] Releasing license: PlanAhead
+No Unisim elements were transformed.open_netlist_design: Time (s): 13.291w. Memory (MB): 734.672p 186.648g
+startgroup
+startgroup
+set_property loc PAD2 [get_ports A]
+set_property loc PAD2 [get_ports A]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD30 [get_ports D]
+set_property loc PAD30 [get_ports D]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD29 [get_ports C]
+set_property loc PAD29 [get_ports C]
+endgroup
+endgroup
+save_design
diff --git a/planAhead_run_1/planAhead_run.log b/planAhead_run_1/planAhead_run.log
index bae2bd8..9d4c5fa 100755
--- a/planAhead_run_1/planAhead_run.log
+++ b/planAhead_run_1/planAhead_run.log
@@ -9,72 +9,38 @@ INFO: [Device-25] Loading parts and site information from C:/Xilinx/13.3/ISE_DS/
Finished parsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
start_gui
starting gui ...
-source {X:/My Documents/ec311/lab1/pa.fromHdl.tcl}
-# create_project -name lab1 -dir "X:/My Documents/ec311/lab1/planAhead_run_1" -part xc6slx16csg324-3
+source {X:/My Documents/ec311/ec311-lab1/pa.fromNetlist.tcl}
+# create_project -name lab1 -dir "X:/My Documents/ec311/ec311-lab1/planAhead_run_1" -part xc6slx16csg324-3
Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
-# set_param project.pinAheadLayout yes
-# set srcset [get_property srcset [current_run -impl]]
-# set_property top ALU $srcset
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "X:/My Documents/ec311/ec311-lab1/ALU.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {X:/My Documents/ec311/ec311-lab1} }
+# set_param project.pinAheadLayout yes
# set_property target_constrs_file "ALU.ucf" [current_fileset -constrset]
-Adding file 'X:\My Documents\ec311\lab1\ALU.ucf' to fileset 'constrs_1'
-# set hdlfile [add_files [list {Negate_3.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate_2.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate_1.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate_0.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo_3.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo_1.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo_0.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_3.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_2.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_1.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_0.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {sev_seg_disp.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {ALU.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
+Adding file 'X:\My Documents\ec311\ec311-lab1\ALU.ucf' to fileset 'constrs_1'
# add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]]
-# open_rtl_design -part xc6slx16csg324-3
-INFO: [PlanAhead-58] Using Verific elaboration
-Parsing VHDL file "C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify
-Analyzing Verilog file "X:\My Documents\ec311\lab1\Negate.vf" into library work
+# open_netlist_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to part: xc6slx16csg324-3
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91624 kilobytes
+
+Parsing EDIF File [.\planAhead_run_1\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_1\lab1.data\cache\ALU_ngc_c04f956c.edif]
Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
@@ -82,12 +48,26 @@ Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spart
Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
Loading device configuration modes from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/ConfigModes.xml
Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
-Parsing UCF File [X:\My Documents\ec311\lab1\ALU.ucf]
-Finished Parsing UCF File [X:\My Documents\ec311\lab1\ALU.ucf]
-INFO: [Designutils-20] Invalid constraints found, use command 'write_ucf -constraints invalid <file>' to save all the invalid constraints to a file
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
INFO: [PlanAhead-566] Unisim Transformation Summary:
-No Unisim elements were transformed.open_rtl_design: Time (s): 13.288w. Memory (MB): 788.289p 223.703g
-exit
-stop_gui
-INFO: [PlanAhead-261] Exiting PlanAhead...
-INFO: [Common-83] Releasing license: PlanAhead
+No Unisim elements were transformed.open_netlist_design: Time (s): 13.291w. Memory (MB): 734.672p 186.648g
+startgroup
+startgroup
+set_property loc PAD2 [get_ports A]
+set_property loc PAD2 [get_ports A]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD30 [get_ports D]
+set_property loc PAD30 [get_ports D]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD29 [get_ports C]
+set_property loc PAD29 [get_ports C]
+endgroup
+endgroup
+save_design
diff --git a/planAhead_run_2/lab1.data/cache/ALU_ngc_c04f956c.edif b/planAhead_run_2/lab1.data/cache/ALU_ngc_c04f956c.edif
new file mode 100755
index 0000000..b8c1e02
--- /dev/null
+++ b/planAhead_run_2/lab1.data/cache/ALU_ngc_c04f956c.edif
@@ -0,0 +1,2476 @@
+(edif ALU
+ (edifVersion 2 0 0)
+ (edifLevel 0)
+ (keywordMap (keywordLevel 0))
+ (status
+ (written
+ (timestamp 2012 2 16 19 53 2)
+ (program "Xilinx ngc2edif" (version "O.76xd"))
+ (author "Xilinx. Inc ")
+ (comment "This EDIF netlist is to be used within supported synthesis tools")
+ (comment "for determining resource/timing estimates of the design component")
+ (comment "represented by this netlist.")
+ (comment "Command line: -mdp2sp -w -secure ALU.ngc ALU.edif ")))
+ (external UNISIMS
+ (edifLevel 0)
+ (technology (numberDefinition))
+ (cell GND
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port G
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell VCC
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port P
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell OR3
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell OR2
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell INV
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell AND2
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell AND4
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port I3
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell AND3
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell OR5
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port I3
+ (direction INPUT)
+ )
+ (port I4
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell OR4
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port I3
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell LUT6
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port I3
+ (direction INPUT)
+ )
+ (port I4
+ (direction INPUT)
+ )
+ (port I5
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell BUF
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell XOR2
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell XNOR2
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell IBUF
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell OBUF
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ )
+
+ (library ALU_lib
+ (edifLevel 0)
+ (technology (numberDefinition))
+ (cell (rename M4_1E_HXILINX_ALU_NO3_XLXI_4 "M4_1E_HXILINX_ALU")
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port D0
+ (direction INPUT)
+ )
+ (port D1
+ (direction INPUT)
+ )
+ (port D2
+ (direction INPUT)
+ )
+ (port D3
+ (direction INPUT)
+ )
+ (port E
+ (direction INPUT)
+ )
+ (port S0
+ (direction INPUT)
+ )
+ (port S1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ (contents
+ (instance Mmux_O11
+ (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx"))
+ )
+ (net D0
+ (joined
+ (portRef D0)
+ (portRef I4 (instanceRef Mmux_O11))
+ )
+ )
+ (net D1
+ (joined
+ (portRef D1)
+ (portRef I3 (instanceRef Mmux_O11))
+ )
+ )
+ (net D2
+ (joined
+ (portRef D2)
+ (portRef I5 (instanceRef Mmux_O11))
+ )
+ )
+ (net D3
+ (joined
+ (portRef D3)
+ (portRef I1 (instanceRef Mmux_O11))
+ )
+ )
+ (net S0
+ (joined
+ (portRef S0)
+ (portRef I0 (instanceRef Mmux_O11))
+ )
+ )
+ (net S1
+ (joined
+ (portRef S1)
+ (portRef I2 (instanceRef Mmux_O11))
+ )
+ )
+ (net O
+ (joined
+ (portRef O)
+ (portRef O (instanceRef Mmux_O11))
+ )
+ )
+ )
+ )
+ )
+ (cell (rename M4_1E_HXILINX_ALU_NO2_XLXI_5 "M4_1E_HXILINX_ALU")
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port D0
+ (direction INPUT)
+ )
+ (port D1
+ (direction INPUT)
+ )
+ (port D2
+ (direction INPUT)
+ )
+ (port D3
+ (direction INPUT)
+ )
+ (port E
+ (direction INPUT)
+ )
+ (port S0
+ (direction INPUT)
+ )
+ (port S1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ (contents
+ (instance Mmux_O11
+ (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx"))
+ )
+ (net D0
+ (joined
+ (portRef D0)
+ (portRef I4 (instanceRef Mmux_O11))
+ )
+ )
+ (net D1
+ (joined
+ (portRef D1)
+ (portRef I3 (instanceRef Mmux_O11))
+ )
+ )
+ (net D2
+ (joined
+ (portRef D2)
+ (portRef I5 (instanceRef Mmux_O11))
+ )
+ )
+ (net D3
+ (joined
+ (portRef D3)
+ (portRef I1 (instanceRef Mmux_O11))
+ )
+ )
+ (net S0
+ (joined
+ (portRef S0)
+ (portRef I0 (instanceRef Mmux_O11))
+ )
+ )
+ (net S1
+ (joined
+ (portRef S1)
+ (portRef I2 (instanceRef Mmux_O11))
+ )
+ )
+ (net O
+ (joined
+ (portRef O)
+ (portRef O (instanceRef Mmux_O11))
+ )
+ )
+ )
+ )
+ )
+ (cell (rename M4_1E_HXILINX_ALU_NO1_XLXI_6 "M4_1E_HXILINX_ALU")
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port D0
+ (direction INPUT)
+ )
+ (port D1
+ (direction INPUT)
+ )
+ (port D2
+ (direction INPUT)
+ )
+ (port D3
+ (direction INPUT)
+ )
+ (port E
+ (direction INPUT)
+ )
+ (port S0
+ (direction INPUT)
+ )
+ (port S1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ (contents
+ (instance Mmux_O11
+ (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx"))
+ )
+ (net D0
+ (joined
+ (portRef D0)
+ (portRef I4 (instanceRef Mmux_O11))
+ )
+ )
+ (net D1
+ (joined
+ (portRef D1)
+ (portRef I3 (instanceRef Mmux_O11))
+ )
+ )
+ (net D2
+ (joined
+ (portRef D2)
+ (portRef I5 (instanceRef Mmux_O11))
+ )
+ )
+ (net D3
+ (joined
+ (portRef D3)
+ (portRef I1 (instanceRef Mmux_O11))
+ )
+ )
+ (net S0
+ (joined
+ (portRef S0)
+ (portRef I0 (instanceRef Mmux_O11))
+ )
+ )
+ (net S1
+ (joined
+ (portRef S1)
+ (portRef I2 (instanceRef Mmux_O11))
+ )
+ )
+ (net O
+ (joined
+ (portRef O)
+ (portRef O (instanceRef Mmux_O11))
+ )
+ )
+ )
+ )
+ )
+ (cell (rename M4_1E_HXILINX_ALU_XLXI_7 "M4_1E_HXILINX_ALU")
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port D0
+ (direction INPUT)
+ )
+ (port D1
+ (direction INPUT)
+ )
+ (port D2
+ (direction INPUT)
+ )
+ (port D3
+ (direction INPUT)
+ )
+ (port E
+ (direction INPUT)
+ )
+ (port S0
+ (direction INPUT)
+ )
+ (port S1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ (contents
+ (instance Mmux_O11
+ (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx"))
+ )
+ (net D0
+ (joined
+ (portRef D0)
+ (portRef I4 (instanceRef Mmux_O11))
+ )
+ )
+ (net D1
+ (joined
+ (portRef D1)
+ (portRef I3 (instanceRef Mmux_O11))
+ )
+ )
+ (net D2
+ (joined
+ (portRef D2)
+ (portRef I5 (instanceRef Mmux_O11))
+ )
+ )
+ (net D3
+ (joined
+ (portRef D3)
+ (portRef I1 (instanceRef Mmux_O11))
+ )
+ )
+ (net S0
+ (joined
+ (portRef S0)
+ (portRef I0 (instanceRef Mmux_O11))
+ )
+ )
+ (net S1
+ (joined
+ (portRef S1)
+ (portRef I2 (instanceRef Mmux_O11))
+ )
+ )
+ (net O
+ (joined
+ (portRef O)
+ (portRef O (instanceRef Mmux_O11))
+ )
+ )
+ )
+ )
+ )
+ (cell ALU
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port A
+ (direction INPUT)
+ )
+ (port B
+ (direction INPUT)
+ )
+ (port C
+ (direction INPUT)
+ )
+ (port D
+ (direction INPUT)
+ )
+ (port S0
+ (direction INPUT)
+ )
+ (port S1
+ (direction INPUT)
+ )
+ (port AN0
+ (direction OUTPUT)
+ )
+ (port AN1
+ (direction OUTPUT)
+ )
+ (port AN2
+ (direction OUTPUT)
+ )
+ (port AN3
+ (direction OUTPUT)
+ )
+ (port a_out
+ (direction OUTPUT)
+ )
+ (port b_out
+ (direction OUTPUT)
+ )
+ (port c_out
+ (direction OUTPUT)
+ )
+ (port d_out
+ (direction OUTPUT)
+ )
+ (port e_out
+ (direction OUTPUT)
+ )
+ (port f_out
+ (direction OUTPUT)
+ )
+ (port g_out
+ (direction OUTPUT)
+ )
+ (port sign
+ (direction OUTPUT)
+ )
+ (designator "xc6slx16-3-csg324")
+ (property TYPE (string "ALU") (owner "Xilinx"))
+ (property SHREG_MIN_SIZE (string "2") (owner "Xilinx"))
+ (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx"))
+ (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
+ (property NLW_MACRO_TAG (integer 0) (owner "Xilinx"))
+ (property NLW_MACRO_ALIAS (string "ALU_ALU") (owner "Xilinx"))
+ )
+ (contents
+ (instance XST_GND
+ (viewRef view_1 (cellRef GND (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance XLXI_8
+ (viewRef view_1 (cellRef VCC (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_2 "XLXI_1/XLXI_8/XLXI_2")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_5 "XLXI_1/XLXI_8/XLXI_5")
+ (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_7 "XLXI_1/XLXI_8/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_6 "XLXI_1/XLXI_8/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_4 "XLXI_1/XLXI_8/XLXI_4")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_8 "XLXI_1/XLXI_8/XLXI_8")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_3 "XLXI_1/XLXI_8/XLXI_3")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_9 "XLXI_1/XLXI_8/XLXI_9")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_1 "XLXI_1/XLXI_8/XLXI_1")
+ (viewRef view_1 (cellRef AND4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_9_XLXI_12 "XLXI_1/XLXI_9/XLXI_12")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_9_XLXI_10 "XLXI_1/XLXI_9/XLXI_10")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_9_XLXI_16 "XLXI_1/XLXI_9/XLXI_16")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_9_XLXI_15 "XLXI_1/XLXI_9/XLXI_15")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_9_XLXI_13 "XLXI_1/XLXI_9/XLXI_13")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_10_XLXI_4 "XLXI_1/XLXI_10/XLXI_4")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_10_XLXI_2 "XLXI_1/XLXI_10/XLXI_2")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_10_XLXI_6 "XLXI_1/XLXI_10/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_10_XLXI_7 "XLXI_1/XLXI_10/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_10_XLXI_8 "XLXI_1/XLXI_10/XLXI_8")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_7 "XLXI_1/XLXI_12/XLXI_7")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_9 "XLXI_1/XLXI_12/XLXI_9")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_5 "XLXI_1/XLXI_12/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_3 "XLXI_1/XLXI_12/XLXI_3")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_2 "XLXI_1/XLXI_12/XLXI_2")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_6 "XLXI_1/XLXI_12/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_1 "XLXI_1/XLXI_12/XLXI_1")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_4 "XLXI_2/XLXI_2/XLXI_4")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_2 "XLXI_2/XLXI_2/XLXI_2")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_7 "XLXI_2/XLXI_2/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_5 "XLXI_2/XLXI_2/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_1 "XLXI_2/XLXI_2/XLXI_1")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_6 "XLXI_2/XLXI_2/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_3 "XLXI_2/XLXI_2/XLXI_3")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_4 "XLXI_2/XLXI_1/XLXI_4")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_2 "XLXI_2/XLXI_1/XLXI_2")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_7 "XLXI_2/XLXI_1/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_5 "XLXI_2/XLXI_1/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_1 "XLXI_2/XLXI_1/XLXI_1")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_6 "XLXI_2/XLXI_1/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_3 "XLXI_2/XLXI_1/XLXI_3")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_22 "XLXI_2/XLXI_3/XLXI_22")
+ (viewRef view_1 (cellRef OR5 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_20 "XLXI_2/XLXI_3/XLXI_20")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_15 "XLXI_2/XLXI_3/XLXI_15")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_2 "XLXI_2/XLXI_3/XLXI_2")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_19 "XLXI_2/XLXI_3/XLXI_19")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_7 "XLXI_2/XLXI_3/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_18 "XLXI_2/XLXI_3/XLXI_18")
+ (viewRef view_1 (cellRef AND4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_16 "XLXI_2/XLXI_3/XLXI_16")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_5 "XLXI_2/XLXI_3/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_1 "XLXI_2/XLXI_3/XLXI_1")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_21 "XLXI_2/XLXI_3/XLXI_21")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_11 "XLXI_2/XLXI_3/XLXI_11")
+ (viewRef view_1 (cellRef AND4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_6 "XLXI_2/XLXI_3/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_3 "XLXI_2/XLXI_3/XLXI_3")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_8_XLXI_8 "XLXI_3/XLXI_8/XLXI_8")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_8_XLXI_10 "XLXI_3/XLXI_8/XLXI_10")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_8_XLXI_9 "XLXI_3/XLXI_8/XLXI_9")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_8_XLXI_12 "XLXI_3/XLXI_8/XLXI_12")
+ (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_4 "XLXI_3/XLXI_9/XLXI_4")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_3 "XLXI_3/XLXI_9/XLXI_3")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_5 "XLXI_3/XLXI_9/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_6 "XLXI_3/XLXI_9/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_1 "XLXI_3/XLXI_9/XLXI_1")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_7 "XLXI_3/XLXI_9/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_2 "XLXI_3/XLXI_9/XLXI_2")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_8 "XLXI_3/XLXI_10/XLXI_8")
+ (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_9 "XLXI_3/XLXI_10/XLXI_9")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_15 "XLXI_3/XLXI_10/XLXI_15")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_14 "XLXI_3/XLXI_10/XLXI_14")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_16 "XLXI_3/XLXI_10/XLXI_16")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_10 "XLXI_3/XLXI_10/XLXI_10")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_17 "XLXI_3/XLXI_10/XLXI_17")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_11 "XLXI_3/XLXI_10/XLXI_11")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_12_XLXI_16 "XLXI_3/XLXI_12/XLXI_16")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_12_XLXI_15 "XLXI_3/XLXI_12/XLXI_15")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_12_XLXI_14 "XLXI_3/XLXI_12/XLXI_14")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_14 "XLXI_2/XLXI_4/XLXI_14")
+ (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_4 "XLXI_2/XLXI_4/XLXI_4")
+ (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_16 "XLXI_2/XLXI_4/XLXI_16")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_12 "XLXI_2/XLXI_4/XLXI_12")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_2 "XLXI_2/XLXI_4/XLXI_2")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_13 "XLXI_2/XLXI_4/XLXI_13")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_9 "XLXI_2/XLXI_4/XLXI_9")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_15 "XLXI_2/XLXI_4/XLXI_15")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_11 "XLXI_2/XLXI_4/XLXI_11")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_10 "XLXI_2/XLXI_4/XLXI_10")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance XLXI_7
+ (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_XLXI_7 (libraryRef ALU_lib)))
+ (property HU_SET (string "XLXI_7_3") (owner "Xilinx"))
+ (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
+ (property NLW_MACRO_TAG (integer 1) (owner "Xilinx"))
+ (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_XLXI_7") (owner "Xilinx"))
+ )
+ (instance XLXI_6
+ (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_NO1_XLXI_6 (libraryRef ALU_lib)))
+ (property HU_SET (string "XLXI_6_2") (owner "Xilinx"))
+ (property NLW_UNIQUE_ID (integer 1) (owner "Xilinx"))
+ (property NLW_MACRO_TAG (integer 2) (owner "Xilinx"))
+ (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_NO1_XLXI_6") (owner "Xilinx"))
+ )
+ (instance XLXI_5
+ (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_NO2_XLXI_5 (libraryRef ALU_lib)))
+ (property HU_SET (string "XLXI_5_1") (owner "Xilinx"))
+ (property NLW_UNIQUE_ID (integer 2) (owner "Xilinx"))
+ (property NLW_MACRO_TAG (integer 3) (owner "Xilinx"))
+ (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_NO2_XLXI_5") (owner "Xilinx"))
+ )
+ (instance XLXI_4
+ (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_NO3_XLXI_4 (libraryRef ALU_lib)))
+ (property HU_SET (string "XLXI_4_0") (owner "Xilinx"))
+ (property NLW_UNIQUE_ID (integer 3) (owner "Xilinx"))
+ (property NLW_MACRO_TAG (integer 4) (owner "Xilinx"))
+ (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_NO3_XLXI_4") (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_8 "XLXI_9/XLXI_8")
+ (viewRef view_1 (cellRef BUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_7 "XLXI_9/XLXI_7")
+ (viewRef view_1 (cellRef BUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_6 "XLXI_9/XLXI_6")
+ (viewRef view_1 (cellRef BUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_5 "XLXI_9/XLXI_5")
+ (viewRef view_1 (cellRef BUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_68 "XLXI_9/XLXI_68")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_69 "XLXI_9/XLXI_69")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_71 "XLXI_9/XLXI_71")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_70 "XLXI_9/XLXI_70")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_66 "XLXI_9/XLXI_66")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_73 "XLXI_9/XLXI_73")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_65 "XLXI_9/XLXI_65")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_67 "XLXI_9/XLXI_67")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_53 "XLXI_9/XLXI_53")
+ (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_57 "XLXI_9/XLXI_57")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_43 "XLXI_9/XLXI_43")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_52 "XLXI_9/XLXI_52")
+ (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_49 "XLXI_9/XLXI_49")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_44 "XLXI_9/XLXI_44")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_32 "XLXI_9/XLXI_32")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_60 "XLXI_9/XLXI_60")
+ (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_58 "XLXI_9/XLXI_58")
+ (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_41 "XLXI_9/XLXI_41")
+ (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_72 "XLXI_9/XLXI_72")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_34 "XLXI_9/XLXI_34")
+ (viewRef view_1 (cellRef OR5 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_47 "XLXI_9/XLXI_47")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_40 "XLXI_9/XLXI_40")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_63 "XLXI_9/XLXI_63")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_62 "XLXI_9/XLXI_62")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_50 "XLXI_9/XLXI_50")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_48 "XLXI_9/XLXI_48")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_45 "XLXI_9/XLXI_45")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_39 "XLXI_9/XLXI_39")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_33 "XLXI_9/XLXI_33")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_31 "XLXI_9/XLXI_31")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_61 "XLXI_9/XLXI_61")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_56 "XLXI_9/XLXI_56")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_54 "XLXI_9/XLXI_54")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_51 "XLXI_9/XLXI_51")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_38 "XLXI_9/XLXI_38")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_30 "XLXI_9/XLXI_30")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_64 "XLXI_9/XLXI_64")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_55 "XLXI_9/XLXI_55")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_46 "XLXI_9/XLXI_46")
+ (viewRef view_1 (cellRef XOR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_42 "XLXI_9/XLXI_42")
+ (viewRef view_1 (cellRef XNOR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_37 "XLXI_9/XLXI_37")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_35 "XLXI_9/XLXI_35")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename A_IBUF_renamed_0 "A_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename B_IBUF_renamed_1 "B_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename C_IBUF_renamed_2 "C_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename D_IBUF_renamed_3 "D_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename S0_IBUF_renamed_4 "S0_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename S1_IBUF_renamed_5 "S1_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename AN0_OBUF_renamed_6 "AN0_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename AN1_OBUF_renamed_7 "AN1_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename AN2_OBUF_renamed_8 "AN2_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename AN3_OBUF_renamed_9 "AN3_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename a_out_OBUF_renamed_10 "a_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename b_out_OBUF_renamed_11 "b_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename c_out_OBUF_renamed_12 "c_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename d_out_OBUF_renamed_13 "d_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename e_out_OBUF_renamed_14 "e_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename f_out_OBUF_renamed_15 "f_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename g_out_OBUF_renamed_16 "g_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename sign_OBUF_renamed_17 "sign_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (net A_IBUF
+ (joined
+ (portRef I (instanceRef XLXI_1_XLXI_8_XLXI_7))
+ (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_1))
+ (portRef I1 (instanceRef XLXI_1_XLXI_9_XLXI_10))
+ (portRef I1 (instanceRef XLXI_1_XLXI_10_XLXI_2))
+ (portRef I (instanceRef XLXI_1_XLXI_12_XLXI_9))
+ (portRef I1 (instanceRef XLXI_1_XLXI_12_XLXI_1))
+ (portRef I2 (instanceRef XLXI_2_XLXI_2_XLXI_2))
+ (portRef I2 (instanceRef XLXI_2_XLXI_2_XLXI_1))
+ (portRef I2 (instanceRef XLXI_2_XLXI_2_XLXI_3))
+ (portRef I2 (instanceRef XLXI_2_XLXI_1_XLXI_2))
+ (portRef I2 (instanceRef XLXI_2_XLXI_1_XLXI_1))
+ (portRef I2 (instanceRef XLXI_2_XLXI_1_XLXI_3))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_20))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_15))
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_2))
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_1))
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_3))
+ (portRef I0 (instanceRef XLXI_3_XLXI_8_XLXI_8))
+ (portRef I2 (instanceRef XLXI_3_XLXI_9_XLXI_3))
+ (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_9))
+ (portRef I (instanceRef XLXI_3_XLXI_12_XLXI_15))
+ (portRef D0 (instanceRef XLXI_4))
+ (portRef O (instanceRef A_IBUF_renamed_0))
+ )
+ )
+ (net B_IBUF
+ (joined
+ (portRef I (instanceRef XLXI_1_XLXI_8_XLXI_6))
+ (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_4))
+ (portRef I (instanceRef XLXI_1_XLXI_9_XLXI_16))
+ (portRef I (instanceRef XLXI_1_XLXI_10_XLXI_6))
+ (portRef I (instanceRef XLXI_2_XLXI_2_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_2_XLXI_1))
+ (portRef I (instanceRef XLXI_2_XLXI_1_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_1))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_19))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_1))
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_11))
+ (portRef I (instanceRef XLXI_3_XLXI_8_XLXI_10))
+ (portRef I (instanceRef XLXI_3_XLXI_9_XLXI_5))
+ (portRef I2 (instanceRef XLXI_3_XLXI_10_XLXI_15))
+ (portRef I (instanceRef XLXI_3_XLXI_10_XLXI_14))
+ (portRef I2 (instanceRef XLXI_3_XLXI_12_XLXI_14))
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_2))
+ (portRef I (instanceRef XLXI_2_XLXI_4_XLXI_12))
+ (portRef D0 (instanceRef XLXI_5))
+ (portRef O (instanceRef B_IBUF_renamed_1))
+ )
+ )
+ (net C_IBUF
+ (joined
+ (portRef I (instanceRef XLXI_1_XLXI_8_XLXI_8))
+ (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_3))
+ (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_1))
+ (portRef I (instanceRef XLXI_1_XLXI_9_XLXI_15))
+ (portRef I (instanceRef XLXI_1_XLXI_10_XLXI_7))
+ (portRef I (instanceRef XLXI_1_XLXI_12_XLXI_5))
+ (portRef I0 (instanceRef XLXI_1_XLXI_12_XLXI_3))
+ (portRef I0 (instanceRef XLXI_1_XLXI_12_XLXI_2))
+ (portRef I (instanceRef XLXI_2_XLXI_2_XLXI_5))
+ (portRef I0 (instanceRef XLXI_2_XLXI_2_XLXI_1))
+ (portRef I (instanceRef XLXI_2_XLXI_1_XLXI_5))
+ (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_1))
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_18))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_16))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_5))
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_1))
+ (portRef I (instanceRef XLXI_3_XLXI_8_XLXI_9))
+ (portRef I (instanceRef XLXI_3_XLXI_9_XLXI_6))
+ (portRef I0 (instanceRef XLXI_3_XLXI_9_XLXI_1))
+ (portRef I (instanceRef XLXI_3_XLXI_10_XLXI_16))
+ (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_10))
+ (portRef I1 (instanceRef XLXI_3_XLXI_12_XLXI_14))
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_15))
+ (portRef I (instanceRef XLXI_2_XLXI_4_XLXI_9))
+ (portRef I (instanceRef XLXI_2_XLXI_4_XLXI_13))
+ (portRef D0 (instanceRef XLXI_6))
+ (portRef O (instanceRef C_IBUF_renamed_2))
+ )
+ )
+ (net D_IBUF
+ (joined
+ (portRef I (instanceRef XLXI_1_XLXI_8_XLXI_9))
+ (portRef I3 (instanceRef XLXI_1_XLXI_8_XLXI_1))
+ (portRef I (instanceRef XLXI_1_XLXI_9_XLXI_13))
+ (portRef I (instanceRef XLXI_1_XLXI_10_XLXI_8))
+ (portRef I (instanceRef XLXI_1_XLXI_12_XLXI_6))
+ (portRef I0 (instanceRef XLXI_1_XLXI_12_XLXI_1))
+ (portRef I (instanceRef XLXI_2_XLXI_2_XLXI_6))
+ (portRef I0 (instanceRef XLXI_2_XLXI_2_XLXI_3))
+ (portRef I (instanceRef XLXI_2_XLXI_1_XLXI_6))
+ (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_3))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_21))
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_11))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_6))
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_3))
+ (portRef I1 (instanceRef XLXI_3_XLXI_8_XLXI_12))
+ (portRef I (instanceRef XLXI_3_XLXI_9_XLXI_7))
+ (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_2))
+ (portRef I (instanceRef XLXI_3_XLXI_10_XLXI_17))
+ (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_11))
+ (portRef I0 (instanceRef XLXI_3_XLXI_12_XLXI_14))
+ (portRef I (instanceRef XLXI_2_XLXI_4_XLXI_10))
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_11))
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_15))
+ (portRef D0 (instanceRef XLXI_7))
+ (portRef O (instanceRef D_IBUF_renamed_3))
+ )
+ )
+ (net S0_IBUF
+ (joined
+ (portRef S0 (instanceRef XLXI_7))
+ (portRef S0 (instanceRef XLXI_6))
+ (portRef S0 (instanceRef XLXI_5))
+ (portRef S0 (instanceRef XLXI_4))
+ (portRef O (instanceRef S0_IBUF_renamed_4))
+ )
+ )
+ (net S1_IBUF
+ (joined
+ (portRef S1 (instanceRef XLXI_7))
+ (portRef S1 (instanceRef XLXI_6))
+ (portRef S1 (instanceRef XLXI_5))
+ (portRef S1 (instanceRef XLXI_4))
+ (portRef O (instanceRef S1_IBUF_renamed_5))
+ )
+ )
+ (net XLXN_36
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_7))
+ (portRef D2 (instanceRef XLXI_7))
+ )
+ )
+ (net XLXN_35
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_5))
+ (portRef D2 (instanceRef XLXI_6))
+ )
+ )
+ (net XLXN_34
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_9_XLXI_10))
+ (portRef D2 (instanceRef XLXI_5))
+ )
+ )
+ (net XLXN_33
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_10_XLXI_2))
+ (portRef D2 (instanceRef XLXI_4))
+ )
+ )
+ (net XLXN_37
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_4))
+ (portRef D3 (instanceRef XLXI_7))
+ )
+ )
+ (net XLXN_38
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_22))
+ (portRef D3 (instanceRef XLXI_6))
+ )
+ )
+ (net XLXN_39
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_4))
+ (portRef D3 (instanceRef XLXI_5))
+ )
+ )
+ (net XLXN_41
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_4))
+ (portRef D3 (instanceRef XLXI_4))
+ )
+ )
+ (net XLXN_42
+ (joined
+ (portRef O (instanceRef XLXI_3_XLXI_8_XLXI_12))
+ (portRef D1 (instanceRef XLXI_7))
+ )
+ )
+ (net XLXN_43
+ (joined
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_4))
+ (portRef D1 (instanceRef XLXI_6))
+ )
+ )
+ (net XLXN_44
+ (joined
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_8))
+ (portRef D1 (instanceRef XLXI_5))
+ )
+ )
+ (net XLXN_45
+ (joined
+ (portRef O (instanceRef XLXI_3_XLXI_12_XLXI_16))
+ (portRef D1 (instanceRef XLXI_4))
+ )
+ )
+ (net XLXN_22
+ (joined
+ (portRef O (instanceRef XLXI_4))
+ (portRef I1 (instanceRef XLXI_9_XLXI_35))
+ (portRef I (instanceRef XLXI_9_XLXI_37))
+ (portRef I1 (instanceRef XLXI_9_XLXI_42))
+ (portRef I1 (instanceRef XLXI_9_XLXI_46))
+ (portRef I2 (instanceRef XLXI_9_XLXI_55))
+ (portRef I1 (instanceRef XLXI_9_XLXI_64))
+ )
+ )
+ (net XLXN_23
+ (joined
+ (portRef O (instanceRef XLXI_5))
+ (portRef I0 (instanceRef XLXI_9_XLXI_42))
+ (portRef I0 (instanceRef XLXI_9_XLXI_46))
+ (portRef I0 (instanceRef XLXI_9_XLXI_30))
+ (portRef I (instanceRef XLXI_9_XLXI_38))
+ (portRef I2 (instanceRef XLXI_9_XLXI_51))
+ (portRef I1 (instanceRef XLXI_9_XLXI_54))
+ (portRef I1 (instanceRef XLXI_9_XLXI_56))
+ (portRef I1 (instanceRef XLXI_9_XLXI_61))
+ )
+ )
+ (net XLXN_24
+ (joined
+ (portRef O (instanceRef XLXI_6))
+ (portRef I0 (instanceRef XLXI_9_XLXI_55))
+ (portRef I2 (instanceRef XLXI_9_XLXI_31))
+ (portRef I0 (instanceRef XLXI_9_XLXI_33))
+ (portRef I (instanceRef XLXI_9_XLXI_39))
+ (portRef I2 (instanceRef XLXI_9_XLXI_45))
+ (portRef I1 (instanceRef XLXI_9_XLXI_48))
+ (portRef I0 (instanceRef XLXI_9_XLXI_50))
+ (portRef I1 (instanceRef XLXI_9_XLXI_62))
+ (portRef I1 (instanceRef XLXI_9_XLXI_63))
+ )
+ )
+ (net XLXN_25
+ (joined
+ (portRef O (instanceRef XLXI_7))
+ (portRef I2 (instanceRef XLXI_9_XLXI_30))
+ (portRef I1 (instanceRef XLXI_9_XLXI_51))
+ (portRef I1 (instanceRef XLXI_9_XLXI_31))
+ (portRef I1 (instanceRef XLXI_9_XLXI_45))
+ (portRef I (instanceRef XLXI_9_XLXI_40))
+ (portRef I0 (instanceRef XLXI_9_XLXI_47))
+ )
+ )
+ (net AN0_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_5))
+ (portRef I (instanceRef AN0_OBUF_renamed_6))
+ )
+ )
+ (net AN1_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_6))
+ (portRef I (instanceRef AN1_OBUF_renamed_7))
+ )
+ )
+ (net AN2_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_7))
+ (portRef I (instanceRef AN2_OBUF_renamed_8))
+ )
+ )
+ (net AN3_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_8))
+ (portRef I (instanceRef AN3_OBUF_renamed_9))
+ )
+ )
+ (net a_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_65))
+ (portRef I (instanceRef a_out_OBUF_renamed_10))
+ )
+ )
+ (net b_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_66))
+ (portRef I (instanceRef b_out_OBUF_renamed_11))
+ )
+ )
+ (net c_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_67))
+ (portRef I (instanceRef c_out_OBUF_renamed_12))
+ )
+ )
+ (net d_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_69))
+ (portRef I (instanceRef d_out_OBUF_renamed_13))
+ )
+ )
+ (net e_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_68))
+ (portRef I (instanceRef e_out_OBUF_renamed_14))
+ )
+ )
+ (net f_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_70))
+ (portRef I (instanceRef f_out_OBUF_renamed_15))
+ )
+ )
+ (net g_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_71))
+ (portRef I (instanceRef g_out_OBUF_renamed_16))
+ )
+ )
+ (net sign_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_73))
+ (portRef I (instanceRef sign_OBUF_renamed_17))
+ )
+ )
+ (net XLXN_12
+ (joined
+ (portRef P (instanceRef XLXI_8))
+ (portRef E (instanceRef XLXI_7))
+ (portRef E (instanceRef XLXI_6))
+ (portRef E (instanceRef XLXI_5))
+ (portRef E (instanceRef XLXI_4))
+ (portRef I (instanceRef XLXI_9_XLXI_5))
+ (portRef I (instanceRef XLXI_9_XLXI_6))
+ (portRef I (instanceRef XLXI_9_XLXI_7))
+ )
+ )
+ (net N0
+ (joined
+ (portRef G (instanceRef XST_GND))
+ (portRef I (instanceRef XLXI_9_XLXI_8))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_2 "XLXI_1/XLXI_8/XLXN_2")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_2))
+ (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_4))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_13 "XLXI_1/XLXI_8/XLXN_13")
+ (joined
+ (portRef I2 (instanceRef XLXI_1_XLXI_8_XLXI_2))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_7))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_8 "XLXI_1/XLXI_8/XLXN_8")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_6))
+ (portRef I2 (instanceRef XLXI_1_XLXI_8_XLXI_1))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_4 "XLXI_1/XLXI_8/XLXN_4")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_5))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_4))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_16 "XLXI_1/XLXI_8/XLXN_16")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_2))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_8))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_1 "XLXI_1/XLXI_8/XLXN_1")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_2))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_3))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_17 "XLXI_1/XLXI_8/XLXN_17")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_3))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_9))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_5 "XLXI_1/XLXI_8/XLXN_5")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_5))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_1))
+ )
+ )
+ (net (rename XLXI_1_XLXI_9_XLXN_9 "XLXI_1/XLXI_9/XLXN_9")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_9_XLXI_12))
+ (portRef I0 (instanceRef XLXI_1_XLXI_9_XLXI_10))
+ )
+ )
+ (net (rename XLXI_1_XLXI_9_XLXN_15 "XLXI_1/XLXI_9/XLXN_15")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_9_XLXI_12))
+ (portRef O (instanceRef XLXI_1_XLXI_9_XLXI_16))
+ )
+ )
+ (net (rename XLXI_1_XLXI_9_XLXN_14 "XLXI_1/XLXI_9/XLXN_14")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_9_XLXI_12))
+ (portRef O (instanceRef XLXI_1_XLXI_9_XLXI_15))
+ )
+ )
+ (net (rename XLXI_1_XLXI_9_XLXN_13 "XLXI_1/XLXI_9/XLXN_13")
+ (joined
+ (portRef I2 (instanceRef XLXI_1_XLXI_9_XLXI_12))
+ (portRef O (instanceRef XLXI_1_XLXI_9_XLXI_13))
+ )
+ )
+ (net (rename XLXI_1_XLXI_10_XLXN_2 "XLXI_1/XLXI_10/XLXN_2")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_10_XLXI_4))
+ (portRef I0 (instanceRef XLXI_1_XLXI_10_XLXI_2))
+ )
+ )
+ (net (rename XLXI_1_XLXI_10_XLXN_13 "XLXI_1/XLXI_10/XLXN_13")
+ (joined
+ (portRef I2 (instanceRef XLXI_1_XLXI_10_XLXI_4))
+ (portRef O (instanceRef XLXI_1_XLXI_10_XLXI_6))
+ )
+ )
+ (net (rename XLXI_1_XLXI_10_XLXN_14 "XLXI_1/XLXI_10/XLXN_14")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_10_XLXI_4))
+ (portRef O (instanceRef XLXI_1_XLXI_10_XLXI_7))
+ )
+ )
+ (net (rename XLXI_1_XLXI_10_XLXN_15 "XLXI_1/XLXI_10/XLXN_15")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_10_XLXI_4))
+ (portRef O (instanceRef XLXI_1_XLXI_10_XLXI_8))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_12 "XLXI_1/XLXI_12/XLXN_12")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_9))
+ (portRef I1 (instanceRef XLXI_1_XLXI_12_XLXI_2))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_2 "XLXI_1/XLXI_12/XLXN_2")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_5))
+ (portRef I2 (instanceRef XLXI_1_XLXI_12_XLXI_1))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_6 "XLXI_1/XLXI_12/XLXN_6")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_12_XLXI_7))
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_3))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_4 "XLXI_1/XLXI_12/XLXN_4")
+ (joined
+ (portRef I2 (instanceRef XLXI_1_XLXI_12_XLXI_7))
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_2))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_3 "XLXI_1/XLXI_12/XLXN_3")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_12_XLXI_3))
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_6))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_5 "XLXI_1/XLXI_12/XLXN_5")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_12_XLXI_7))
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_1))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_2 "XLXI_2/XLXI_2/XLXN_2")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_2_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_2))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_7 "XLXI_2/XLXI_2/XLXN_7")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_2_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_5 "XLXI_2/XLXI_2/XLXN_5")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_2_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_5))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_1 "XLXI_2/XLXI_2/XLXN_1")
+ (joined
+ (portRef I2 (instanceRef XLXI_2_XLXI_2_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_1))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_6 "XLXI_2/XLXI_2/XLXN_6")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_2_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_6))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_3 "XLXI_2/XLXI_2/XLXN_3")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_2_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_2 "XLXI_2/XLXI_1/XLXN_2")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_2))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_7 "XLXI_2/XLXI_1/XLXN_7")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_5 "XLXI_2/XLXI_1/XLXN_5")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_5))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_1 "XLXI_2/XLXI_1/XLXN_1")
+ (joined
+ (portRef I2 (instanceRef XLXI_2_XLXI_1_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_1))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_6 "XLXI_2/XLXI_1/XLXN_6")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_6))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_3 "XLXI_2/XLXI_1/XLXN_3")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_51 "XLXI_2/XLXI_3/XLXN_51")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_20))
+ (portRef I3 (instanceRef XLXI_2_XLXI_3_XLXI_18))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_23 "XLXI_2/XLXI_3/XLXN_23")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_15))
+ (portRef I3 (instanceRef XLXI_2_XLXI_3_XLXI_11))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_2 "XLXI_2/XLXI_3/XLXN_2")
+ (joined
+ (portRef I3 (instanceRef XLXI_2_XLXI_3_XLXI_22))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_2))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_50 "XLXI_2/XLXI_3/XLXN_50")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_19))
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_18))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_7 "XLXI_2/XLXI_3/XLXN_7")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_56 "XLXI_2/XLXI_3/XLXN_56")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_22))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_18))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_24 "XLXI_2/XLXI_3/XLXN_24")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_16))
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_11))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_5 "XLXI_2/XLXI_3/XLXN_5")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_5))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_55 "XLXI_2/XLXI_3/XLXN_55")
+ (joined
+ (portRef I4 (instanceRef XLXI_2_XLXI_3_XLXI_22))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_1))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_54 "XLXI_2/XLXI_3/XLXN_54")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_18))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_21))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_57 "XLXI_2/XLXI_3/XLXN_57")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_22))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_11))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_6 "XLXI_2/XLXI_3/XLXN_6")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_6))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_3 "XLXI_2/XLXI_3/XLXN_3")
+ (joined
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_22))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_3))
+ )
+ )
+ (net (rename XLXI_3_XLXI_8_XLXN_17 "XLXI_3/XLXI_8/XLXN_17")
+ (joined
+ (portRef O (instanceRef XLXI_3_XLXI_8_XLXI_8))
+ (portRef I0 (instanceRef XLXI_3_XLXI_8_XLXI_12))
+ )
+ )
+ (net (rename XLXI_3_XLXI_8_XLXN_15 "XLXI_3/XLXI_8/XLXN_15")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_8_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_8_XLXI_10))
+ )
+ )
+ (net (rename XLXI_3_XLXI_8_XLXN_14 "XLXI_3/XLXI_8/XLXN_14")
+ (joined
+ (portRef I2 (instanceRef XLXI_3_XLXI_8_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_8_XLXI_9))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_3 "XLXI_3/XLXI_9/XLXN_3")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_9_XLXI_4))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_3))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_4 "XLXI_3/XLXI_9/XLXN_4")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_9_XLXI_3))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_5))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_5 "XLXI_3/XLXI_9/XLXN_5")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_3))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_6))
+ (portRef I0 (instanceRef XLXI_3_XLXI_9_XLXI_2))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_2 "XLXI_3/XLXI_9/XLXN_2")
+ (joined
+ (portRef I2 (instanceRef XLXI_3_XLXI_9_XLXI_4))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_1))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_6 "XLXI_3/XLXI_9/XLXN_6")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_1))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_7))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_1 "XLXI_3/XLXI_9/XLXN_1")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_4))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_2))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_35 "XLXI_3/XLXI_10/XLXN_35")
+ (joined
+ (portRef I3 (instanceRef XLXI_3_XLXI_10_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_9))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_37 "XLXI_3/XLXI_10/XLXN_37")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_15))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_44 "XLXI_3/XLXI_10/XLXN_44")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_9))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_14))
+ (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_10))
+ (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_11))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_49 "XLXI_3/XLXI_10/XLXN_49")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_15))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_16))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_41 "XLXI_3/XLXI_10/XLXN_41")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_10))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_47 "XLXI_3/XLXI_10/XLXN_47")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_15))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_17))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_40 "XLXI_3/XLXI_10/XLXN_40")
+ (joined
+ (portRef I2 (instanceRef XLXI_3_XLXI_10_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_11))
+ )
+ )
+ (net (rename XLXI_3_XLXI_12_XLXN_10 "XLXI_3/XLXI_12/XLXN_10")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_12_XLXI_16))
+ (portRef O (instanceRef XLXI_3_XLXI_12_XLXI_15))
+ )
+ )
+ (net (rename XLXI_3_XLXI_12_XLXN_8 "XLXI_3/XLXI_12/XLXN_8")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_12_XLXI_16))
+ (portRef O (instanceRef XLXI_3_XLXI_12_XLXI_14))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_1 "XLXI_2/XLXI_4/XLXN_1")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_14))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_14 "XLXI_2/XLXI_4/XLXN_14")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_16))
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_14))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_27 "XLXI_2/XLXI_4/XLXN_27")
+ (joined
+ (portRef I2 (instanceRef XLXI_2_XLXI_4_XLXI_11))
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_12))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_4 "XLXI_2/XLXI_4/XLXN_4")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_2))
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_4))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_28 "XLXI_2/XLXI_4/XLXN_28")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_11))
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_13))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_15 "XLXI_2/XLXI_4/XLXN_15")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_9))
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_16))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_12 "XLXI_2/XLXI_4/XLXN_12")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_15))
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_14))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_3 "XLXI_2/XLXI_4/XLXN_3")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_11))
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_4))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_16 "XLXI_2/XLXI_4/XLXN_16")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_10))
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_16))
+ )
+ )
+ (net (rename XLXI_9_XLXN_158 "XLXI_9/XLXN_158")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_53))
+ (portRef I (instanceRef XLXI_9_XLXI_68))
+ )
+ )
+ (net (rename XLXI_9_XLXN_131 "XLXI_9/XLXN_131")
+ (joined
+ (portRef I0 (instanceRef XLXI_9_XLXI_58))
+ (portRef O (instanceRef XLXI_9_XLXI_57))
+ )
+ )
+ (net (rename XLXI_9_XLXN_92 "XLXI_9/XLXN_92")
+ (joined
+ (portRef I2 (instanceRef XLXI_9_XLXI_41))
+ (portRef O (instanceRef XLXI_9_XLXI_43))
+ )
+ )
+ (net (rename XLXI_9_XLXN_156 "XLXI_9/XLXN_156")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_52))
+ (portRef I (instanceRef XLXI_9_XLXI_69))
+ )
+ )
+ (net (rename XLXI_9_XLXN_126 "XLXI_9/XLXN_126")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_49))
+ (portRef I2 (instanceRef XLXI_9_XLXI_52))
+ (portRef I0 (instanceRef XLXI_9_XLXI_53))
+ )
+ )
+ (net (rename XLXI_9_XLXN_93 "XLXI_9/XLXN_93")
+ (joined
+ (portRef I1 (instanceRef XLXI_9_XLXI_41))
+ (portRef O (instanceRef XLXI_9_XLXI_44))
+ )
+ )
+ (net (rename XLXI_9_XLXN_63 "XLXI_9/XLXN_63")
+ (joined
+ (portRef I2 (instanceRef XLXI_9_XLXI_34))
+ (portRef O (instanceRef XLXI_9_XLXI_32))
+ )
+ )
+ (net (rename XLXI_9_XLXN_162 "XLXI_9/XLXN_162")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_60))
+ (portRef I (instanceRef XLXI_9_XLXI_71))
+ )
+ )
+ (net (rename XLXI_9_XLXN_160 "XLXI_9/XLXN_160")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_58))
+ (portRef I (instanceRef XLXI_9_XLXI_70))
+ )
+ )
+ (net (rename XLXI_9_XLXN_151 "XLXI_9/XLXN_151")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_41))
+ (portRef I (instanceRef XLXI_9_XLXI_66))
+ )
+ )
+ (net (rename XLXI_9_XLXN_165 "XLXI_9/XLXN_165")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_72))
+ (portRef I (instanceRef XLXI_9_XLXI_73))
+ )
+ )
+ (net (rename XLXI_9_XLXN_149 "XLXI_9/XLXN_149")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_34))
+ (portRef I (instanceRef XLXI_9_XLXI_65))
+ )
+ )
+ (net (rename XLXI_9_XLXN_155 "XLXI_9/XLXN_155")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_47))
+ (portRef I (instanceRef XLXI_9_XLXI_67))
+ )
+ )
+ (net (rename XLXI_9_D_BAR "XLXI_9/D_BAR")
+ (joined
+ (portRef I0 (instanceRef XLXI_9_XLXI_64))
+ (portRef I0 (instanceRef XLXI_9_XLXI_56))
+ (portRef I1 (instanceRef XLXI_9_XLXI_33))
+ (portRef I0 (instanceRef XLXI_9_XLXI_48))
+ (portRef I0 (instanceRef XLXI_9_XLXI_62))
+ (portRef O (instanceRef XLXI_9_XLXI_40))
+ (portRef I1 (instanceRef XLXI_9_XLXI_32))
+ (portRef I0 (instanceRef XLXI_9_XLXI_49))
+ (portRef I0 (instanceRef XLXI_9_XLXI_43))
+ (portRef I0 (instanceRef XLXI_9_XLXI_57))
+ )
+ )
+ (net (rename XLXI_9_XLXN_147 "XLXI_9/XLXN_147")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_63))
+ (portRef I1 (instanceRef XLXI_9_XLXI_60))
+ )
+ )
+ (net (rename XLXI_9_XLXN_146 "XLXI_9/XLXN_146")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_62))
+ (portRef I2 (instanceRef XLXI_9_XLXI_60))
+ )
+ )
+ (net (rename XLXI_9_XLXN_113 "XLXI_9/XLXN_113")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_50))
+ (portRef I1 (instanceRef XLXI_9_XLXI_52))
+ )
+ )
+ (net (rename XLXI_9_XLXN_125 "XLXI_9/XLXN_125")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_48))
+ (portRef I3 (instanceRef XLXI_9_XLXI_52))
+ (portRef I1 (instanceRef XLXI_9_XLXI_53))
+ )
+ )
+ (net (rename XLXI_9_XLXN_94 "XLXI_9/XLXN_94")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_45))
+ (portRef I0 (instanceRef XLXI_9_XLXI_41))
+ )
+ )
+ (net (rename XLXI_9_C_BAR "XLXI_9/C_BAR")
+ (joined
+ (portRef I1 (instanceRef XLXI_9_XLXI_30))
+ (portRef I0 (instanceRef XLXI_9_XLXI_51))
+ (portRef I0 (instanceRef XLXI_9_XLXI_54))
+ (portRef I0 (instanceRef XLXI_9_XLXI_61))
+ (portRef O (instanceRef XLXI_9_XLXI_39))
+ (portRef I1 (instanceRef XLXI_9_XLXI_47))
+ (portRef I1 (instanceRef XLXI_9_XLXI_44))
+ (portRef I1 (instanceRef XLXI_9_XLXI_43))
+ (portRef I1 (instanceRef XLXI_9_XLXI_57))
+ )
+ )
+ (net (rename XLXI_9_XLXN_64 "XLXI_9/XLXN_64")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_33))
+ (portRef I1 (instanceRef XLXI_9_XLXI_34))
+ )
+ )
+ (net (rename XLXI_9_XLXN_62 "XLXI_9/XLXN_62")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_31))
+ (portRef I3 (instanceRef XLXI_9_XLXI_34))
+ )
+ )
+ (net (rename XLXI_9_XLXN_145 "XLXI_9/XLXN_145")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_61))
+ (portRef I3 (instanceRef XLXI_9_XLXI_60))
+ )
+ )
+ (net (rename XLXI_9_XLXN_130 "XLXI_9/XLXN_130")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_56))
+ (portRef I1 (instanceRef XLXI_9_XLXI_58))
+ )
+ )
+ (net (rename XLXI_9_XLXN_128 "XLXI_9/XLXN_128")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_54))
+ (portRef I3 (instanceRef XLXI_9_XLXI_58))
+ )
+ )
+ (net (rename XLXI_9_XLXN_114 "XLXI_9/XLXN_114")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_51))
+ (portRef I0 (instanceRef XLXI_9_XLXI_52))
+ )
+ )
+ (net (rename XLXI_9_B_BAR "XLXI_9/B_BAR")
+ (joined
+ (portRef I0 (instanceRef XLXI_9_XLXI_35))
+ (portRef I1 (instanceRef XLXI_9_XLXI_55))
+ (portRef O (instanceRef XLXI_9_XLXI_38))
+ (portRef I1 (instanceRef XLXI_9_XLXI_50))
+ (portRef I0 (instanceRef XLXI_9_XLXI_63))
+ (portRef I0 (instanceRef XLXI_9_XLXI_32))
+ (portRef I0 (instanceRef XLXI_9_XLXI_44))
+ (portRef I1 (instanceRef XLXI_9_XLXI_49))
+ )
+ )
+ (net (rename XLXI_9_XLXN_61 "XLXI_9/XLXN_61")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_30))
+ (portRef I4 (instanceRef XLXI_9_XLXI_34))
+ )
+ )
+ (net (rename XLXI_9_XLXN_148 "XLXI_9/XLXN_148")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_64))
+ (portRef I0 (instanceRef XLXI_9_XLXI_60))
+ )
+ )
+ (net (rename XLXI_9_XLXN_129 "XLXI_9/XLXN_129")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_55))
+ (portRef I2 (instanceRef XLXI_9_XLXI_58))
+ )
+ )
+ (net (rename XLXI_9_XLXN_105 "XLXI_9/XLXN_105")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_46))
+ (portRef I2 (instanceRef XLXI_9_XLXI_47))
+ )
+ )
+ (net (rename XLXI_9_XLXN_91 "XLXI_9/XLXN_91")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_42))
+ (portRef I3 (instanceRef XLXI_9_XLXI_41))
+ )
+ )
+ (net (rename XLXI_9_A_BAR "XLXI_9/A_BAR")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_37))
+ (portRef I2 (instanceRef XLXI_9_XLXI_54))
+ (portRef I2 (instanceRef XLXI_9_XLXI_56))
+ (portRef I0 (instanceRef XLXI_9_XLXI_31))
+ (portRef I0 (instanceRef XLXI_9_XLXI_45))
+ (portRef I (instanceRef XLXI_9_XLXI_72))
+ )
+ )
+ (net (rename XLXI_9_XLXN_65 "XLXI_9/XLXN_65")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_35))
+ (portRef I0 (instanceRef XLXI_9_XLXI_34))
+ )
+ )
+ (net A
+ (joined
+ (portRef A)
+ (portRef I (instanceRef A_IBUF_renamed_0))
+ )
+ )
+ (net B
+ (joined
+ (portRef B)
+ (portRef I (instanceRef B_IBUF_renamed_1))
+ )
+ )
+ (net C
+ (joined
+ (portRef C)
+ (portRef I (instanceRef C_IBUF_renamed_2))
+ )
+ )
+ (net D
+ (joined
+ (portRef D)
+ (portRef I (instanceRef D_IBUF_renamed_3))
+ )
+ )
+ (net S0
+ (joined
+ (portRef S0)
+ (portRef I (instanceRef S0_IBUF_renamed_4))
+ )
+ )
+ (net S1
+ (joined
+ (portRef S1)
+ (portRef I (instanceRef S1_IBUF_renamed_5))
+ )
+ )
+ (net AN0
+ (joined
+ (portRef AN0)
+ (portRef O (instanceRef AN0_OBUF_renamed_6))
+ )
+ )
+ (net AN1
+ (joined
+ (portRef AN1)
+ (portRef O (instanceRef AN1_OBUF_renamed_7))
+ )
+ )
+ (net AN2
+ (joined
+ (portRef AN2)
+ (portRef O (instanceRef AN2_OBUF_renamed_8))
+ )
+ )
+ (net AN3
+ (joined
+ (portRef AN3)
+ (portRef O (instanceRef AN3_OBUF_renamed_9))
+ )
+ )
+ (net a_out
+ (joined
+ (portRef a_out)
+ (portRef O (instanceRef a_out_OBUF_renamed_10))
+ )
+ )
+ (net b_out
+ (joined
+ (portRef b_out)
+ (portRef O (instanceRef b_out_OBUF_renamed_11))
+ )
+ )
+ (net c_out
+ (joined
+ (portRef c_out)
+ (portRef O (instanceRef c_out_OBUF_renamed_12))
+ )
+ )
+ (net d_out
+ (joined
+ (portRef d_out)
+ (portRef O (instanceRef d_out_OBUF_renamed_13))
+ )
+ )
+ (net e_out
+ (joined
+ (portRef e_out)
+ (portRef O (instanceRef e_out_OBUF_renamed_14))
+ )
+ )
+ (net f_out
+ (joined
+ (portRef f_out)
+ (portRef O (instanceRef f_out_OBUF_renamed_15))
+ )
+ )
+ (net g_out
+ (joined
+ (portRef g_out)
+ (portRef O (instanceRef g_out_OBUF_renamed_16))
+ )
+ )
+ (net sign
+ (joined
+ (portRef sign)
+ (portRef O (instanceRef sign_OBUF_renamed_17))
+ )
+ )
+ )
+ )
+ )
+ )
+
+ (design ALU
+ (cellRef ALU
+ (libraryRef ALU_lib)
+ )
+ (property PART (string "xc6slx16-3-csg324") (owner "Xilinx"))
+ )
+)
+
diff --git a/planAhead_run_2/lab1.data/constrs_1/fileset.xml b/planAhead_run_2/lab1.data/constrs_1/fileset.xml
new file mode 100755
index 0000000..80984cf
--- /dev/null
+++ b/planAhead_run_2/lab1.data/constrs_1/fileset.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1"
+ Minor="19">
+ <FileSet Name="constrs_1"
+ Type="Constrs"
+ RelSrcDir="$PSRCDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../ALU.ucf">
+ <FileInfo>
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TargetConstrsFile"
+ Val="$PPRDIR/../ALU.ucf"/>
+ <Option Name="ConstrsType"
+ Val="UCF"/>
+ </Config>
+ </FileSet>
+</DARoots>
diff --git a/planAhead_run_2/lab1.data/runs/impl_1.psg b/planAhead_run_2/lab1.data/runs/impl_1.psg
new file mode 100755
index 0000000..43196a2
--- /dev/null
+++ b/planAhead_run_2/lab1.data/runs/impl_1.psg
@@ -0,0 +1,18 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+ <StratHandle Name="ISE Defaults" Flow="ISE13">
+ <Desc>ISE Defaults, including packing registers in IOs off</Desc>
+ </StratHandle>
+ <Step Id="ngdbuild">
+ </Step>
+ <Step Id="map">
+ <Option Id="FFPackEnum">3</Option>
+ </Step>
+ <Step Id="par">
+ </Step>
+ <Step Id="trce">
+ </Step>
+ <Step Id="xdl">
+ </Step>
+</Strategy>
+
diff --git a/planAhead_run_2/lab1.data/runs/runs.xml b/planAhead_run_2/lab1.data/runs/runs.xml
new file mode 100755
index 0000000..2651a01
--- /dev/null
+++ b/planAhead_run_2/lab1.data/runs/runs.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="8">
+ <Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc6slx16csg324-3" ConstrsSet="constrs_1" State="current"/>
+</Runs>
+
diff --git a/planAhead_run_2/lab1.data/sources_1/fileset.xml b/planAhead_run_2/lab1.data/sources_1/fileset.xml
new file mode 100755
index 0000000..ff57e87
--- /dev/null
+++ b/planAhead_run_2/lab1.data/sources_1/fileset.xml
@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1"
+ Minor="19">
+ <FileSet Name="sources_1"
+ Type="DesignSrcs"
+ RelSrcDir="$PSRCDIR/sources_1">
+ <Filter Type="EDIFSrcs"/>
+ <File Path="$PPRDIR/../ALU.ngc">
+ <FileInfo>
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode"
+ Val="GateLvl"/>
+ <Option Name="GateLvlMode"
+ Val="EDIF"/>
+ <Option Name="TopModule"
+ Val="ALU"/>
+ <Option Name="TopFile"
+ Val="$PPRDIR/../ALU.ngc"/>
+ </Config>
+ </FileSet>
+</DARoots>
diff --git a/planAhead_run_2/lab1.data/wt/webtalk_pa.xml b/planAhead_run_2/lab1.data/wt/webtalk_pa.xml
new file mode 100755
index 0000000..2bed019
--- /dev/null
+++ b/planAhead_run_2/lab1.data/wt/webtalk_pa.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Thu Feb 16 20:00:26 2012">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="98952ffb65684da08e4e1169ac26bbac" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="GateLvl" type="DesignMode"/>
+<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="0" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="0" type="TclMode"/>
+<property name="ISEMode" value="14" type="ISEMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/planAhead_run_2/lab1.ppr b/planAhead_run_2/lab1.ppr
new file mode 100755
index 0000000..6081e20
--- /dev/null
+++ b/planAhead_run_2/lab1.ppr
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Project Version="4" Minor="27">
+ <FileSet Dir="sources_1" File="fileset.xml"/>
+ <FileSet Dir="constrs_1" File="fileset.xml"/>
+ <RunSet Dir="runs" File="runs.xml"/>
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <DefaultPromote Dir="$PROMOTEDIR"/>
+ <Config>
+ <Option Name="Part" Val="xc6slx16csg324-3"/>
+ <Option Name="TargetLanguage" Val="Verilog"/>
+ <Option Name="SourceMgmtMode" Val="All"/>
+ </Config>
+</Project>
+
diff --git a/planAhead_run_2/planAhead.jou b/planAhead_run_2/planAhead.jou
new file mode 100755
index 0000000..2ada6d2
--- /dev/null
+++ b/planAhead_run_2/planAhead.jou
@@ -0,0 +1,18 @@
+#-----------------------------------------------------------
+# PlanAhead v13.3 (64-bit)
+# Build 147507 by hdbuild on Tue Oct 4 19:13:50 MDT 2011
+# Start of session at: Thu Feb 16 18:59:46 2012
+# Process ID: 3164
+# Log file: X:/My Documents/ec311/ec311-lab1/planAhead_run_2/planAhead.log
+# Journal file: X:/My Documents/ec311/ec311-lab1/planAhead_run_2/planAhead.jou
+#-----------------------------------------------------------
+start_gui
+source {X:/My Documents/ec311/ec311-lab1/pa.fromNetlist.tcl}
+refresh_design
+refresh_design
+refresh_design
+refresh_design
+refresh_design
+refresh_design
+exit
+stop_gui
diff --git a/planAhead_run_2/planAhead.log b/planAhead_run_2/planAhead.log
new file mode 100755
index 0000000..4c49347
--- /dev/null
+++ b/planAhead_run_2/planAhead.log
@@ -0,0 +1,198 @@
+#-----------------------------------------------------------
+# PlanAhead v13.3 (64-bit)
+# Build 147507 by hdbuild on Tue Oct 4 19:13:50 MDT 2011
+# Start of session at: Thu Feb 16 18:59:46 2012
+# Process ID: 3164
+# Log file: X:/My Documents/ec311/ec311-lab1/planAhead_run_2/planAhead.log
+# Journal file: X:/My Documents/ec311/ec311-lab1/planAhead_run_2/planAhead.jou
+#-----------------------------------------------------------
+INFO: [Common-78] Attempting to get a license: PlanAhead
+INFO: [Common-82] Got a license: PlanAhead
+INFO: [Device-25] Loading parts and site information from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\arch.xmlParsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
+Finished parsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
+start_gui
+source {X:/My Documents/ec311/ec311-lab1/pa.fromNetlist.tcl}
+# create_project -name lab1 -dir "X:/My Documents/ec311/ec311-lab1/planAhead_run_2" -part xc6slx16csg324-3
+Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
+Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
+Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
+Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
+Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
+Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "X:/My Documents/ec311/ec311-lab1/ALU.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {X:/My Documents/ec311/ec311-lab1} }
+# set_param project.pinAheadLayout yes
+# set_property target_constrs_file "ALU.ucf" [current_fileset -constrset]
+Adding file 'X:\My Documents\ec311\ec311-lab1\ALU.ucf' to fileset 'constrs_1'
+# add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]]
+# open_netlist_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to part: xc6slx16csg324-3
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91624 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+INFO: [PlanAhead-566] Unisim Transformation Summary:
+No Unisim elements were transformed.open_netlist_design: Time (s): 13.385w. Memory (MB): 744.074p 196.641g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91432 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 9.017w. Memory (MB): 778.047p 27.094g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91752 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.317w. Memory (MB): 783.742p 5.559g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91560 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.364w. Memory (MB): 786.453p 2.711g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91880 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.628w. Memory (MB): 805.910p 19.457g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91368 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.425w. Memory (MB): 807.293p 0.000g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91304 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.566w. Memory (MB): 807.293p 0.000g
+exit
+stop_gui
+INFO: [PlanAhead-261] Exiting PlanAhead...
+INFO: [Common-83] Releasing license: PlanAhead
diff --git a/planAhead_run_2/planAhead_run.log b/planAhead_run_2/planAhead_run.log
new file mode 100755
index 0000000..3809618
--- /dev/null
+++ b/planAhead_run_2/planAhead_run.log
@@ -0,0 +1,196 @@
+
+****** PlanAhead v13.3 (64-bit)
+ **** Build 147507 by hdbuild on Tue Oct 4 19:13:50 MDT 2011
+ ** Copyright 1986-1999, 2001-2011 Xilinx, Inc. All Rights Reserved.
+
+INFO: [Common-78] Attempting to get a license: PlanAhead
+INFO: [Common-82] Got a license: PlanAhead
+INFO: [Device-25] Loading parts and site information from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\arch.xmlParsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
+Finished parsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
+start_gui
+starting gui ...
+source {X:/My Documents/ec311/ec311-lab1/pa.fromNetlist.tcl}
+# create_project -name lab1 -dir "X:/My Documents/ec311/ec311-lab1/planAhead_run_2" -part xc6slx16csg324-3
+Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
+Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
+Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
+Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
+Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
+Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "X:/My Documents/ec311/ec311-lab1/ALU.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {X:/My Documents/ec311/ec311-lab1} }
+# set_param project.pinAheadLayout yes
+# set_property target_constrs_file "ALU.ucf" [current_fileset -constrset]
+Adding file 'X:\My Documents\ec311\ec311-lab1\ALU.ucf' to fileset 'constrs_1'
+# add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]]
+# open_netlist_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to part: xc6slx16csg324-3
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91624 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+INFO: [PlanAhead-566] Unisim Transformation Summary:
+No Unisim elements were transformed.open_netlist_design: Time (s): 13.385w. Memory (MB): 744.074p 196.641g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91432 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 9.017w. Memory (MB): 778.047p 27.094g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91752 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.317w. Memory (MB): 783.742p 5.559g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91560 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.364w. Memory (MB): 786.453p 2.711g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91880 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.628w. Memory (MB): 805.910p 19.457g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91368 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.425w. Memory (MB): 807.293p 0.000g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91304 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.566w. Memory (MB): 807.293p 0.000g
+exit
+stop_gui
+INFO: [PlanAhead-261] Exiting PlanAhead...
+INFO: [Common-83] Releasing license: PlanAhead
diff --git a/sch2HdlBatchFile b/sch2HdlBatchFile
index e69de29..0c0f422 100755
--- a/sch2HdlBatchFile
+++ b/sch2HdlBatchFile
@@ -0,0 +1,3 @@
+sch2hdl,-intstyle,ise,-family,spartan6,-verilog,X:/My Documents/ec311/ec311-lab1/Modulo_0.vf,-w,X:/My Documents/ec311/ec311-lab1/Modulo_0.sch
+sch2hdl,-intstyle,ise,-family,spartan6,-verilog,X:/My Documents/ec311/ec311-lab1/Modulo.vf,-w,X:/My Documents/ec311/ec311-lab1/Modulo.sch
+sch2hdl,-intstyle,ise,-family,spartan6,-verilog,X:/My Documents/ec311/ec311-lab1/ALU.vf,-w,X:/My Documents/ec311/ec311-lab1/ALU.sch
diff --git a/sev_seg_disp.vf b/sev_seg_disp.vf
index f19330a..89f7bf5 100755
--- a/sev_seg_disp.vf
+++ b/sev_seg_disp.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : sev_seg_disp.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:08
+// /___/ /\ Timestamp : 02/16/2012 18:40:36
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/sev_seg_disp.vf" -w "X:/My Documents/ec311/lab1/sev_seg_disp.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/sev_seg_disp.vf" -w "X:/My Documents/ec311/ec311-lab1/sev_seg_disp.sch"
//Design Name: sev_seg_disp
//Device: spartan6
//Purpose:
diff --git a/usage_statistics_webtalk.html b/usage_statistics_webtalk.html
index 75086d7..c049566 100755
--- a/usage_statistics_webtalk.html
+++ b/usage_statistics_webtalk.html
@@ -17,7 +17,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
-<TD><xtag-property name="RandomID">dbce46a19c5c40ccaaf30d92d5e4ee96</xtag-property>.<xtag-property name="ProjectID">122a59e4f4dc4f05b8d5b3e9ab90be80</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
+<TD><xtag-property name="RandomID">6a162e1ea80e42df9d06b05d72bff062</xtag-property>.<xtag-property name="ProjectID">9e8420de10a2429e85800c55fcf0284c</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage"></xtag-property></TD>
</TR>
@@ -29,7 +29,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
-<TD><xtag-property name="Date Generated">2012-02-15T15:29:36</xtag-property></TD>
+<TD><xtag-property name="Date Generated">2012-02-16T21:17:39</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">IMPACT</xtag-property></TD>
</TR>
@@ -49,7 +49,19 @@
<TD><xtag-property-name>Part1</xtag-property-name>=<xtag-property-value>xc6slx16</xtag-property-value></TD>
<TR ALIGN=CENTER><TD COLSPAN=4><B>Boundary Scan Operations Statistics</B></TD></TR>
<TR>
-<TD><xtag-property-name>BSCAN Operation</xtag-property-name>=<xtag-property-value>Program -p 0 -v </xtag-property-value></TD>
+<TD><xtag-property-name>BSCAN Operation</xtag-property-name>=<xtag-property-value>Program -p 0 </xtag-property-value></TD>
+<TD><xtag-property-name>BSCAN Operation</xtag-property-name>=<xtag-property-value>Program -p 0 </xtag-property-value></TD>
+<TD><xtag-property-name>BSCAN Operation</xtag-property-name>=<xtag-property-value>Program -p 0 </xtag-property-value></TD>
+<TD><xtag-property-name>BSCAN Operation</xtag-property-name>=<xtag-property-value>Program -p 0 </xtag-property-value></TD>
+
+</TR><TR><TD><xtag-property-name>BSCAN Operation</xtag-property-name>=<xtag-property-value>Program -p 0 </xtag-property-value></TD>
+<TD><xtag-property-name>BSCAN Operation</xtag-property-name>=<xtag-property-value>Program -p 0 </xtag-property-value></TD>
+<TD><xtag-property-name>BSCAN Operation</xtag-property-name>=<xtag-property-value>Program -p 0 </xtag-property-value></TD>
+<TD><xtag-property-name>BSCAN Operation</xtag-property-name>=<xtag-property-value>Program -p 0 </xtag-property-value></TD>
+
+</TR><TR><TD><xtag-property-name>BSCAN Operation</xtag-property-name>=<xtag-property-value>Program -p 0 </xtag-property-value></TD>
+<TD><xtag-property-name>BSCAN Operation</xtag-property-name>=<xtag-property-value>Program -p 0 </xtag-property-value></TD>
+<TD><xtag-property-name>BSCAN Operation</xtag-property-name>=<xtag-property-value>Program -p 0 </xtag-property-value></TD>
<TR ALIGN=CENTER><TD COLSPAN=4><B>Cable Summary</B></TD></TR>
<TR>
<TD><xtag-property-name>Cable Type</xtag-property-name>=<xtag-property-value>Nexys3</xtag-property-value></TD>
diff --git a/webtalk.log b/webtalk.log
index b3b6d7b..d3c4486 100755
--- a/webtalk.log
+++ b/webtalk.log
@@ -3,7 +3,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
-ProjectID=122a59e4f4dc4f05b8d5b3e9ab90be80
+ProjectID=9e8420de10a2429e85800c55fcf0284c
ProjectIteration=1
WebTalk Summary
@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON.
-INFO:WebTalk:4 - X:/My Documents/ec311/lab1/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2012-02-15T15:29:44. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/13.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
+INFO:WebTalk:4 - X:/My Documents/ec311/ec311-lab1/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2012-02-16T21:17:46. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/13.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
diff --git a/webtalk_impact.xml b/webtalk_impact.xml
index a0211d4..26b11db 100755
--- a/webtalk_impact.xml
+++ b/webtalk_impact.xml
@@ -3,9 +3,9 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="impact" timeStamp="Wed Feb 15 15:29:36 2012">
+<application name="impact" timeStamp="Thu Feb 16 21:17:38 2012">
<section name="Project Information" visible="false">
-<property name="ProjectID" value="122a59e4f4dc4f05b8d5b3e9ab90be80"/>
+<property name="ProjectID" value="9e8420de10a2429e85800c55fcf0284c"/>
<property name="ProjectIteration" value="1"/>
</section>
<section name="iMPACT Project Info" visible="true">
@@ -25,7 +25,27 @@ This means code written to parse this file will need to be revisited each subseq
<property name="Part1" value="xc6slx16"/>
</item>
<item name="Boundary Scan Operations Statistics">
-<property name="BSCAN Operation" value="Program -p 0 -v
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
+"/>
+<property name="BSCAN Operation" value="Program -p 0
"/>
</item>
<item name="Cable Summary">
diff --git a/webtalk_pn.xml b/webtalk_pn.xml
index 5409eba..78fb8e5 100755
--- a/webtalk_pn.xml
+++ b/webtalk_pn.xml
@@ -3,11 +3,11 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pn" timeStamp="Wed Feb 15 15:16:03 2012">
+<application name="pn" timeStamp="Thu Feb 16 19:53:06 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="23EF1CF2DA254B0F8463C6B682ABB1F9" type="project"/>
-<property name="ProjectIteration" value="1" type="project"/>
-<property name="ProjectFile" value="X:/My Documents/ec311/lab1/lab1.xise" type="project"/>
+<property name="ProjectIteration" value="11" type="project"/>
+<property name="ProjectFile" value="X:/My Documents/ec311/ec311-lab1/lab1.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2012-02-15T14:51:10" type="project"/>
</section>
<section name="Project Statistics" visible="true">
@@ -16,6 +16,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
+<property name="PROP_OverwriteSym" value="true" type="process"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
@@ -24,7 +25,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2012-02-15T14:51:10" type="design"/>
<property name="PROP_intWbtProjectID" value="23EF1CF2DA254B0F8463C6B682ABB1F9" type="design"/>
-<property name="PROP_intWbtProjectIteration" value="1" type="process"/>
+<property name="PROP_intWbtProjectIteration" value="11" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
diff --git a/xlnx_auto_0_xdb/cst.xbcd b/xlnx_auto_0_xdb/cst.xbcd
index 4ccedbd..3b63769 100755
--- a/xlnx_auto_0_xdb/cst.xbcd
+++ b/xlnx_auto_0_xdb/cst.xbcd
Binary files differ
diff --git a/xst/work/work.sdbl b/xst/work/work.sdbl
index cc5bedb..41dc61a 100755
--- a/xst/work/work.sdbl
+++ b/xst/work/work.sdbl
Binary files differ
diff --git a/xst/work/work.sdbx b/xst/work/work.sdbx
index 164ea43..774796a 100755
--- a/xst/work/work.sdbx
+++ b/xst/work/work.sdbx
Binary files differ
generated by cgit v1.2.3-54-g00ecf (git 2.45.2) at 2024-12-03 18:02:31 +0000