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author | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:19 -0500 |
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committer | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:19 -0500 |
commit | 57738e75e221fe61a8f87270b430c0f1c0b8ead5 (patch) | |
tree | 8ace7cfb1f8b7330e45dad06e4a21efeb2cadd64 /Negate_0.vf | |
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Diffstat (limited to 'Negate_0.vf')
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diff --git a/Negate_0.vf b/Negate_0.vf new file mode 100755 index 0000000..4ea3c60 --- /dev/null +++ b/Negate_0.vf @@ -0,0 +1,50 @@ +////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version : 13.3
+// \ \ Application : sch2hdl
+// / / Filename : Negate_0.vf
+// /___/ /\ Timestamp : 02/15/2012 15:00:09
+// \ \ / \
+// \___\/\___\
+//
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate_0.vf" -w "X:/My Documents/ec311/lab1/Negate_0.sch"
+//Design Name: Negate_0
+//Device: spartan6
+//Purpose:
+// This verilog netlist is translated from an ECS schematic.It can be
+// synthesized and simulated, but it should not be modified.
+//
+`timescale 1ns / 1ps
+
+module Negate_0(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_14;
+ wire XLXN_15;
+ wire XLXN_17;
+
+ AND3 XLXI_8 (.I0(b3),
+ .I1(XLXN_15),
+ .I2(XLXN_14),
+ .O(XLXN_17));
+ INV XLXI_9 (.I(b1),
+ .O(XLXN_14));
+ INV XLXI_10 (.I(b2),
+ .O(XLXN_15));
+ OR2 XLXI_12 (.I0(XLXN_17),
+ .I1(b0),
+ .O(result));
+endmodule
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