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+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+//   ____  ____ 
+//  /   /\/   / 
+// /___/  \  /    Vendor: Xilinx 
+// \   \   \/     Version : 13.3
+//  \   \         Application : sch2hdl
+//  /   /         Filename : Negate_0.vf
+// /___/   /\     Timestamp : 02/15/2012 15:00:09
+// \   \  /  \ 
+//  \___\/\___\ 
+//
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate_0.vf" -w "X:/My Documents/ec311/lab1/Negate_0.sch"
+//Design Name: Negate_0
+//Device: spartan6
+//Purpose:
+//    This verilog netlist is translated from an ECS schematic.It can be 
+//    synthesized and simulated, but it should not be modified. 
+//
+`timescale 1ns / 1ps
+
+module Negate_0(b0, 
+                b1, 
+                b2, 
+                b3, 
+                result);
+
+    input b0;
+    input b1;
+    input b2;
+    input b3;
+   output result;
+   
+   wire XLXN_14;
+   wire XLXN_15;
+   wire XLXN_17;
+   
+   AND3  XLXI_8 (.I0(b3), 
+                .I1(XLXN_15), 
+                .I2(XLXN_14), 
+                .O(XLXN_17));
+   INV  XLXI_9 (.I(b1), 
+               .O(XLXN_14));
+   INV  XLXI_10 (.I(b2), 
+                .O(XLXN_15));
+   OR2  XLXI_12 (.I0(XLXN_17), 
+                .I1(b0), 
+                .O(result));
+endmodule