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| author | Michael Abed <michaelabed@gmail.com> | 2012-02-17 12:08:05 -0500 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-02-17 12:08:05 -0500 |
| commit | 70b77304f37d9681aa3bfa0eb57df0bcfd1aef81 (patch) | |
| tree | 48ab397b4072275dbc5a6b2f92a54d3c79e1fdea /Negate_2.vf | |
| parent | 57738e75e221fe61a8f87270b430c0f1c0b8ead5 (diff) | |
| download | ec311-lab1-70b77304f37d9681aa3bfa0eb57df0bcfd1aef81.tar.gz ec311-lab1-70b77304f37d9681aa3bfa0eb57df0bcfd1aef81.tar.bz2 ec311-lab1-70b77304f37d9681aa3bfa0eb57df0bcfd1aef81.zip | |
Diffstat (limited to 'Negate_2.vf')
| -rwxr-xr-x | Negate_2.vf | 59 |
1 files changed, 32 insertions, 27 deletions
diff --git a/Negate_2.vf b/Negate_2.vf index 6ce41b2..b2302b8 100755 --- a/Negate_2.vf +++ b/Negate_2.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Negate_2.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:09
+// /___/ /\ Timestamp : 02/16/2012 18:54:27
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate_2.vf" -w "X:/My Documents/ec311/lab1/Negate_2.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Negate_2.vf" -w "X:/My Documents/ec311/ec311-lab1/Negate_2.sch"
//Design Name: Negate_2
//Device: spartan6
//Purpose:
@@ -32,31 +32,36 @@ module Negate_2(b0, input b3;
output result;
- wire XLXN_7;
- wire XLXN_9;
- wire XLXN_10;
- wire XLXN_12;
- wire XLXN_16;
- wire XLXN_17;
+ wire XLXN_35;
+ wire XLXN_37;
+ wire XLXN_40;
+ wire XLXN_41;
+ wire XLXN_44;
+ wire XLXN_47;
+ wire XLXN_49;
- AND2 XLXI_1 (.I0(XLXN_7),
- .I1(b3),
- .O(XLXN_9));
- AND3 XLXI_2 (.I0(b2),
- .I1(XLXN_16),
- .I2(XLXN_17),
- .O(XLXN_10));
- OR2 XLXI_3 (.I0(XLXN_10),
- .I1(XLXN_9),
+ OR4 XLXI_8 (.I0(XLXN_37),
+ .I1(XLXN_41),
+ .I2(XLXN_40),
+ .I3(XLXN_35),
.O(result));
- OR3 XLXI_4 (.I0(XLXN_12),
- .I1(b1),
- .I2(b0),
- .O(XLXN_7));
- INV XLXI_5 (.I(b2),
- .O(XLXN_12));
- INV XLXI_6 (.I(b1),
- .O(XLXN_16));
- INV XLXI_7 (.I(b0),
- .O(XLXN_17));
+ AND2 XLXI_9 (.I0(XLXN_44),
+ .I1(b3),
+ .O(XLXN_35));
+ AND2 XLXI_10 (.I0(b1),
+ .I1(XLXN_44),
+ .O(XLXN_41));
+ AND2 XLXI_11 (.I0(b0),
+ .I1(XLXN_44),
+ .O(XLXN_40));
+ INV XLXI_14 (.I(b2),
+ .O(XLXN_44));
+ AND3 XLXI_15 (.I0(XLXN_47),
+ .I1(XLXN_49),
+ .I2(b2),
+ .O(XLXN_37));
+ INV XLXI_16 (.I(b1),
+ .O(XLXN_49));
+ INV XLXI_17 (.I(b0),
+ .O(XLXN_47));
endmodule
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