diff options
| author | Michael Abed <michaelabed@gmail.com> | 2012-02-17 12:08:05 -0500 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-02-17 12:08:05 -0500 |
| commit | 70b77304f37d9681aa3bfa0eb57df0bcfd1aef81 (patch) | |
| tree | 48ab397b4072275dbc5a6b2f92a54d3c79e1fdea /lab1.xise | |
| parent | 57738e75e221fe61a8f87270b430c0f1c0b8ead5 (diff) | |
| download | ec311-lab1-master.tar.gz ec311-lab1-master.tar.bz2 ec311-lab1-master.zip | |
Diffstat (limited to 'lab1.xise')
| -rwxr-xr-x | lab1.xise | 5 |
1 files changed, 2 insertions, 3 deletions
@@ -12,7 +12,7 @@ <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> </header> - <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/> + <version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/> <files> <file xil_pn:name="ALU.sch" xil_pn:type="FILE_SCHEMATIC"> @@ -109,7 +109,7 @@ <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> @@ -226,7 +226,6 @@ <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/> <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/> <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |