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| author | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:19 -0500 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:19 -0500 |
| commit | 57738e75e221fe61a8f87270b430c0f1c0b8ead5 (patch) | |
| tree | 8ace7cfb1f8b7330e45dad06e4a21efeb2cadd64 /pa.fromHdl.tcl | |
| download | ec311-lab1-57738e75e221fe61a8f87270b430c0f1c0b8ead5.tar.gz ec311-lab1-57738e75e221fe61a8f87270b430c0f1c0b8ead5.tar.bz2 ec311-lab1-57738e75e221fe61a8f87270b430c0f1c0b8ead5.zip | |
initial commit
Diffstat (limited to 'pa.fromHdl.tcl')
| -rwxr-xr-x | pa.fromHdl.tcl | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/pa.fromHdl.tcl b/pa.fromHdl.tcl new file mode 100755 index 0000000..68516e9 --- /dev/null +++ b/pa.fromHdl.tcl @@ -0,0 +1,58 @@ +
+# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator
+
+create_project -name lab1 -dir "X:/My Documents/ec311/lab1/planAhead_run_1" -part xc6slx16csg324-3
+set_param project.pinAheadLayout yes
+set srcset [get_property srcset [current_run -impl]]
+set_property top ALU $srcset
+set_property target_constrs_file "ALU.ucf" [current_fileset -constrset]
+set hdlfile [add_files [list {Negate_3.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {Negate_2.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {Negate_1.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {Negate_0.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {Modulo_3.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {Modulo_1.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {Modulo_0.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {Divide_3.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {Divide_2.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {Divide_1.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {Divide_0.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {sev_seg_disp.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {Negate.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {Modulo.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {Divide.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {ALU.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]]
+open_rtl_design -part xc6slx16csg324-3
|