summaryrefslogtreecommitdiff
path: root/planAhead_run_1/lab1.data/sources_1
diff options
context:
space:
mode:
authorMichael Abed <michaelabed@gmail.com>2012-02-17 12:08:05 -0500
committerMichael Abed <michaelabed@gmail.com>2012-02-17 12:08:05 -0500
commit70b77304f37d9681aa3bfa0eb57df0bcfd1aef81 (patch)
tree48ab397b4072275dbc5a6b2f92a54d3c79e1fdea /planAhead_run_1/lab1.data/sources_1
parent57738e75e221fe61a8f87270b430c0f1c0b8ead5 (diff)
downloadec311-lab1-master.tar.gz
ec311-lab1-master.tar.bz2
ec311-lab1-master.zip
make it workHEADmaster
Diffstat (limited to 'planAhead_run_1/lab1.data/sources_1')
-rwxr-xr-xplanAhead_run_1/lab1.data/sources_1/chipscope.xml6
-rwxr-xr-xplanAhead_run_1/lab1.data/sources_1/fileset.xml156
-rwxr-xr-xplanAhead_run_1/lab1.data/sources_1/ports.xml24
3 files changed, 42 insertions, 144 deletions
diff --git a/planAhead_run_1/lab1.data/sources_1/chipscope.xml b/planAhead_run_1/lab1.data/sources_1/chipscope.xml
new file mode 100755
index 0000000..af5cfeb
--- /dev/null
+++ b/planAhead_run_1/lab1.data/sources_1/chipscope.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<ChipScope Version="1" Minor="3">
+ <UnassignedNets>
+ </UnassignedNets>
+</ChipScope>
+
diff --git a/planAhead_run_1/lab1.data/sources_1/fileset.xml b/planAhead_run_1/lab1.data/sources_1/fileset.xml
index 8ada118..c8f890f 100755
--- a/planAhead_run_1/lab1.data/sources_1/fileset.xml
+++ b/planAhead_run_1/lab1.data/sources_1/fileset.xml
@@ -4,8 +4,8 @@
<FileSet Name="sources_1"
Type="DesignSrcs"
RelSrcDir="$PSRCDIR/sources_1">
- <Filter Type="Srcs"/>
- <File Path="$PPRDIR/../Negate_2.vf">
+ <Filter Type="EDIFSrcs"/>
+ <File Path="$PPRDIR/../ALU.ngc">
<FileInfo>
<Attr Name="UsedInSynthesis"
Val="1"/>
@@ -15,58 +15,8 @@
Val="1"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../Negate_1.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Negate_0.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Modulo_3.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Modulo_1.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Modulo_0.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Divide_3.vf">
- <FileInfo>
+ <File Path="$PDATADIR/sources_1/ports.xml">
+ <FileInfo SFType="PortsDb">
<Attr Name="UsedInSynthesis"
Val="1"/>
<Attr Name="UsedInImplementation"
@@ -75,88 +25,8 @@
Val="1"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../Divide_2.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Divide_1.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Divide_0.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../sev_seg_disp.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Negate_3.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Modulo.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Divide.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../ALU.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Negate.vf">
- <FileInfo>
+ <File Path="$PDATADIR/sources_1/chipscope.xml">
+ <FileInfo SFType="ChipscopeDb">
<Attr Name="UsedInSynthesis"
Val="1"/>
<Attr Name="UsedInImplementation"
@@ -167,15 +37,13 @@
</File>
<Config>
<Option Name="DesignMode"
- Val="RTL"/>
+ Val="GateLvl"/>
+ <Option Name="GateLvlMode"
+ Val="EDIF"/>
<Option Name="TopModule"
- Val="Negate"/>
- <Option Name="TopLib"
- Val="work"/>
- <Option Name="TopRTLFile"
- Val="$PPRDIR/../Negate.vf"/>
- <Option Name="TopAutoSet"
- Val="TRUE"/>
+ Val="ALU"/>
+ <Option Name="TopFile"
+ Val="$PPRDIR/../ALU.ngc"/>
</Config>
</FileSet>
</DARoots>
diff --git a/planAhead_run_1/lab1.data/sources_1/ports.xml b/planAhead_run_1/lab1.data/sources_1/ports.xml
new file mode 100755
index 0000000..99a5439
--- /dev/null
+++ b/planAhead_run_1/lab1.data/sources_1/ports.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0"?>
+<Interface Version="1" Minor="1">
+ <Ifc Id="ROOT" Top="1">
+ <Port Id="A" Dir="IN"/>
+ <Port Id="B" Dir="IN"/>
+ <Port Id="C" Dir="IN"/>
+ <Port Id="D" Dir="IN"/>
+ <Port Id="S0" Dir="IN"/>
+ <Port Id="S1" Dir="IN"/>
+ <Port Id="AN0" Dir="OUT"/>
+ <Port Id="AN1" Dir="OUT"/>
+ <Port Id="AN2" Dir="OUT"/>
+ <Port Id="AN3" Dir="OUT"/>
+ <Port Id="a_out" Dir="OUT"/>
+ <Port Id="b_out" Dir="OUT"/>
+ <Port Id="c_out" Dir="OUT"/>
+ <Port Id="d_out" Dir="OUT"/>
+ <Port Id="e_out" Dir="OUT"/>
+ <Port Id="f_out" Dir="OUT"/>
+ <Port Id="g_out" Dir="OUT"/>
+ <Port Id="sign" Dir="OUT"/>
+ </Ifc>
+</Interface>
+
generated by cgit v1.2.3-54-g00ecf (git 2.45.2) at 2024-11-01 00:31:48 +0000