diff options
| author | Michael Abed <michaelabed@gmail.com> | 2012-02-17 12:08:05 -0500 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-02-17 12:08:05 -0500 |
| commit | 70b77304f37d9681aa3bfa0eb57df0bcfd1aef81 (patch) | |
| tree | 48ab397b4072275dbc5a6b2f92a54d3c79e1fdea /planAhead_run_1 | |
| parent | 57738e75e221fe61a8f87270b430c0f1c0b8ead5 (diff) | |
| download | ec311-lab1-70b77304f37d9681aa3bfa0eb57df0bcfd1aef81.tar.gz ec311-lab1-70b77304f37d9681aa3bfa0eb57df0bcfd1aef81.tar.bz2 ec311-lab1-70b77304f37d9681aa3bfa0eb57df0bcfd1aef81.zip | |
Diffstat (limited to 'planAhead_run_1')
| -rwxr-xr-x | planAhead_run_1/lab1.data/cache/ALU_ngc_c04f956c.edif | 2404 | ||||
| -rwxr-xr-x | planAhead_run_1/lab1.data/constrs_1/designprops.xml | 29 | ||||
| -rwxr-xr-x | planAhead_run_1/lab1.data/constrs_1/fileset.xml | 20 | ||||
| -rwxr-xr-x | planAhead_run_1/lab1.data/constrs_1/usercols.xml | 4 | ||||
| -rwxr-xr-x | planAhead_run_1/lab1.data/runs/impl_1.psg | 18 | ||||
| -rwxr-xr-x | planAhead_run_1/lab1.data/runs/runs.xml | 5 | ||||
| -rwxr-xr-x | planAhead_run_1/lab1.data/sources_1/chipscope.xml | 6 | ||||
| -rwxr-xr-x | planAhead_run_1/lab1.data/sources_1/fileset.xml | 156 | ||||
| -rwxr-xr-x | planAhead_run_1/lab1.data/sources_1/ports.xml | 24 | ||||
| -rwxr-xr-x | planAhead_run_1/lab1.ppr | 1 | ||||
| -rwxr-xr-x | planAhead_run_1/planAhead.jou | 22 | ||||
| -rwxr-xr-x | planAhead_run_1/planAhead.log | 139 | ||||
| -rwxr-xr-x | planAhead_run_1/planAhead_run.log | 112 |
13 files changed, 2634 insertions, 306 deletions
diff --git a/planAhead_run_1/lab1.data/cache/ALU_ngc_c04f956c.edif b/planAhead_run_1/lab1.data/cache/ALU_ngc_c04f956c.edif new file mode 100755 index 0000000..0b84157 --- /dev/null +++ b/planAhead_run_1/lab1.data/cache/ALU_ngc_c04f956c.edif @@ -0,0 +1,2404 @@ +(edif ALU + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2012 2 16 18 17 18) + (program "Xilinx ngc2edif" (version "O.76xd")) + (author "Xilinx. Inc ") + (comment "This EDIF netlist is to be used within supported synthesis tools") + (comment "for determining resource/timing estimates of the design component") + (comment "represented by this netlist.") + (comment "Command line: -mdp2sp -w -secure ALU.ngc ALU.edif "))) + (external UNISIMS + (edifLevel 0) + (technology (numberDefinition)) + (cell GND + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port G + (direction OUTPUT) + ) + ) + ) + ) + (cell VCC + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port P + (direction OUTPUT) + ) + ) + ) + ) + (cell OR3 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell OR2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell INV + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell AND2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell AND4 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell NOR3 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell AND3 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell NAND4 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell NAND3 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell XNOR2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell OR4 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell NAND2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT6 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port I5 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell BUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell OR5 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell XOR2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell IBUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell OBUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + ) + + (library ALU_lib + (edifLevel 0) + (technology (numberDefinition)) + (cell (rename M4_1E_HXILINX_ALU_NO3_XLXI_4 "M4_1E_HXILINX_ALU") + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT) + ) + (port D1 + (direction INPUT) + ) + (port D2 + (direction INPUT) + ) + (port D3 + (direction INPUT) + ) + (port E + (direction INPUT) + ) + (port S0 + (direction INPUT) + ) + (port S1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + (contents + (instance Mmux_O11 + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx")) + ) + (net D0 + (joined + (portRef D0) + (portRef I4 (instanceRef Mmux_O11)) + ) + ) + (net D1 + (joined + (portRef D1) + (portRef I3 (instanceRef Mmux_O11)) + ) + ) + (net D2 + (joined + (portRef D2) + (portRef I5 (instanceRef Mmux_O11)) + ) + ) + (net D3 + (joined + (portRef D3) + (portRef I1 (instanceRef Mmux_O11)) + ) + ) + (net S0 + (joined + (portRef S0) + (portRef I0 (instanceRef Mmux_O11)) + ) + ) + (net S1 + (joined + (portRef S1) + (portRef I2 (instanceRef Mmux_O11)) + ) + ) + (net O + (joined + (portRef O) + (portRef O (instanceRef Mmux_O11)) + ) + ) + ) + ) + ) + (cell (rename M4_1E_HXILINX_ALU_NO2_XLXI_5 "M4_1E_HXILINX_ALU") + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT) + ) + (port D1 + (direction INPUT) + ) + (port D2 + (direction INPUT) + ) + (port D3 + (direction INPUT) + ) + (port E + (direction INPUT) + ) + (port S0 + (direction INPUT) + ) + (port S1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + (contents + (instance Mmux_O11 + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx")) + ) + (net D0 + (joined + (portRef D0) + (portRef I4 (instanceRef Mmux_O11)) + ) + ) + (net D1 + (joined + (portRef D1) + (portRef I3 (instanceRef Mmux_O11)) + ) + ) + (net D2 + (joined + (portRef D2) + (portRef I5 (instanceRef Mmux_O11)) + ) + ) + (net D3 + (joined + (portRef D3) + (portRef I1 (instanceRef Mmux_O11)) + ) + ) + (net S0 + (joined + (portRef S0) + (portRef I0 (instanceRef Mmux_O11)) + ) + ) + (net S1 + (joined + (portRef S1) + (portRef I2 (instanceRef Mmux_O11)) + ) + ) + (net O + (joined + (portRef O) + (portRef O (instanceRef Mmux_O11)) + ) + ) + ) + ) + ) + (cell (rename M4_1E_HXILINX_ALU_NO1_XLXI_6 "M4_1E_HXILINX_ALU") + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT) + ) + (port D1 + (direction INPUT) + ) + (port D2 + (direction INPUT) + ) + (port D3 + (direction INPUT) + ) + (port E + (direction INPUT) + ) + (port S0 + (direction INPUT) + ) + (port S1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + (contents + (instance Mmux_O11 + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx")) + ) + (net D0 + (joined + (portRef D0) + (portRef I4 (instanceRef Mmux_O11)) + ) + ) + (net D1 + (joined + (portRef D1) + (portRef I3 (instanceRef Mmux_O11)) + ) + ) + (net D2 + (joined + (portRef D2) + (portRef I5 (instanceRef Mmux_O11)) + ) + ) + (net D3 + (joined + (portRef D3) + (portRef I1 (instanceRef Mmux_O11)) + ) + ) + (net S0 + (joined + (portRef S0) + (portRef I0 (instanceRef Mmux_O11)) + ) + ) + (net S1 + (joined + (portRef S1) + (portRef I2 (instanceRef Mmux_O11)) + ) + ) + (net O + (joined + (portRef O) + (portRef O (instanceRef Mmux_O11)) + ) + ) + ) + ) + ) + (cell (rename M4_1E_HXILINX_ALU_XLXI_7 "M4_1E_HXILINX_ALU") + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT) + ) + (port D1 + (direction INPUT) + ) + (port D2 + (direction INPUT) + ) + (port D3 + (direction INPUT) + ) + (port E + (direction INPUT) + ) + (port S0 + (direction INPUT) + ) + (port S1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + (contents + (instance Mmux_O11 + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx")) + ) + (net D0 + (joined + (portRef D0) + (portRef I4 (instanceRef Mmux_O11)) + ) + ) + (net D1 + (joined + (portRef D1) + (portRef I3 (instanceRef Mmux_O11)) + ) + ) + (net D2 + (joined + (portRef D2) + (portRef I5 (instanceRef Mmux_O11)) + ) + ) + (net D3 + (joined + (portRef D3) + (portRef I1 (instanceRef Mmux_O11)) + ) + ) + (net S0 + (joined + (portRef S0) + (portRef I0 (instanceRef Mmux_O11)) + ) + ) + (net S1 + (joined + (portRef S1) + (portRef I2 (instanceRef Mmux_O11)) + ) + ) + (net O + (joined + (portRef O) + (portRef O (instanceRef Mmux_O11)) + ) + ) + ) + ) + ) + (cell ALU + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port A + (direction INPUT) + ) + (port B + (direction INPUT) + ) + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port S0 + (direction INPUT) + ) + (port S1 + (direction INPUT) + ) + (port AN0 + (direction OUTPUT) + ) + (port AN1 + (direction OUTPUT) + ) + (port AN2 + (direction OUTPUT) + ) + (port AN3 + (direction OUTPUT) + ) + (port a_out + (direction OUTPUT) + ) + (port b_out + (direction OUTPUT) + ) + (port c_out + (direction OUTPUT) + ) + (port d_out + (direction OUTPUT) + ) + (port e_out + (direction OUTPUT) + ) + (port f_out + (direction OUTPUT) + ) + (port g_out + (direction OUTPUT) + ) + (port sign + (direction OUTPUT) + ) + (designator "xc6slx16-3-csg324") + (property TYPE (string "ALU") (owner "Xilinx")) + (property SHREG_MIN_SIZE (string "2") (owner "Xilinx")) + (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 0) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "ALU_ALU") (owner "Xilinx")) + ) + (contents + (instance XST_GND + (viewRef view_1 (cellRef GND (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance XLXI_8 + (viewRef view_1 (cellRef VCC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_2 "XLXI_1/XLXI_8/XLXI_2") + (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_5 "XLXI_1/XLXI_8/XLXI_5") + (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_7 "XLXI_1/XLXI_8/XLXI_7") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_6 "XLXI_1/XLXI_8/XLXI_6") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_4 "XLXI_1/XLXI_8/XLXI_4") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_8 "XLXI_1/XLXI_8/XLXI_8") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_3 "XLXI_1/XLXI_8/XLXI_3") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_9 "XLXI_1/XLXI_8/XLXI_9") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_1 "XLXI_1/XLXI_8/XLXI_1") + (viewRef view_1 (cellRef AND4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_9_XLXI_10 "XLXI_1/XLXI_9/XLXI_10") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_9_XLXI_11 "XLXI_1/XLXI_9/XLXI_11") + (viewRef view_1 (cellRef NOR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_10_XLXI_2 "XLXI_1/XLXI_10/XLXI_2") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_10_XLXI_3 "XLXI_1/XLXI_10/XLXI_3") + (viewRef view_1 (cellRef NOR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_12_XLXI_7 "XLXI_1/XLXI_12/XLXI_7") + (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_12_XLXI_4 "XLXI_1/XLXI_12/XLXI_4") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_12_XLXI_5 "XLXI_1/XLXI_12/XLXI_5") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_12_XLXI_3 "XLXI_1/XLXI_12/XLXI_3") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_12_XLXI_2 "XLXI_1/XLXI_12/XLXI_2") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_12_XLXI_6 "XLXI_1/XLXI_12/XLXI_6") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_12_XLXI_1 "XLXI_1/XLXI_12/XLXI_1") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_2_XLXI_4 "XLXI_2/XLXI_2/XLXI_4") + (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_2_XLXI_2 "XLXI_2/XLXI_2/XLXI_2") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_2_XLXI_7 "XLXI_2/XLXI_2/XLXI_7") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_2_XLXI_5 "XLXI_2/XLXI_2/XLXI_5") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_2_XLXI_1 "XLXI_2/XLXI_2/XLXI_1") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_2_XLXI_6 "XLXI_2/XLXI_2/XLXI_6") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_2_XLXI_3 "XLXI_2/XLXI_2/XLXI_3") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_1_XLXI_4 "XLXI_2/XLXI_1/XLXI_4") + (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_1_XLXI_2 "XLXI_2/XLXI_1/XLXI_2") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_1_XLXI_7 "XLXI_2/XLXI_1/XLXI_7") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_1_XLXI_5 "XLXI_2/XLXI_1/XLXI_5") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_1_XLXI_1 "XLXI_2/XLXI_1/XLXI_1") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_1_XLXI_6 "XLXI_2/XLXI_1/XLXI_6") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_1_XLXI_3 "XLXI_2/XLXI_1/XLXI_3") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_17 "XLXI_2/XLXI_3/XLXI_17") + (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_4 "XLXI_2/XLXI_3/XLXI_4") + (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_15 "XLXI_2/XLXI_3/XLXI_15") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_2 "XLXI_2/XLXI_3/XLXI_2") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_7 "XLXI_2/XLXI_3/XLXI_7") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_16 "XLXI_2/XLXI_3/XLXI_16") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_14 "XLXI_2/XLXI_3/XLXI_14") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_5 "XLXI_2/XLXI_3/XLXI_5") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_1 "XLXI_2/XLXI_3/XLXI_1") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_13 "XLXI_2/XLXI_3/XLXI_13") + (viewRef view_1 (cellRef NAND4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_11 "XLXI_2/XLXI_3/XLXI_11") + (viewRef view_1 (cellRef AND4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_6 "XLXI_2/XLXI_3/XLXI_6") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_3 "XLXI_2/XLXI_3/XLXI_3") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_4_XLXI_4 "XLXI_2/XLXI_4/XLXI_4") + (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_4_XLXI_2 "XLXI_2/XLXI_4/XLXI_2") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_4_XLXI_3 "XLXI_2/XLXI_4/XLXI_3") + (viewRef view_1 (cellRef NAND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_4_XLXI_5 "XLXI_2/XLXI_4/XLXI_5") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_4_XLXI_1 "XLXI_2/XLXI_4/XLXI_1") + (viewRef view_1 (cellRef XNOR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_8_XLXI_8 "XLXI_3/XLXI_8/XLXI_8") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_8_XLXI_10 "XLXI_3/XLXI_8/XLXI_10") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_8_XLXI_9 "XLXI_3/XLXI_8/XLXI_9") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_8_XLXI_12 "XLXI_3/XLXI_8/XLXI_12") + (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_9_XLXI_4 "XLXI_3/XLXI_9/XLXI_4") + (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_9_XLXI_3 "XLXI_3/XLXI_9/XLXI_3") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_9_XLXI_5 "XLXI_3/XLXI_9/XLXI_5") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_9_XLXI_6 "XLXI_3/XLXI_9/XLXI_6") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_9_XLXI_1 "XLXI_3/XLXI_9/XLXI_1") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_9_XLXI_7 "XLXI_3/XLXI_9/XLXI_7") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_9_XLXI_2 "XLXI_3/XLXI_9/XLXI_2") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_10_XLXI_8 "XLXI_3/XLXI_10/XLXI_8") + (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_10_XLXI_9 "XLXI_3/XLXI_10/XLXI_9") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_10_XLXI_14 "XLXI_3/XLXI_10/XLXI_14") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_10_XLXI_10 "XLXI_3/XLXI_10/XLXI_10") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_10_XLXI_12 "XLXI_3/XLXI_10/XLXI_12") + (viewRef view_1 (cellRef NAND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_10_XLXI_11 "XLXI_3/XLXI_10/XLXI_11") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_12_XLXI_9 "XLXI_3/XLXI_12/XLXI_9") + (viewRef view_1 (cellRef NAND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_12_XLXI_13 "XLXI_3/XLXI_12/XLXI_13") + (viewRef view_1 (cellRef NOR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance XLXI_7 + (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_XLXI_7 (libraryRef ALU_lib))) + (property HU_SET (string "XLXI_7_3") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 1) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_XLXI_7") (owner "Xilinx")) + ) + (instance XLXI_6 + (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_NO1_XLXI_6 (libraryRef ALU_lib))) + (property HU_SET (string "XLXI_6_2") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 1) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 2) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_NO1_XLXI_6") (owner "Xilinx")) + ) + (instance XLXI_5 + (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_NO2_XLXI_5 (libraryRef ALU_lib))) + (property HU_SET (string "XLXI_5_1") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 2) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 3) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_NO2_XLXI_5") (owner "Xilinx")) + ) + (instance XLXI_4 + (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_NO3_XLXI_4 (libraryRef ALU_lib))) + (property HU_SET (string "XLXI_4_0") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 3) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 4) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_NO3_XLXI_4") (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_8 "XLXI_9/XLXI_8") + (viewRef view_1 (cellRef BUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_7 "XLXI_9/XLXI_7") + (viewRef view_1 (cellRef BUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_6 "XLXI_9/XLXI_6") + (viewRef view_1 (cellRef BUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_5 "XLXI_9/XLXI_5") + (viewRef view_1 (cellRef BUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_68 "XLXI_9/XLXI_68") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_69 "XLXI_9/XLXI_69") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_71 "XLXI_9/XLXI_71") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_70 "XLXI_9/XLXI_70") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_66 "XLXI_9/XLXI_66") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_73 "XLXI_9/XLXI_73") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_65 "XLXI_9/XLXI_65") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_67 "XLXI_9/XLXI_67") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_53 "XLXI_9/XLXI_53") + (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_57 "XLXI_9/XLXI_57") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_43 "XLXI_9/XLXI_43") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_52 "XLXI_9/XLXI_52") + (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_49 "XLXI_9/XLXI_49") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_44 "XLXI_9/XLXI_44") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_32 "XLXI_9/XLXI_32") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_60 "XLXI_9/XLXI_60") + (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_58 "XLXI_9/XLXI_58") + (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_41 "XLXI_9/XLXI_41") + (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_72 "XLXI_9/XLXI_72") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_34 "XLXI_9/XLXI_34") + (viewRef view_1 (cellRef OR5 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_47 "XLXI_9/XLXI_47") + (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_40 "XLXI_9/XLXI_40") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_63 "XLXI_9/XLXI_63") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_62 "XLXI_9/XLXI_62") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_50 "XLXI_9/XLXI_50") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_48 "XLXI_9/XLXI_48") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_45 "XLXI_9/XLXI_45") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_39 "XLXI_9/XLXI_39") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_33 "XLXI_9/XLXI_33") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_31 "XLXI_9/XLXI_31") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_61 "XLXI_9/XLXI_61") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_56 "XLXI_9/XLXI_56") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_54 "XLXI_9/XLXI_54") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_51 "XLXI_9/XLXI_51") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_38 "XLXI_9/XLXI_38") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_30 "XLXI_9/XLXI_30") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_64 "XLXI_9/XLXI_64") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_55 "XLXI_9/XLXI_55") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_46 "XLXI_9/XLXI_46") + (viewRef view_1 (cellRef XOR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_42 "XLXI_9/XLXI_42") + (viewRef view_1 (cellRef XNOR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_37 "XLXI_9/XLXI_37") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_35 "XLXI_9/XLXI_35") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename A_IBUF_renamed_0 "A_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename B_IBUF_renamed_1 "B_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename C_IBUF_renamed_2 "C_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename D_IBUF_renamed_3 "D_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename S0_IBUF_renamed_4 "S0_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename S1_IBUF_renamed_5 "S1_IBUF") + (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename AN0_OBUF_renamed_6 "AN0_OBUF") + (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename AN1_OBUF_renamed_7 "AN1_OBUF") + (viewRef view_1 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O (instanceRef XLXI_2_XLXI_1_XLXI_2)) + ) + ) + (net (rename XLXI_2_XLXI_1_XLXN_7 "XLXI_2/XLXI_1/XLXN_7") + (joined + (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_7)) + (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_3)) + ) + ) + (net (rename XLXI_2_XLXI_1_XLXN_5 "XLXI_2/XLXI_1/XLXN_5") + (joined + (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_2)) + (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_5)) + ) + ) + (net (rename XLXI_2_XLXI_1_XLXN_1 "XLXI_2/XLXI_1/XLXN_1") + (joined + (portRef I2 (instanceRef XLXI_2_XLXI_1_XLXI_4)) + (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_1)) + ) + ) + (net (rename XLXI_2_XLXI_1_XLXN_6 "XLXI_2/XLXI_1/XLXN_6") + (joined + (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_2)) + (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_6)) + ) + ) + (net (rename XLXI_2_XLXI_1_XLXN_3 "XLXI_2/XLXI_1/XLXN_3") + (joined + (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_4)) + (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_3)) + ) + ) + (net (rename XLXI_2_XLXI_3_XLXN_21 "XLXI_2/XLXI_3/XLXN_21") + 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(joined + (portRef I2 (instanceRef XLXI_3_XLXI_9_XLXI_4)) + (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_1)) + ) + ) + (net (rename XLXI_3_XLXI_9_XLXN_6 "XLXI_3/XLXI_9/XLXN_6") + (joined + (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_1)) + (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_7)) + ) + ) + (net (rename XLXI_3_XLXI_9_XLXN_1 "XLXI_3/XLXI_9/XLXN_1") + (joined + (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_4)) + (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_2)) + ) + ) + (net (rename XLXI_3_XLXI_10_XLXN_35 "XLXI_3/XLXI_10/XLXN_35") + (joined + (portRef I3 (instanceRef XLXI_3_XLXI_10_XLXI_8)) + (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_9)) + ) + ) + (net (rename XLXI_3_XLXI_10_XLXN_44 "XLXI_3/XLXI_10/XLXN_44") + (joined + (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_9)) + (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_14)) + (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_10)) + (portRef I2 (instanceRef XLXI_3_XLXI_10_XLXI_12)) + (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_11)) + ) + ) + (net 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XLXI_9_XLXI_30)) + (portRef I4 (instanceRef XLXI_9_XLXI_34)) + ) + ) + (net (rename XLXI_9_XLXN_148 "XLXI_9/XLXN_148") + (joined + (portRef O (instanceRef XLXI_9_XLXI_64)) + (portRef I0 (instanceRef XLXI_9_XLXI_60)) + ) + ) + (net (rename XLXI_9_XLXN_129 "XLXI_9/XLXN_129") + (joined + (portRef O (instanceRef XLXI_9_XLXI_55)) + (portRef I2 (instanceRef XLXI_9_XLXI_58)) + ) + ) + (net (rename XLXI_9_XLXN_105 "XLXI_9/XLXN_105") + (joined + (portRef O (instanceRef XLXI_9_XLXI_46)) + (portRef I2 (instanceRef XLXI_9_XLXI_47)) + ) + ) + (net (rename XLXI_9_XLXN_91 "XLXI_9/XLXN_91") + (joined + (portRef O (instanceRef XLXI_9_XLXI_42)) + (portRef I3 (instanceRef XLXI_9_XLXI_41)) + ) + ) + (net (rename XLXI_9_A_BAR "XLXI_9/A_BAR") + (joined + (portRef O (instanceRef XLXI_9_XLXI_37)) + (portRef I2 (instanceRef XLXI_9_XLXI_54)) + (portRef I2 (instanceRef XLXI_9_XLXI_56)) + (portRef I0 (instanceRef XLXI_9_XLXI_31)) + (portRef I0 (instanceRef XLXI_9_XLXI_45)) + (portRef I (instanceRef XLXI_9_XLXI_72)) + ) + ) + (net (rename XLXI_9_XLXN_65 "XLXI_9/XLXN_65") + (joined + (portRef O (instanceRef XLXI_9_XLXI_35)) + (portRef I0 (instanceRef XLXI_9_XLXI_34)) + ) + ) + (net A + (joined + (portRef A) + (portRef I (instanceRef A_IBUF_renamed_0)) + ) + ) + (net B + (joined + (portRef B) + (portRef I (instanceRef B_IBUF_renamed_1)) + ) + ) + (net C + (joined + (portRef C) + (portRef I (instanceRef C_IBUF_renamed_2)) + ) + ) + (net D + (joined + (portRef D) + (portRef I (instanceRef D_IBUF_renamed_3)) + ) + ) + (net S0 + (joined + (portRef S0) + (portRef I (instanceRef S0_IBUF_renamed_4)) + ) + ) + (net S1 + (joined + (portRef S1) + (portRef I (instanceRef S1_IBUF_renamed_5)) + ) + ) + (net AN0 + (joined + (portRef AN0) + (portRef O (instanceRef AN0_OBUF_renamed_6)) + ) + ) + (net AN1 + (joined + (portRef AN1) + (portRef O (instanceRef AN1_OBUF_renamed_7)) + ) + ) + (net AN2 + (joined + (portRef AN2) + (portRef O (instanceRef AN2_OBUF_renamed_8)) + ) + ) + (net AN3 + (joined + (portRef AN3) + (portRef O (instanceRef AN3_OBUF_renamed_9)) + ) + ) + (net a_out + (joined + (portRef a_out) + (portRef O (instanceRef a_out_OBUF_renamed_10)) + ) + ) + (net b_out + (joined + (portRef b_out) + (portRef O (instanceRef b_out_OBUF_renamed_11)) + ) + ) + (net c_out + (joined + (portRef c_out) + (portRef O (instanceRef c_out_OBUF_renamed_12)) + ) + ) + (net d_out + (joined + (portRef d_out) + (portRef O (instanceRef d_out_OBUF_renamed_13)) + ) + ) + (net e_out + (joined + (portRef e_out) + (portRef O (instanceRef e_out_OBUF_renamed_14)) + ) + ) + (net f_out + (joined + (portRef f_out) + (portRef O (instanceRef f_out_OBUF_renamed_15)) + ) + ) + (net g_out + (joined + (portRef g_out) + (portRef O (instanceRef g_out_OBUF_renamed_16)) + ) + ) + (net sign + (joined + (portRef sign) + (portRef O (instanceRef sign_OBUF_renamed_17)) + ) + ) + ) + ) + ) + ) + + (design ALU + (cellRef ALU + (libraryRef ALU_lib) + ) + (property PART (string "xc6slx16-3-csg324") (owner "Xilinx")) + ) +) + diff --git a/planAhead_run_1/lab1.data/constrs_1/designprops.xml b/planAhead_run_1/lab1.data/constrs_1/designprops.xml new file mode 100755 index 0000000..ae00c39 --- /dev/null +++ b/planAhead_run_1/lab1.data/constrs_1/designprops.xml @@ -0,0 +1,29 @@ +<?xml version="1.0"?>
+<Compat Version="1" Minor="4">
+ <CompatParts>
+ </CompatParts>
+ <ConfigModes>
+ <Mode Id="JTAG"/>
+ </ConfigModes>
+ <PortProps>
+ <Port Name="A" OffChipTerm="NONE"/>
+ <Port Name="B" OffChipTerm="NONE"/>
+ <Port Name="C" OffChipTerm="NONE"/>
+ <Port Name="D" OffChipTerm="NONE"/>
+ <Port Name="S0" OffChipTerm="NONE"/>
+ <Port Name="S1" OffChipTerm="NONE"/>
+ <Port Name="AN0" OffChipTerm="FP_VTT_50"/>
+ <Port Name="AN1" OffChipTerm="FP_VTT_50"/>
+ <Port Name="AN2" OffChipTerm="FP_VTT_50"/>
+ <Port Name="AN3" OffChipTerm="FP_VTT_50"/>
+ <Port Name="a_out" OffChipTerm="FP_VTT_50"/>
+ <Port Name="b_out" OffChipTerm="FP_VTT_50"/>
+ <Port Name="c_out" OffChipTerm="FP_VTT_50"/>
+ <Port Name="d_out" OffChipTerm="FP_VTT_50"/>
+ <Port Name="e_out" OffChipTerm="FP_VTT_50"/>
+ <Port Name="f_out" OffChipTerm="FP_VTT_50"/>
+ <Port Name="g_out" OffChipTerm="FP_VTT_50"/>
+ <Port Name="sign" OffChipTerm="FP_VTT_50"/>
+ </PortProps>
+</Compat>
+
diff --git a/planAhead_run_1/lab1.data/constrs_1/fileset.xml b/planAhead_run_1/lab1.data/constrs_1/fileset.xml index 80984cf..6fa147b 100755 --- a/planAhead_run_1/lab1.data/constrs_1/fileset.xml +++ b/planAhead_run_1/lab1.data/constrs_1/fileset.xml @@ -15,6 +15,26 @@ Val="1"/>
</FileInfo>
</File>
+ <File Path="$PDATADIR/constrs_1/designprops.xml">
+ <FileInfo SFType="CompatPartsDb">
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <File Path="$PDATADIR/constrs_1/usercols.xml">
+ <FileInfo SFType="UserColsDb">
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
<Config>
<Option Name="TargetConstrsFile"
Val="$PPRDIR/../ALU.ucf"/>
diff --git a/planAhead_run_1/lab1.data/constrs_1/usercols.xml b/planAhead_run_1/lab1.data/constrs_1/usercols.xml new file mode 100755 index 0000000..b2e369a --- /dev/null +++ b/planAhead_run_1/lab1.data/constrs_1/usercols.xml @@ -0,0 +1,4 @@ +<?xml version="1.0"?>
+<UserColInfo Version="1" Minor="0">
+</UserColInfo>
+
diff --git a/planAhead_run_1/lab1.data/runs/impl_1.psg b/planAhead_run_1/lab1.data/runs/impl_1.psg new file mode 100755 index 0000000..43196a2 --- /dev/null +++ b/planAhead_run_1/lab1.data/runs/impl_1.psg @@ -0,0 +1,18 @@ +<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+ <StratHandle Name="ISE Defaults" Flow="ISE13">
+ <Desc>ISE Defaults, including packing registers in IOs off</Desc>
+ </StratHandle>
+ <Step Id="ngdbuild">
+ </Step>
+ <Step Id="map">
+ <Option Id="FFPackEnum">3</Option>
+ </Step>
+ <Step Id="par">
+ </Step>
+ <Step Id="trce">
+ </Step>
+ <Step Id="xdl">
+ </Step>
+</Strategy>
+
diff --git a/planAhead_run_1/lab1.data/runs/runs.xml b/planAhead_run_1/lab1.data/runs/runs.xml new file mode 100755 index 0000000..2651a01 --- /dev/null +++ b/planAhead_run_1/lab1.data/runs/runs.xml @@ -0,0 +1,5 @@ +<?xml version="1.0"?>
+<Runs Version="1" Minor="8">
+ <Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc6slx16csg324-3" ConstrsSet="constrs_1" State="current"/>
+</Runs>
+
diff --git a/planAhead_run_1/lab1.data/sources_1/chipscope.xml b/planAhead_run_1/lab1.data/sources_1/chipscope.xml new file mode 100755 index 0000000..af5cfeb --- /dev/null +++ b/planAhead_run_1/lab1.data/sources_1/chipscope.xml @@ -0,0 +1,6 @@ +<?xml version="1.0"?>
+<ChipScope Version="1" Minor="3">
+ <UnassignedNets>
+ </UnassignedNets>
+</ChipScope>
+
diff --git a/planAhead_run_1/lab1.data/sources_1/fileset.xml b/planAhead_run_1/lab1.data/sources_1/fileset.xml index 8ada118..c8f890f 100755 --- a/planAhead_run_1/lab1.data/sources_1/fileset.xml +++ b/planAhead_run_1/lab1.data/sources_1/fileset.xml @@ -4,8 +4,8 @@ <FileSet Name="sources_1"
Type="DesignSrcs"
RelSrcDir="$PSRCDIR/sources_1">
- <Filter Type="Srcs"/>
- <File Path="$PPRDIR/../Negate_2.vf">
+ <Filter Type="EDIFSrcs"/>
+ <File Path="$PPRDIR/../ALU.ngc">
<FileInfo>
<Attr Name="UsedInSynthesis"
Val="1"/>
@@ -15,58 +15,8 @@ Val="1"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../Negate_1.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Negate_0.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Modulo_3.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Modulo_1.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Modulo_0.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Divide_3.vf">
- <FileInfo>
+ <File Path="$PDATADIR/sources_1/ports.xml">
+ <FileInfo SFType="PortsDb">
<Attr Name="UsedInSynthesis"
Val="1"/>
<Attr Name="UsedInImplementation"
@@ -75,88 +25,8 @@ Val="1"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../Divide_2.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Divide_1.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Divide_0.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../sev_seg_disp.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Negate_3.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Modulo.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Divide.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../ALU.vf">
- <FileInfo>
- <Attr Name="UsedInSynthesis"
- Val="1"/>
- <Attr Name="UsedInImplementation"
- Val="1"/>
- <Attr Name="UsedInSimulation"
- Val="1"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../Negate.vf">
- <FileInfo>
+ <File Path="$PDATADIR/sources_1/chipscope.xml">
+ <FileInfo SFType="ChipscopeDb">
<Attr Name="UsedInSynthesis"
Val="1"/>
<Attr Name="UsedInImplementation"
@@ -167,15 +37,13 @@ </File>
<Config>
<Option Name="DesignMode"
- Val="RTL"/>
+ Val="GateLvl"/>
+ <Option Name="GateLvlMode"
+ Val="EDIF"/>
<Option Name="TopModule"
- Val="Negate"/>
- <Option Name="TopLib"
- Val="work"/>
- <Option Name="TopRTLFile"
- Val="$PPRDIR/../Negate.vf"/>
- <Option Name="TopAutoSet"
- Val="TRUE"/>
+ Val="ALU"/>
+ <Option Name="TopFile"
+ Val="$PPRDIR/../ALU.ngc"/>
</Config>
</FileSet>
</DARoots>
diff --git a/planAhead_run_1/lab1.data/sources_1/ports.xml b/planAhead_run_1/lab1.data/sources_1/ports.xml new file mode 100755 index 0000000..99a5439 --- /dev/null +++ b/planAhead_run_1/lab1.data/sources_1/ports.xml @@ -0,0 +1,24 @@ +<?xml version="1.0"?>
+<Interface Version="1" Minor="1">
+ <Ifc Id="ROOT" Top="1">
+ <Port Id="A" Dir="IN"/>
+ <Port Id="B" Dir="IN"/>
+ <Port Id="C" Dir="IN"/>
+ <Port Id="D" Dir="IN"/>
+ <Port Id="S0" Dir="IN"/>
+ <Port Id="S1" Dir="IN"/>
+ <Port Id="AN0" Dir="OUT"/>
+ <Port Id="AN1" Dir="OUT"/>
+ <Port Id="AN2" Dir="OUT"/>
+ <Port Id="AN3" Dir="OUT"/>
+ <Port Id="a_out" Dir="OUT"/>
+ <Port Id="b_out" Dir="OUT"/>
+ <Port Id="c_out" Dir="OUT"/>
+ <Port Id="d_out" Dir="OUT"/>
+ <Port Id="e_out" Dir="OUT"/>
+ <Port Id="f_out" Dir="OUT"/>
+ <Port Id="g_out" Dir="OUT"/>
+ <Port Id="sign" Dir="OUT"/>
+ </Ifc>
+</Interface>
+
diff --git a/planAhead_run_1/lab1.ppr b/planAhead_run_1/lab1.ppr index 22481f8..6081e20 100755 --- a/planAhead_run_1/lab1.ppr +++ b/planAhead_run_1/lab1.ppr @@ -2,6 +2,7 @@ <Project Version="4" Minor="27">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
+ <RunSet Dir="runs" File="runs.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
<Config>
diff --git a/planAhead_run_1/planAhead.jou b/planAhead_run_1/planAhead.jou index 245a6d0..1ae8ec4 100755 --- a/planAhead_run_1/planAhead.jou +++ b/planAhead_run_1/planAhead.jou @@ -1,12 +1,20 @@ #----------------------------------------------------------- # PlanAhead v13.3 (64-bit) # Build 147507 by hdbuild on Tue Oct 4 19:13:50 MDT 2011 -# Start of session at: Wed Feb 15 15:13:16 2012 -# Process ID: 3932 -# Log file: X:/My Documents/ec311/lab1/planAhead_run_1/planAhead.log -# Journal file: X:/My Documents/ec311/lab1/planAhead_run_1/planAhead.jou +# Start of session at: Thu Feb 16 18:17:07 2012 +# Process ID: 1252 +# Log file: X:/My Documents/ec311/ec311-lab1/planAhead_run_1/planAhead.log +# Journal file: X:/My Documents/ec311/ec311-lab1/planAhead_run_1/planAhead.jou #----------------------------------------------------------- start_gui -source {X:/My Documents/ec311/lab1/pa.fromHdl.tcl} -exit -stop_gui +source {X:/My Documents/ec311/ec311-lab1/pa.fromNetlist.tcl} +startgroup +set_property loc PAD2 [get_ports A] +endgroup +startgroup +set_property loc PAD30 [get_ports D] +endgroup +startgroup +set_property loc PAD29 [get_ports C] +endgroup +save_design diff --git a/planAhead_run_1/planAhead.log b/planAhead_run_1/planAhead.log index fda2b18..19f24a3 100755 --- a/planAhead_run_1/planAhead.log +++ b/planAhead_run_1/planAhead.log @@ -1,83 +1,48 @@ #----------------------------------------------------------- # PlanAhead v13.3 (64-bit) # Build 147507 by hdbuild on Tue Oct 4 19:13:50 MDT 2011 -# Start of session at: Wed Feb 15 15:13:16 2012 -# Process ID: 3932 -# Log file: X:/My Documents/ec311/lab1/planAhead_run_1/planAhead.log -# Journal file: X:/My Documents/ec311/lab1/planAhead_run_1/planAhead.jou +# Start of session at: Thu Feb 16 18:17:07 2012 +# Process ID: 1252 +# Log file: X:/My Documents/ec311/ec311-lab1/planAhead_run_1/planAhead.log +# Journal file: X:/My Documents/ec311/ec311-lab1/planAhead_run_1/planAhead.jou #----------------------------------------------------------- INFO: [Common-78] Attempting to get a license: PlanAhead INFO: [Common-82] Got a license: PlanAhead INFO: [Device-25] Loading parts and site information from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\arch.xmlParsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml] Finished parsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml] start_gui -source {X:/My Documents/ec311/lab1/pa.fromHdl.tcl} -# create_project -name lab1 -dir "X:/My Documents/ec311/lab1/planAhead_run_1" -part xc6slx16csg324-3 +source {X:/My Documents/ec311/ec311-lab1/pa.fromNetlist.tcl} +# create_project -name lab1 -dir "X:/My Documents/ec311/ec311-lab1/planAhead_run_1" -part xc6slx16csg324-3 Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml]. Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml]. Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml]. Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml]. Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml]. Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml]. -# set_param project.pinAheadLayout yes -# set srcset [get_property srcset [current_run -impl]] -# set_property top ALU $srcset +# set_property design_mode GateLvl [get_property srcset [current_run -impl]] +# set_property edif_top_file "X:/My Documents/ec311/ec311-lab1/ALU.ngc" [ get_property srcset [ current_run ] ] +# add_files -norecurse { {X:/My Documents/ec311/ec311-lab1} } +# set_param project.pinAheadLayout yes # set_property target_constrs_file "ALU.ucf" [current_fileset -constrset] -Adding file 'X:\My Documents\ec311\lab1\ALU.ucf' to fileset 'constrs_1' -CRITICAL WARNING: [Designutils-735] The top module "ALU" specified for this project can not be validated. The current project is using automatic hierarchy update mode, and hence a new suitable replacement top will be automatically selected. If this is not desired, please change the hierarchy update mode to one of the manual compile order modes first, and then set top to any desired value. -# set hdlfile [add_files [list {Negate_3.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile -# set hdlfile [add_files [list {Negate_2.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile -# set hdlfile [add_files [list {Negate_1.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile -# set hdlfile [add_files [list {Negate_0.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile -# set hdlfile [add_files [list {Modulo_3.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile -# set hdlfile [add_files [list {Modulo_1.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile -# set hdlfile [add_files [list {Modulo_0.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile -# set hdlfile [add_files [list {Divide_3.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile -# set hdlfile [add_files [list {Divide_2.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile -# set hdlfile [add_files [list {Divide_1.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile -# set hdlfile [add_files [list {Divide_0.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile -# set hdlfile [add_files [list {sev_seg_disp.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile -# set hdlfile [add_files [list {Negate.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile -# set hdlfile [add_files [list {Modulo.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile -# set hdlfile [add_files [list {Divide.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile -# set hdlfile [add_files [list {ALU.vf}]] -# set_property file_type Verilog $hdlfile -# set_property library work $hdlfile +Adding file 'X:\My Documents\ec311\ec311-lab1\ALU.ucf' to fileset 'constrs_1' # add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]] -# open_rtl_design -part xc6slx16csg324-3 -INFO: [PlanAhead-58] Using Verific elaboration -Parsing VHDL file "C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify -Analyzing Verilog file "X:\My Documents\ec311\lab1\Negate.vf" into library work +# open_netlist_design +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +Design is defaulting to part: xc6slx16csg324-3 +Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91624 kilobytes
+
+Parsing EDIF File [.\planAhead_run_1\lab1.data\cache\ALU_ngc_c04f956c.edif] +Finished Parsing EDIF File [.\planAhead_run_1\lab1.data\cache\ALU_ngc_c04f956c.edif] Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml... @@ -85,30 +50,26 @@ Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spart Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml Loading device configuration modes from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/ConfigModes.xml Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml -Parsing UCF File [X:\My Documents\ec311\lab1\ALU.ucf] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'A' [X:\My Documents\ec311\lab1\ALU.ucf:4] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'AN0' [X:\My Documents\ec311\lab1\ALU.ucf:5] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'AN1' [X:\My Documents\ec311\lab1\ALU.ucf:6] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'AN2' [X:\My Documents\ec311\lab1\ALU.ucf:7] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'AN3' [X:\My Documents\ec311\lab1\ALU.ucf:8] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'B' [X:\My Documents\ec311\lab1\ALU.ucf:9] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'C' [X:\My Documents\ec311\lab1\ALU.ucf:10] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'D' [X:\My Documents\ec311\lab1\ALU.ucf:11] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'S0' [X:\My Documents\ec311\lab1\ALU.ucf:12] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'S1' [X:\My Documents\ec311\lab1\ALU.ucf:13] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'a_out' [X:\My Documents\ec311\lab1\ALU.ucf:14] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'b_out' [X:\My Documents\ec311\lab1\ALU.ucf:15] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'c_out' [X:\My Documents\ec311\lab1\ALU.ucf:16] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'd_out' [X:\My Documents\ec311\lab1\ALU.ucf:17] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'e_out' [X:\My Documents\ec311\lab1\ALU.ucf:18] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'f_out' [X:\My Documents\ec311\lab1\ALU.ucf:19] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'g_out' [X:\My Documents\ec311\lab1\ALU.ucf:20] -CRITICAL WARNING: [Constraints-11] Could not find net or pin 'sign' [X:\My Documents\ec311\lab1\ALU.ucf:21] -Finished Parsing UCF File [X:\My Documents\ec311\lab1\ALU.ucf] -INFO: [Designutils-20] Invalid constraints found, use command 'write_ucf -constraints invalid <file>' to save all the invalid constraints to a file +Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf] +Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf] INFO: [PlanAhead-566] Unisim Transformation Summary: -No Unisim elements were transformed.open_rtl_design: Time (s): 13.288w. Memory (MB): 788.289p 223.703g -exit -stop_gui -INFO: [PlanAhead-261] Exiting PlanAhead... -INFO: [Common-83] Releasing license: PlanAhead +No Unisim elements were transformed.open_netlist_design: Time (s): 13.291w. Memory (MB): 734.672p 186.648g +startgroup +startgroup +set_property loc PAD2 [get_ports A] +set_property loc PAD2 [get_ports A] +endgroup +endgroup +startgroup +startgroup +set_property loc PAD30 [get_ports D] +set_property loc PAD30 [get_ports D] +endgroup +endgroup +startgroup +startgroup +set_property loc PAD29 [get_ports C] +set_property loc PAD29 [get_ports C] +endgroup +endgroup +save_design diff --git a/planAhead_run_1/planAhead_run.log b/planAhead_run_1/planAhead_run.log index bae2bd8..9d4c5fa 100755 --- a/planAhead_run_1/planAhead_run.log +++ b/planAhead_run_1/planAhead_run.log @@ -9,72 +9,38 @@ INFO: [Device-25] Loading parts and site information from C:/Xilinx/13.3/ISE_DS/ Finished parsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
start_gui
starting gui ...
-source {X:/My Documents/ec311/lab1/pa.fromHdl.tcl}
-# create_project -name lab1 -dir "X:/My Documents/ec311/lab1/planAhead_run_1" -part xc6slx16csg324-3
+source {X:/My Documents/ec311/ec311-lab1/pa.fromNetlist.tcl}
+# create_project -name lab1 -dir "X:/My Documents/ec311/ec311-lab1/planAhead_run_1" -part xc6slx16csg324-3
Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
-# set_param project.pinAheadLayout yes
-# set srcset [get_property srcset [current_run -impl]]
-# set_property top ALU $srcset
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "X:/My Documents/ec311/ec311-lab1/ALU.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {X:/My Documents/ec311/ec311-lab1} }
+# set_param project.pinAheadLayout yes
# set_property target_constrs_file "ALU.ucf" [current_fileset -constrset]
-Adding file 'X:\My Documents\ec311\lab1\ALU.ucf' to fileset 'constrs_1'
-# set hdlfile [add_files [list {Negate_3.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate_2.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate_1.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate_0.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo_3.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo_1.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo_0.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_3.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_2.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_1.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_0.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {sev_seg_disp.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {ALU.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
+Adding file 'X:\My Documents\ec311\ec311-lab1\ALU.ucf' to fileset 'constrs_1'
# add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]]
-# open_rtl_design -part xc6slx16csg324-3
-INFO: [PlanAhead-58] Using Verific elaboration
-Parsing VHDL file "C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify
-Analyzing Verilog file "X:\My Documents\ec311\lab1\Negate.vf" into library work
+# open_netlist_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to part: xc6slx16csg324-3
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91624 kilobytes
+
+Parsing EDIF File [.\planAhead_run_1\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_1\lab1.data\cache\ALU_ngc_c04f956c.edif]
Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
@@ -82,12 +48,26 @@ Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spart Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
Loading device configuration modes from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/ConfigModes.xml
Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
-Parsing UCF File [X:\My Documents\ec311\lab1\ALU.ucf]
-Finished Parsing UCF File [X:\My Documents\ec311\lab1\ALU.ucf]
-INFO: [Designutils-20] Invalid constraints found, use command 'write_ucf -constraints invalid <file>' to save all the invalid constraints to a file
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
INFO: [PlanAhead-566] Unisim Transformation Summary:
-No Unisim elements were transformed.open_rtl_design: Time (s): 13.288w. Memory (MB): 788.289p 223.703g
-exit
-stop_gui
-INFO: [PlanAhead-261] Exiting PlanAhead...
-INFO: [Common-83] Releasing license: PlanAhead
+No Unisim elements were transformed.open_netlist_design: Time (s): 13.291w. Memory (MB): 734.672p 186.648g
+startgroup
+startgroup
+set_property loc PAD2 [get_ports A]
+set_property loc PAD2 [get_ports A]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD30 [get_ports D]
+set_property loc PAD30 [get_ports D]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD29 [get_ports C]
+set_property loc PAD29 [get_ports C]
+endgroup
+endgroup
+save_design
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