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-rwxr-xr-xALU.par12
1 files changed, 6 insertions, 6 deletions
diff --git a/ALU.par b/ALU.par
index 4b07d80..3adecd5 100755
--- a/ALU.par
+++ b/ALU.par
@@ -1,7 +1,7 @@
Release 13.3 par O.76xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
-ECE-PHO115-09:: Wed Feb 15 15:16:04 2012
+ECE-PHO115-08:: Thu Feb 16 19:53:08 2012
par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf
@@ -36,7 +36,7 @@ Slice Logic Utilization:
Number used as Memory: 0 out of 2,176 0%
Slice Logic Distribution:
- Number of occupied Slices: 5 out of 2,278 1%
+ Number of occupied Slices: 6 out of 2,278 1%
Nummber of MUXCYs used: 0 out of 4,556 0%
Number of LUT Flip Flop pairs used: 13
Number with an unused Flip Flop: 13 out of 13 100%
@@ -92,9 +92,9 @@ Phase 1 : 67 unrouted; REAL time: 5 secs
Phase 2 : 67 unrouted; REAL time: 5 secs
-Phase 3 : 49 unrouted; REAL time: 6 secs
+Phase 3 : 25 unrouted; REAL time: 6 secs
-Phase 4 : 49 unrouted; (Par is working to improve performance) REAL time: 7 secs
+Phase 4 : 25 unrouted; (Par is working to improve performance) REAL time: 7 secs
Updating file: ALU.ncd with current fully routed design.
@@ -129,10 +129,10 @@ Generating Pad Report.
All signals are completely routed.
-Total REAL time to PAR completion: 19 secs
+Total REAL time to PAR completion: 16 secs
Total CPU time to PAR completion: 7 secs
-Peak Memory Usage: 307 MB
+Peak Memory Usage: 308 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.