diff options
Diffstat (limited to 'ALU.syr')
| -rwxr-xr-x | ALU.syr | 169 |
1 files changed, 79 insertions, 90 deletions
@@ -4,13 +4,13 @@ Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.12 secs +Total CPU time to Xst completion: 0.11 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.13 secs +Total CPU time to Xst completion: 0.11 secs --> Reading design: ALU.prj @@ -105,48 +105,48 @@ Slice Utilization Ratio Delta : 5 ========================================================================= * HDL Parsing * ========================================================================= -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_3.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_3.vf" into library work Parsing module <Negate_3>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_2.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_2.vf" into library work Parsing module <Negate_2>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_1.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_1.vf" into library work Parsing module <Negate_1>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_0.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_0.vf" into library work Parsing module <Negate_0>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo_3.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo_3.vf" into library work Parsing module <Modulo_3>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo_1.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo_1.vf" into library work Parsing module <Modulo_1>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo_0.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo_0.vf" into library work Parsing module <Modulo_0>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_3.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_3.vf" into library work Parsing module <Divide_3>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_2.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_2.vf" into library work Parsing module <Divide_2>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_1.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_1.vf" into library work Parsing module <Divide_1>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_0.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_0.vf" into library work Parsing module <Divide_0>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\sev_seg_disp.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\sev_seg_disp.vf" into library work Parsing module <sev_seg_disp>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate.vf" into library work Parsing module <Negate_3_MUSER_Negate>. Parsing module <Negate_1_MUSER_Negate>. Parsing module <Negate_2_MUSER_Negate>. Parsing module <Negate_0_MUSER_Negate>. Parsing module <Negate>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo.vf" into library work Parsing module <Modulo_0_MUSER_Modulo>. Parsing module <Modulo_1_MUSER_Modulo>. Parsing module <Modulo_3_MUSER_Modulo>. Parsing module <Modulo>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide.vf" into library work Parsing module <Divide_1_MUSER_Divide>. Parsing module <Divide_2_MUSER_Divide>. Parsing module <Divide_3_MUSER_Divide>. Parsing module <Divide_0_MUSER_Divide>. Parsing module <Divide>. -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\ALU.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\ALU.vf" into library work Parsing module <M4_1E_HXILINX_ALU>. Parsing module <sev_seg_disp_MUSER_ALU>. Parsing module <Negate_3_MUSER_ALU>. @@ -187,28 +187,22 @@ Elaborating module <INV>. Elaborating module <Divide_2_MUSER_ALU>. -Elaborating module <AND3>. - Elaborating module <Divide_3_MUSER_ALU>. -Elaborating module <NOR3>. - Elaborating module <Divide_0_MUSER_ALU>. +Elaborating module <AND3>. + Elaborating module <Modulo_MUSER_ALU>. Elaborating module <Modulo_3_MUSER_ALU>. Elaborating module <Modulo_1_MUSER_ALU>. -Elaborating module <NAND4>. +Elaborating module <OR5>. Elaborating module <Modulo_0_MUSER_ALU>. -Elaborating module <XNOR2>. - -Elaborating module <NAND3>. - Elaborating module <Negate_MUSER_ALU>. Elaborating module <Negate_0_MUSER_ALU>. @@ -217,9 +211,9 @@ Elaborating module <Negate_1_MUSER_ALU>. Elaborating module <Negate_2_MUSER_ALU>. -Elaborating module <Negate_3_MUSER_ALU>. +Elaborating module <OR4>. -Elaborating module <NAND2>. +Elaborating module <Negate_3_MUSER_ALU>. Elaborating module <M4_1E_HXILINX_ALU>. @@ -231,9 +225,7 @@ Elaborating module <BUF>. Elaborating module <GND>. -Elaborating module <OR5>. - -Elaborating module <OR4>. +Elaborating module <XNOR2>. Elaborating module <XOR2>. @@ -242,7 +234,7 @@ Elaborating module <XOR2>. ========================================================================= Synthesizing Unit <ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Set property "HU_SET = XLXI_4_0" for instance <XLXI_4>. Set property "HU_SET = XLXI_5_1" for instance <XLXI_5>. Set property "HU_SET = XLXI_6_2" for instance <XLXI_6>. @@ -252,100 +244,100 @@ Synthesizing Unit <ALU>. Unit <ALU> synthesized. Synthesizing Unit <Divide_MUSER_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit <Divide_MUSER_ALU> synthesized. Synthesizing Unit <Divide_1_MUSER_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit <Divide_1_MUSER_ALU> synthesized. Synthesizing Unit <Divide_2_MUSER_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit <Divide_2_MUSER_ALU> synthesized. Synthesizing Unit <Divide_3_MUSER_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit <Divide_3_MUSER_ALU> synthesized. Synthesizing Unit <Divide_0_MUSER_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". WARNING:Xst:647 - Input <b2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary: no macro. Unit <Divide_0_MUSER_ALU> synthesized. Synthesizing Unit <Modulo_MUSER_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit <Modulo_MUSER_ALU> synthesized. Synthesizing Unit <Modulo_3_MUSER_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit <Modulo_3_MUSER_ALU> synthesized. Synthesizing Unit <Modulo_1_MUSER_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit <Modulo_1_MUSER_ALU> synthesized. Synthesizing Unit <Modulo_0_MUSER_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". WARNING:Xst:647 - Input <b3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary: no macro. Unit <Modulo_0_MUSER_ALU> synthesized. Synthesizing Unit <Negate_MUSER_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit <Negate_MUSER_ALU> synthesized. Synthesizing Unit <Negate_0_MUSER_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit <Negate_0_MUSER_ALU> synthesized. Synthesizing Unit <Negate_1_MUSER_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit <Negate_1_MUSER_ALU> synthesized. Synthesizing Unit <Negate_2_MUSER_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit <Negate_2_MUSER_ALU> synthesized. Synthesizing Unit <Negate_3_MUSER_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit <Negate_3_MUSER_ALU> synthesized. Synthesizing Unit <M4_1E_HXILINX_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Found 1-bit 4-to-1 multiplexer for signal <S1_D3_Mux_0_o> created at line 44. Summary: inferred 2 Multiplexer(s). Unit <M4_1E_HXILINX_ALU> synthesized. Synthesizing Unit <sev_seg_disp_MUSER_ALU>. - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit <sev_seg_disp_MUSER_ALU> synthesized. @@ -381,6 +373,8 @@ Macro Statistics Optimizing unit <ALU> ... +Optimizing unit <Modulo_0_MUSER_ALU> ... + Optimizing unit <sev_seg_disp_MUSER_ALU> ... Optimizing unit <M4_1E_HXILINX_ALU> ... @@ -416,29 +410,24 @@ Top Level Output File Name : ALU.ngc Primitive and Black Box Usage: ------------------------------ -# BELS : 125 -# AND2 : 22 +# BELS : 138 +# AND2 : 28 # AND3 : 21 -# AND4 : 2 +# AND4 : 3 # BUF : 4 # GND : 1 -# INV : 45 +# INV : 53 # LUT6 : 4 -# OR2 : 7 -# OR3 : 10 -# OR4 : 4 -# OR5 : 1 +# OR2 : 5 +# OR3 : 9 +# OR4 : 5 +# OR5 : 2 # VCC : 1 -# XNOR2 : 2 +# XNOR2 : 1 # XOR2 : 1 # IO Buffers : 18 # IBUF : 6 # OBUF : 12 -# Logical : 4 -# NAND2 : 1 -# NAND3 : 1 -# NAND4 : 1 -# NOR3 : 1 Device utilization summary: --------------------------- @@ -447,14 +436,14 @@ Selected Device : 6slx16csg324-3 Slice Logic Utilization: - Number of Slice LUTs: 49 out of 9112 0% - Number used as Logic: 49 out of 9112 0% + Number of Slice LUTs: 57 out of 9112 0% + Number used as Logic: 57 out of 9112 0% Slice Logic Distribution: - Number of LUT Flip Flop pairs used: 49 - Number with an unused Flip Flop: 49 out of 49 100% - Number with an unused LUT: 0 out of 49 0% - Number of fully used LUT-FF pairs: 0 out of 49 0% + Number of LUT Flip Flop pairs used: 57 + Number with an unused Flip Flop: 57 out of 57 100% + Number with an unused LUT: 0 out of 57 0% + Number of fully used LUT-FF pairs: 0 out of 57 0% Number of unique control sets: 0 IO Utilization: @@ -494,7 +483,7 @@ Speed Grade: -3 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found - Maximum combinational path delay: 16.544ns + Maximum combinational path delay: 16.900ns Timing Details: --------------- @@ -502,33 +491,33 @@ All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default path analysis - Total number of paths / destination ports: 1495 / 8 + Total number of paths / destination ports: 1539 / 8 ------------------------------------------------------------------------- -Delay: 16.544ns (Levels of Logic = 13) - Source: D (PAD) +Delay: 16.900ns (Levels of Logic = 13) + Source: C (PAD) Destination: d_out (PAD) - Data Path: D to d_out + Data Path: C to d_out Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - IBUF:I->O 24 1.222 1.172 D_IBUF (D_IBUF) - INV:I->O 1 0.568 0.944 XLXI_1/XLXI_8/XLXI_9 (XLXI_1/XLXI_8/XLXN_17) - AND2:I0->O 1 0.203 0.924 XLXI_1/XLXI_8/XLXI_3 (XLXI_1/XLXI_8/XLXN_1) - OR3:I1->O 1 0.223 0.944 XLXI_1/XLXI_8/XLXI_2 (XLXI_1/XLXI_8/XLXN_2) - AND2:I0->O 1 0.203 0.924 XLXI_1/XLXI_8/XLXI_4 (XLXI_1/XLXI_8/XLXN_4) - OR2:I1->O 1 0.223 0.580 XLXI_1/XLXI_8/XLXI_5 (XLXN_35) - begin scope: 'XLXI_6:D2' - LUT6:I5->O 9 0.205 0.829 Mmux_O11 (O) - end scope: 'XLXI_6:O' - INV:I->O 8 0.568 1.167 XLXI_9/XLXI_39 (XLXI_9/C_BAR) - AND3:I0->O 1 0.203 0.944 XLXI_9/XLXI_51 (XLXI_9/XLXN_114) - OR4:I0->O 1 0.203 0.579 XLXI_9/XLXI_52 (XLXI_9/XLXN_156) + IBUF:I->O 26 1.222 1.206 C_IBUF (C_IBUF) + INV:I->O 1 0.568 0.924 XLXI_2/XLXI_4/XLXI_9 (XLXI_2/XLXI_4/XLXN_15) + AND2:I1->O 1 0.223 0.944 XLXI_2/XLXI_4/XLXI_16 (XLXI_2/XLXI_4/XLXN_14) + OR2:I0->O 1 0.203 0.944 XLXI_2/XLXI_4/XLXI_14 (XLXI_2/XLXI_4/XLXN_1) + AND2:I0->O 1 0.203 0.944 XLXI_2/XLXI_4/XLXI_2 (XLXI_2/XLXI_4/XLXN_4) + OR2:I0->O 1 0.203 0.924 XLXI_2/XLXI_4/XLXI_4 (XLXN_37) + begin scope: 'XLXI_7:D3' + LUT6:I1->O 6 0.203 0.744 Mmux_O11 (O) + end scope: 'XLXI_7:O' + INV:I->O 9 0.568 1.194 XLXI_9/XLXI_40 (XLXI_9/D_BAR) + AND2:I0->O 2 0.203 0.845 XLXI_9/XLXI_48 (XLXI_9/XLXN_125) + OR4:I3->O 1 0.339 0.579 XLXI_9/XLXI_52 (XLXI_9/XLXN_156) INV:I->O 1 0.568 0.579 XLXI_9/XLXI_69 (d_out_OBUF) OBUF:I->O 2.571 d_out_OBUF (d_out) ---------------------------------------- - Total 16.544ns (6.960ns logic, 9.584ns route) - (42.1% logic, 57.9% route) + Total 16.900ns (7.074ns logic, 9.826ns route) + (41.9% logic, 58.1% route) ========================================================================= @@ -539,11 +528,11 @@ Cross Clock Domains Report: Total REAL time to Xst completion: 8.00 secs -Total CPU time to Xst completion: 7.97 secs +Total CPU time to Xst completion: 7.36 secs --> -Total memory usage is 253940 kilobytes +Total memory usage is 252544 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 2 ( 0 filtered) |