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-rwxr-xr-xDivide.vf72
1 files changed, 40 insertions, 32 deletions
diff --git a/Divide.vf b/Divide.vf
index c428df2..8d6a587 100755
--- a/Divide.vf
+++ b/Divide.vf
@@ -7,11 +7,11 @@
// \ \ \/ Version : 13.3
// \ \ Application : sch2hdl
// / / Filename : Divide.vf
-// /___/ /\ Timestamp : 02/15/2012 15:00:11
+// /___/ /\ Timestamp : 02/16/2012 19:28:10
// \ \ / \
// \___\/\___\
//
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Divide.vf" -w "X:/My Documents/ec311/lab1/Divide.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Divide.vf" -w "X:/My Documents/ec311/ec311-lab1/Divide.sch"
//Design Name: Divide
//Device: spartan6
//Purpose:
@@ -82,25 +82,24 @@ module Divide_2_MUSER_Divide(b0,
input b3;
output result;
- wire XLXN_1;
- wire XLXN_2;
- wire XLXN_3;
- wire XLXN_7;
+ wire XLXN_9;
+ wire XLXN_13;
+ wire XLXN_14;
+ wire XLXN_15;
- OR3 XLXI_1 (.I0(XLXN_1),
- .I1(XLXN_7),
- .I2(XLXN_3),
- .O(result));
- AND3 XLXI_2 (.I0(XLXN_2),
- .I1(b3),
- .I2(b1),
- .O(XLXN_1));
- INV XLXI_3 (.I(b2),
- .O(XLXN_2));
- INV XLXI_4 (.I(b0),
- .O(XLXN_3));
- INV XLXI_9 (.I(b1),
- .O(XLXN_7));
+ AND2 XLXI_10 (.I0(XLXN_9),
+ .I1(b3),
+ .O(result));
+ OR3 XLXI_12 (.I0(XLXN_15),
+ .I1(XLXN_14),
+ .I2(XLXN_13),
+ .O(XLXN_9));
+ INV XLXI_13 (.I(b0),
+ .O(XLXN_13));
+ INV XLXI_15 (.I(b1),
+ .O(XLXN_14));
+ INV XLXI_16 (.I(b2),
+ .O(XLXN_15));
endmodule
`timescale 1ns / 1ps
@@ -117,14 +116,23 @@ module Divide_3_MUSER_Divide(b0,
output result;
wire XLXN_2;
+ wire XLXN_13;
+ wire XLXN_14;
+ wire XLXN_15;
AND2 XLXI_2 (.I0(XLXN_2),
.I1(b3),
.O(result));
- NOR3 XLXI_3 (.I0(b0),
- .I1(b1),
- .I2(b2),
- .O(XLXN_2));
+ OR3 XLXI_4 (.I0(XLXN_15),
+ .I1(XLXN_14),
+ .I2(XLXN_13),
+ .O(XLXN_2));
+ INV XLXI_6 (.I(b2),
+ .O(XLXN_13));
+ INV XLXI_7 (.I(b1),
+ .O(XLXN_14));
+ INV XLXI_8 (.I(b0),
+ .O(XLXN_15));
endmodule
`timescale 1ns / 1ps
@@ -140,25 +148,23 @@ module Divide_0_MUSER_Divide(b0,
input b3;
output result;
- wire XLXN_1;
wire XLXN_2;
wire XLXN_3;
wire XLXN_4;
wire XLXN_5;
wire XLXN_6;
+ wire XLXN_12;
- AND3 XLXI_1 (.I0(b3),
+ AND3 XLXI_1 (.I0(b0),
.I1(b3),
.I2(XLXN_2),
.O(XLXN_5));
AND2 XLXI_2 (.I0(b1),
- .I1(XLXN_1),
+ .I1(XLXN_12),
.O(XLXN_4));
AND2 XLXI_3 (.I0(b1),
.I1(XLXN_3),
.O(XLXN_6));
- INV XLXI_4 (.I(b3),
- .O(XLXN_1));
INV XLXI_5 (.I(b1),
.O(XLXN_2));
INV XLXI_6 (.I(b0),
@@ -167,6 +173,8 @@ module Divide_0_MUSER_Divide(b0,
.I1(XLXN_5),
.I2(XLXN_4),
.O(result));
+ INV XLXI_9 (.I(b3),
+ .O(XLXN_12));
endmodule
`timescale 1ns / 1ps
@@ -204,9 +212,9 @@ module Divide(b0,
.b2(b2),
.b3(b3),
.result(out3));
- Divide_0_MUSER_Divide XLXI_12 (.b0(b1),
- .b1(b2),
+ Divide_0_MUSER_Divide XLXI_12 (.b0(b0),
+ .b1(b1),
.b2(b2),
- .b3(b0),
+ .b3(b3),
.result(out0));
endmodule