1 files changed, 50 insertions, 89 deletions
diff --git a/planAhead_run_1/planAhead.log b/planAhead_run_1/planAhead.log
index fda2b18..19f24a3 100755
--- a/planAhead_run_1/planAhead.log
+++ b/planAhead_run_1/planAhead.log
@@ -1,83 +1,48 @@
 #-----------------------------------------------------------
 # PlanAhead v13.3 (64-bit)
 # Build 147507 by hdbuild on Tue Oct  4 19:13:50 MDT 2011
-# Start of session at: Wed Feb 15 15:13:16 2012
-# Process ID: 3932
-# Log file: X:/My Documents/ec311/lab1/planAhead_run_1/planAhead.log
-# Journal file: X:/My Documents/ec311/lab1/planAhead_run_1/planAhead.jou
+# Start of session at: Thu Feb 16 18:17:07 2012
+# Process ID: 1252
+# Log file: X:/My Documents/ec311/ec311-lab1/planAhead_run_1/planAhead.log
+# Journal file: X:/My Documents/ec311/ec311-lab1/planAhead_run_1/planAhead.jou
 #-----------------------------------------------------------
 INFO: [Common-78] Attempting to get a license: PlanAhead
 INFO: [Common-82] Got a license: PlanAhead
 INFO: [Device-25] Loading parts and site information from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\arch.xmlParsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
 Finished parsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
 start_gui
-source {X:/My Documents/ec311/lab1/pa.fromHdl.tcl}
-# create_project -name lab1 -dir "X:/My Documents/ec311/lab1/planAhead_run_1" -part xc6slx16csg324-3
+source {X:/My Documents/ec311/ec311-lab1/pa.fromNetlist.tcl}
+# create_project -name lab1 -dir "X:/My Documents/ec311/ec311-lab1/planAhead_run_1" -part xc6slx16csg324-3
 Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
 Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
 Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
 Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
 Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
 Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
-# set_param project.pinAheadLayout yes
-# set srcset [get_property srcset [current_run -impl]]
-# set_property top ALU $srcset
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "X:/My Documents/ec311/ec311-lab1/ALU.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {X:/My Documents/ec311/ec311-lab1} }
+# set_param project.pinAheadLayout  yes
 # set_property target_constrs_file "ALU.ucf" [current_fileset -constrset]
-Adding file 'X:\My Documents\ec311\lab1\ALU.ucf' to fileset 'constrs_1'
-CRITICAL WARNING: [Designutils-735] The top module "ALU" specified for this project can not be validated. The current project is using automatic hierarchy update mode, and hence a new suitable replacement top will be automatically selected. If this is not desired, please change the hierarchy update mode to one of the manual compile order modes first, and then set top to any desired value.
-# set hdlfile [add_files [list {Negate_3.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate_2.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate_1.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate_0.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo_3.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo_1.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo_0.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_3.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_2.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_1.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_0.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {sev_seg_disp.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {ALU.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
+Adding file 'X:\My Documents\ec311\ec311-lab1\ALU.ucf' to fileset 'constrs_1'
 # add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]]
-# open_rtl_design -part xc6slx16csg324-3
-INFO: [PlanAhead-58] Using Verific elaboration
-Parsing VHDL file "C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify
-Analyzing Verilog file "X:\My Documents\ec311\lab1\Negate.vf" into library work
+# open_netlist_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to part: xc6slx16csg324-3
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91624 kilobytes
+
+Parsing EDIF File [.\planAhead_run_1\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_1\lab1.data\cache\ALU_ngc_c04f956c.edif]
 Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
 Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
 Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
@@ -85,30 +50,26 @@ Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spart
 Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
 Loading device configuration modes from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/ConfigModes.xml
 Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
-Parsing UCF File [X:\My Documents\ec311\lab1\ALU.ucf]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'A' [X:\My Documents\ec311\lab1\ALU.ucf:4]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'AN0' [X:\My Documents\ec311\lab1\ALU.ucf:5]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'AN1' [X:\My Documents\ec311\lab1\ALU.ucf:6]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'AN2' [X:\My Documents\ec311\lab1\ALU.ucf:7]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'AN3' [X:\My Documents\ec311\lab1\ALU.ucf:8]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'B' [X:\My Documents\ec311\lab1\ALU.ucf:9]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'C' [X:\My Documents\ec311\lab1\ALU.ucf:10]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'D' [X:\My Documents\ec311\lab1\ALU.ucf:11]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'S0' [X:\My Documents\ec311\lab1\ALU.ucf:12]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'S1' [X:\My Documents\ec311\lab1\ALU.ucf:13]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'a_out' [X:\My Documents\ec311\lab1\ALU.ucf:14]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'b_out' [X:\My Documents\ec311\lab1\ALU.ucf:15]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'c_out' [X:\My Documents\ec311\lab1\ALU.ucf:16]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'd_out' [X:\My Documents\ec311\lab1\ALU.ucf:17]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'e_out' [X:\My Documents\ec311\lab1\ALU.ucf:18]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'f_out' [X:\My Documents\ec311\lab1\ALU.ucf:19]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'g_out' [X:\My Documents\ec311\lab1\ALU.ucf:20]
-CRITICAL WARNING: [Constraints-11] Could not find net or pin 'sign' [X:\My Documents\ec311\lab1\ALU.ucf:21]
-Finished Parsing UCF File [X:\My Documents\ec311\lab1\ALU.ucf]
-INFO: [Designutils-20] Invalid constraints found, use command 'write_ucf -constraints invalid <file>' to save all the invalid constraints to a file
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
 INFO: [PlanAhead-566] Unisim Transformation Summary:
-No Unisim elements were transformed.open_rtl_design: Time (s): 13.288w.  Memory (MB): 788.289p 223.703g
-exit
-stop_gui
-INFO: [PlanAhead-261] Exiting PlanAhead...
-INFO: [Common-83] Releasing license: PlanAhead
+No Unisim elements were transformed.open_netlist_design: Time (s): 13.291w.  Memory (MB): 734.672p 186.648g
+startgroup
+startgroup
+set_property loc PAD2 [get_ports A]
+set_property loc PAD2 [get_ports A]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD30 [get_ports D]
+set_property loc PAD30 [get_ports D]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD29 [get_ports C]
+set_property loc PAD29 [get_ports C]
+endgroup
+endgroup
+save_design