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| author | Michael Abed <michaelabed@gmail.com> | 2012-02-17 12:10:31 -0500 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-02-17 12:10:31 -0500 |
| commit | 59d89428d6160fb672c2b6a41339505cc69344d0 (patch) | |
| tree | a774e809a31fc7eae7b0fd0777714c86ffedc9d6 /_xmsgs/trce.xmsgs | |
| parent | 0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a (diff) | |
| download | ec311-lab2-master.tar.gz ec311-lab2-master.tar.bz2 ec311-lab2-master.zip | |
Diffstat (limited to '_xmsgs/trce.xmsgs')
| -rwxr-xr-x | _xmsgs/trce.xmsgs | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/_xmsgs/trce.xmsgs b/_xmsgs/trce.xmsgs new file mode 100755 index 0000000..80cb2e4 --- /dev/null +++ b/_xmsgs/trce.xmsgs @@ -0,0 +1,15 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +<msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg>
+ +<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
+ +<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
+ +</messages> +
|