diff options
| author | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:55 -0500 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:55 -0500 |
| commit | 0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a (patch) | |
| tree | 0546ba14ba410a565b6bff722a23b26860744825 /pa.fromHdl.tcl | |
| download | ec311-lab2-0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a.tar.gz ec311-lab2-0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a.tar.bz2 ec311-lab2-0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a.zip | |
initial commit
Diffstat (limited to 'pa.fromHdl.tcl')
| -rwxr-xr-x | pa.fromHdl.tcl | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/pa.fromHdl.tcl b/pa.fromHdl.tcl new file mode 100755 index 0000000..2112f38 --- /dev/null +++ b/pa.fromHdl.tcl @@ -0,0 +1,19 @@ + +# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator + +create_project -name lab2 -dir "/home/michael/Documents/School/EC311/lab2/planAhead_run_2" -part xc6slx16csg324-3 +set_param project.pinAheadLayout yes +set srcset [get_property srcset [current_run -impl]] +set_property target_constrs_file "ALUSHOW.ucf" [current_fileset -constrset] +set hdlfile [add_files [list {sev_seg_disp.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {ALU.v}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {ALUSHOW.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set_property top ALUSHOW $srcset +add_files [list {ALUSHOW.ucf}] -fileset [get_property constrset [current_run]] +open_rtl_design -part xc6slx16csg324-3 |