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| author | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:55 -0500 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:55 -0500 |
| commit | 0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a (patch) | |
| tree | 0546ba14ba410a565b6bff722a23b26860744825 | |
| download | ec311-lab2-0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a.tar.gz ec311-lab2-0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a.tar.bz2 ec311-lab2-0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a.zip | |
initial commit
39 files changed, 4018 insertions, 0 deletions
diff --git a/ALU.cmd_log b/ALU.cmd_log new file mode 100755 index 0000000..044741b --- /dev/null +++ b/ALU.cmd_log @@ -0,0 +1,10 @@ +vhdtdtfi -lib work {X:/My Documents/ec311/lab2/ALU.v} -lang verilog -prj lab2 -o ALU.spl -module ALU -template C:/Xilinx/13.3/ISE_DS/ISE//data/splveri.tft -deleteonerror
+spl2sym -intstyle ise -family spartan6 ALU.spl {X:/My Documents/ec311/lab2/ALU.sym}
+vhdtdtfi -lib work {X:/My Documents/ec311/lab2/ALU.v} -lang verilog -prj lab2 -o ALU.spl -module ALU -template C:/Xilinx/13.3/ISE_DS/ISE//data/splveri.tft -deleteonerror
+spl2sym -intstyle ise -family spartan6 ALU.spl {X:/My Documents/ec311/lab2/ALU.sym}
+vhdtdtfi -lib work /home/michael/Documents/School/EC311/lab2/ALU.v -lang verilog -prj lab2 -o ALU.spl -module ALU -template /home/michael/opt/Xilinx/13.4/ISE_DS/ISE//data/splveri.tft -deleteonerror +spl2sym -intstyle ise -family spartan6 ALU.spl /home/michael/Documents/School/EC311/lab2/ALU.sym +vhdtdtfi -lib work /home/michael/Documents/School/EC311/lab2/ALU.v -lang verilog -prj lab2 -o ALU.spl -module ALU -template /home/michael/opt/Xilinx/13.4/ISE_DS/ISE//data/splveri.tft -deleteonerror +spl2sym -intstyle ise -family spartan6 -w ALU.spl /home/michael/Documents/School/EC311/lab2/ALU.sym +vhdtdtfi -lib work /home/michael/Documents/School/EC311/lab2/ALU.v -lang verilog -prj lab2 -o ALU.spl -module ALU -template /home/michael/opt/Xilinx/13.4/ISE_DS/ISE//data/splveri.tft -deleteonerror +spl2sym -intstyle ise -family spartan6 -w ALU.spl /home/michael/Documents/School/EC311/lab2/ALU.sym @@ -0,0 +1,9 @@ +[Inputs] +=s[1:0]= +=a[3:0]= +[Outputs] +=o[3:0]= +[BiDir] +[ATTRIBUTES] +VeriModel ALU + @@ -0,0 +1,22 @@ +<?xml version="1.0" encoding="UTF-8"?> +<symbol version="7" name="ALU"> + <symboltype>BLOCK</symboltype> + <timestamp>2012-2-16T2:38:45</timestamp> + <attr value="ALU" name="VeriModel" /> + <pin polarity="Input" x="0" y="416" name="s(1:0)" /> + <pin polarity="Input" x="0" y="480" name="a(3:0)" /> + <pin polarity="Output" x="384" y="416" name="o(3:0)" /> + <graph> + <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-136" type="symbol" /> + <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="416" type="pin s(1:0)" /> + <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="480" type="pin a(3:0)" /> + <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="416" type="pin o(3:0)" /> + <rect width="64" x="0" y="404" height="24" /> + <line x2="0" y1="416" y2="416" x1="64" /> + <rect width="64" x="0" y="468" height="24" /> + <line x2="0" y1="480" y2="480" x1="64" /> + <rect width="64" x="320" y="404" height="24" /> + <line x2="384" y1="416" y2="416" x1="320" /> + <rect width="256" x="64" y="-128" height="640" /> + </graph> +</symbol> @@ -0,0 +1,38 @@ +`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 15:30:47 02/15/2012
+// Design Name:
+// Module Name: ALU
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+module ALU(
+ input [1:0] s, + input [3:0] a,
+ output [3:0] o
+ );
+ +reg [3:0] o;
+
+always @ ( * )
+begin
+ case ( s )
+ 2'd0 : o = a;
+ 2'd1 : o = ~a+1;
+ 2'd2 : o = a >> 1;
+ 2'd3 : o = a % 3;
+ endcase
+end
+endmodule
diff --git a/ALUSHOW.cmd_log b/ALUSHOW.cmd_log new file mode 100755 index 0000000..bf0d338 --- /dev/null +++ b/ALUSHOW.cmd_log @@ -0,0 +1 @@ +xst -intstyle ise -ifn "X:/My Documents/ec311/lab2/ALUSHOW.xst" -ofn "X:/My Documents/ec311/lab2/ALUSHOW.syr"
diff --git a/ALUSHOW.jhd b/ALUSHOW.jhd new file mode 100755 index 0000000..5a366ed --- /dev/null +++ b/ALUSHOW.jhd @@ -0,0 +1,5 @@ +MODULE ALUSHOW + SUBMODULE sev_seg_disp + INSTANCE XLXI_2 + SUBMODULE ALU + INSTANCE XLXI_4 diff --git a/ALUSHOW.lso b/ALUSHOW.lso new file mode 100755 index 0000000..22de730 --- /dev/null +++ b/ALUSHOW.lso @@ -0,0 +1 @@ +work
diff --git a/ALUSHOW.prj b/ALUSHOW.prj new file mode 100755 index 0000000..714802f --- /dev/null +++ b/ALUSHOW.prj @@ -0,0 +1,3 @@ +verilog work "sev_seg_disp.vf"
+verilog work "ALU.v"
+verilog work "ALUSHOW.vf"
diff --git a/ALUSHOW.sch b/ALUSHOW.sch new file mode 100755 index 0000000..ba21753 --- /dev/null +++ b/ALUSHOW.sch @@ -0,0 +1,189 @@ +<?xml version="1.0" encoding="UTF-8"?> +<drawing version="7"> + <attr value="spartan6" name="DeviceFamilyName"> + <trait delete="all:0" /> + <trait editname="all:0" /> + <trait edittrait="all:0" /> + </attr> + <netlist> + <signal name="ao" /> + <signal name="bo" /> + <signal name="co" /> + <signal name="do" /> + <signal name="eo" /> + <signal name="fo" /> + <signal name="go" /> + <signal name="sign" /> + <signal name="AN0" /> + <signal name="AN1" /> + <signal name="AN2" /> + <signal name="AN3" /> + <signal name="ALU_OUT(3:0)" /> + <signal name="ALU_OUT(0)" /> + <signal name="ALU_OUT(1)" /> + <signal name="ALU_OUT(2)" /> + <signal name="ALU_OUT(3)" /> + <signal name="A(3:0)" /> + <signal name="S(1:0)" /> + <port polarity="Output" name="ao" /> + <port polarity="Output" name="bo" /> + <port polarity="Output" name="co" /> + <port polarity="Output" name="do" /> + <port polarity="Output" name="eo" /> + <port polarity="Output" name="fo" /> + <port polarity="Output" name="go" /> + <port polarity="Output" name="sign" /> + <port polarity="Output" name="AN0" /> + <port polarity="Output" name="AN1" /> + <port polarity="Output" name="AN2" /> + <port polarity="Output" name="AN3" /> + <port polarity="Input" name="A(3:0)" /> + <port polarity="Input" name="S(1:0)" /> + <blockdef name="sev_seg_disp"> + <timestamp>2012-2-15T18:55:28</timestamp> + <rect width="256" x="64" y="-768" height="768" /> + <line x2="0" y1="-736" y2="-736" x1="64" /> + <line x2="0" y1="-512" y2="-512" x1="64" /> + <line x2="0" y1="-288" y2="-288" x1="64" /> + <line x2="0" y1="-64" y2="-64" x1="64" /> + <line x2="384" y1="-736" y2="-736" x1="320" /> + <line x2="384" y1="-672" y2="-672" x1="320" /> + <line x2="384" y1="-608" y2="-608" x1="320" /> + <line x2="384" y1="-544" y2="-544" x1="320" /> + <line x2="384" y1="-480" y2="-480" x1="320" /> + <line x2="384" y1="-416" y2="-416" x1="320" /> + <line x2="384" y1="-352" y2="-352" x1="320" /> + <line x2="384" y1="-288" y2="-288" x1="320" /> + <line x2="384" y1="-224" y2="-224" x1="320" /> + <line x2="384" y1="-160" y2="-160" x1="320" /> + <line x2="384" y1="-96" y2="-96" x1="320" /> + <line x2="384" y1="-32" y2="-32" x1="320" /> + </blockdef> + <blockdef name="ALU"> + <timestamp>2012-2-16T2:38:45</timestamp> + <rect width="64" x="0" y="404" height="24" /> + <line x2="0" y1="416" y2="416" x1="64" /> + <rect width="64" x="0" y="468" height="24" /> + <line x2="0" y1="480" y2="480" x1="64" /> + <rect width="64" x="320" y="404" height="24" /> + <line x2="384" y1="416" y2="416" x1="320" /> + <rect width="256" x="64" y="-128" height="640" /> + </blockdef> + <block symbolname="sev_seg_disp" name="XLXI_2"> + <blockpin signalname="ALU_OUT(0)" name="A" /> + <blockpin signalname="ALU_OUT(1)" name="B" /> + <blockpin signalname="ALU_OUT(2)" name="C" /> + <blockpin signalname="ALU_OUT(3)" name="D" /> + <blockpin signalname="ao" name="a_out" /> + <blockpin signalname="bo" name="b_out" /> + <blockpin signalname="co" name="c_out" /> + <blockpin signalname="do" name="d_out" /> + <blockpin signalname="eo" name="e_out" /> + <blockpin signalname="fo" name="f_out" /> + <blockpin signalname="go" name="g_out" /> + <blockpin signalname="sign" name="sign" /> + <blockpin signalname="AN0" name="AN0" /> + <blockpin signalname="AN1" name="AN1" /> + <blockpin signalname="AN2" name="AN2" /> + <blockpin signalname="AN3" name="AN3" /> + </block> + <block symbolname="ALU" name="XLXI_4"> + <blockpin signalname="S(1:0)" name="s(1:0)" /> + <blockpin signalname="A(3:0)" name="a(3:0)" /> + <blockpin signalname="ALU_OUT(3:0)" name="o(3:0)" /> + </block> + </netlist> + <sheet sheetnum="1" width="3520" height="2720"> + <instance x="1728" y="1536" name="XLXI_2" orien="R0"> + </instance> + <branch name="ao"> + <wire x2="2144" y1="800" y2="800" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="800" name="ao" orien="R0" /> + <branch name="bo"> + <wire x2="2144" y1="864" y2="864" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="864" name="bo" orien="R0" /> + <branch name="co"> + <wire x2="2144" y1="928" y2="928" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="928" name="co" orien="R0" /> + <branch name="do"> + <wire x2="2144" y1="992" y2="992" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="992" name="do" orien="R0" /> + <branch name="eo"> + <wire x2="2144" y1="1056" y2="1056" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1056" name="eo" orien="R0" /> + <branch name="fo"> + <wire x2="2144" y1="1120" y2="1120" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1120" name="fo" orien="R0" /> + <branch name="go"> + <wire x2="2144" y1="1184" y2="1184" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1184" name="go" orien="R0" /> + <branch name="sign"> + <wire x2="2144" y1="1248" y2="1248" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1248" name="sign" orien="R0" /> + <branch name="AN0"> + <wire x2="2144" y1="1312" y2="1312" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1312" name="AN0" orien="R0" /> + <branch name="AN1"> + <wire x2="2144" y1="1376" y2="1376" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1376" name="AN1" orien="R0" /> + <branch name="AN2"> + <wire x2="2144" y1="1440" y2="1440" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1440" name="AN2" orien="R0" /> + <branch name="AN3"> + <wire x2="2144" y1="1504" y2="1504" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1504" name="AN3" orien="R0" /> + <instance x="880" y="1152" name="XLXI_4" orien="R0"> + </instance> + <branch name="ALU_OUT(3:0)"> + <wire x2="1376" y1="1568" y2="1568" x1="1264" /> + <wire x2="1376" y1="800" y2="1024" x1="1376" /> + <wire x2="1376" y1="1024" y2="1248" x1="1376" /> + <wire x2="1376" y1="1248" y2="1472" x1="1376" /> + <wire x2="1376" y1="1472" y2="1568" x1="1376" /> + </branch> + <bustap x2="1472" y1="800" y2="800" x1="1376" /> + <branch name="ALU_OUT(0)"> + <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1664" y="800" type="branch" /> + <wire x2="1664" y1="800" y2="800" x1="1472" /> + <wire x2="1728" y1="800" y2="800" x1="1664" /> + </branch> + <bustap x2="1472" y1="1024" y2="1024" x1="1376" /> + <branch name="ALU_OUT(1)"> + <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1632" y="1024" type="branch" /> + <wire x2="1632" y1="1024" y2="1024" x1="1472" /> + <wire x2="1728" y1="1024" y2="1024" x1="1632" /> + </branch> + <bustap x2="1472" y1="1248" y2="1248" x1="1376" /> + <branch name="ALU_OUT(2)"> + <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1568" y="1248" type="branch" /> + <wire x2="1568" y1="1248" y2="1248" x1="1472" /> + <wire x2="1728" y1="1248" y2="1248" x1="1568" /> + </branch> + <bustap x2="1472" y1="1472" y2="1472" x1="1376" /> + <branch name="ALU_OUT(3)"> + <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1568" y="1472" type="branch" /> + <wire x2="1568" y1="1472" y2="1472" x1="1472" /> + <wire x2="1728" y1="1472" y2="1472" x1="1568" /> + </branch> + <branch name="A(3:0)"> + <wire x2="880" y1="1632" y2="1632" x1="848" /> + </branch> + <iomarker fontsize="28" x="848" y="1632" name="A(3:0)" orien="R180" /> + <branch name="S(1:0)"> + <wire x2="880" y1="1568" y2="1568" x1="848" /> + </branch> + <iomarker fontsize="28" x="848" y="1568" name="S(1:0)" orien="R180" /> + </sheet> +</drawing>
\ No newline at end of file diff --git a/ALUSHOW.syr b/ALUSHOW.syr new file mode 100755 index 0000000..f10b0f6 --- /dev/null +++ b/ALUSHOW.syr @@ -0,0 +1,122 @@ +Release 13.3 - xst O.76xd (nt64) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to xst/projnav.tmp + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.11 secs + +--> Parameter xsthdpdir set to xst + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.12 secs + +--> Reading design: ALUSHOW.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Parsing + 3) HDL Elaboration + 4) HDL Synthesis + 4.1) HDL Synthesis Report + 5) Advanced HDL Synthesis + 5.1) Advanced HDL Synthesis Report + 6) Low Level Synthesis + 7) Partition Report + 8) Design Summary + 8.1) Primitive and Black Box Usage + 8.2) Device utilization summary + 8.3) Partition Resource Summary + 8.4) Timing Report + 8.4.1) Clock Information + 8.4.2) Asynchronous Control Signals Information + 8.4.3) Timing Summary + 8.4.4) Timing Details + 8.4.5) Cross Clock Domains Report + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "ALUSHOW.prj" +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "ALUSHOW" +Output Format : NGC +Target Device : xc6slx16-3-csg324 + +---- Source Options +Top Module Name : ALUSHOW +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : LUT +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Shift Register Extraction : YES +ROM Style : Auto +Resource Sharing : YES +Asynchronous To Synchronous : NO +Shift Register Minimum Size : 2 +Use DSP Block : Auto +Automatic Register Balancing : No + +---- Target Options +LUT Combining : Auto +Reduce Control Sets : Auto +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : Auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Power Reduction : NO +Keep Hierarchy : No +Netlist Hierarchy : As_Optimized +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : YES +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : Maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + + +========================================================================= +* HDL Parsing * +========================================================================= +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\sev_seg_disp.vf" into library work +Parsing module <sev_seg_disp>. +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" into library work +Parsing module <ALU>. +ERROR:HDLCompiler:44 - "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 26: out3 is not a constant +ERROR:HDLCompiler:598 - "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 21: Module <ALU> ignored due to previous errors. +Verilog file \\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v ignored due to errors +--> + +Total memory usage is 201016 kilobytes + +Number of errors : 2 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) + diff --git a/ALUSHOW.ucf b/ALUSHOW.ucf new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/ALUSHOW.ucf diff --git a/ALUSHOW.vf b/ALUSHOW.vf new file mode 100644 index 0000000..8662af8 --- /dev/null +++ b/ALUSHOW.vf @@ -0,0 +1,286 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 13.4 +// \ \ Application : sch2hdl +// / / Filename : ALUSHOW.vf +// /___/ /\ Timestamp : 02/15/2012 21:35:26 +// \ \ / \ +// \___\/\___\ +// +//Command: sch2hdl -intstyle ise -family spartan6 -verilog /home/michael/Documents/School/EC311/lab2/ALUSHOW.vf -w /home/michael/Documents/School/EC311/lab2/ALUSHOW.sch +//Design Name: ALUSHOW +//Device: spartan6 +//Purpose: +// This verilog netlist is translated from an ECS schematic.It can be +// synthesized and simulated, but it should not be modified. +// +`timescale 1ns / 1ps + +module sev_seg_disp_MUSER_ALUSHOW(A, + B, + C, + D, + AN0, + AN1, + AN2, + AN3, + a_out, + b_out, + c_out, + d_out, + e_out, + f_out, + g_out, + sign); + + input A; + input B; + input C; + input D; + output AN0; + output AN1; + output AN2; + output AN3; + output a_out; + output b_out; + output c_out; + output d_out; + output e_out; + output f_out; + output g_out; + output sign; + + wire A_BAR; + wire B_BAR; + wire C_BAR; + wire D_BAR; + wire XLXN_14; + wire XLXN_24; + wire XLXN_61; + wire XLXN_62; + wire XLXN_63; + wire XLXN_64; + wire XLXN_65; + wire XLXN_91; + wire XLXN_92; + wire XLXN_93; + wire XLXN_94; + wire XLXN_105; + wire XLXN_113; + wire XLXN_114; + wire XLXN_125; + wire XLXN_126; + wire XLXN_128; + wire XLXN_129; + wire XLXN_130; + wire XLXN_131; + wire XLXN_145; + wire XLXN_146; + wire XLXN_147; + wire XLXN_148; + wire XLXN_149; + wire XLXN_151; + wire XLXN_155; + wire XLXN_156; + wire XLXN_158; + wire XLXN_160; + wire XLXN_162; + wire XLXN_165; + + BUF XLXI_5 (.I(XLXN_14), + .O(AN0)); + BUF XLXI_6 (.I(XLXN_14), + .O(AN1)); + BUF XLXI_7 (.I(XLXN_14), + .O(AN2)); + BUF XLXI_8 (.I(XLXN_24), + .O(AN3)); + GND XLXI_11 (.G(XLXN_24)); + VCC XLXI_12 (.P(XLXN_14)); + AND3 XLXI_30 (.I0(B), + .I1(C_BAR), + .I2(D), + .O(XLXN_61)); + AND3 XLXI_31 (.I0(A_BAR), + .I1(D), + .I2(C), + .O(XLXN_62)); + AND2 XLXI_32 (.I0(B_BAR), + .I1(D_BAR), + .O(XLXN_63)); + AND2 XLXI_33 (.I0(C), + .I1(D_BAR), + .O(XLXN_64)); + OR5 XLXI_34 (.I0(XLXN_65), + .I1(XLXN_64), + .I2(XLXN_63), + .I3(XLXN_62), + .I4(XLXN_61), + .O(XLXN_149)); + AND2 XLXI_35 (.I0(B_BAR), + .I1(A), + .O(XLXN_65)); + INV XLXI_37 (.I(A), + .O(A_BAR)); + INV XLXI_38 (.I(B), + .O(B_BAR)); + INV XLXI_39 (.I(C), + .O(C_BAR)); + INV XLXI_40 (.I(D), + .O(D_BAR)); + OR4 XLXI_41 (.I0(XLXN_94), + .I1(XLXN_93), + .I2(XLXN_92), + .I3(XLXN_91), + .O(XLXN_151)); + XNOR2 XLXI_42 (.I0(B), + .I1(A), + .O(XLXN_91)); + AND2 XLXI_43 (.I0(D_BAR), + .I1(C_BAR), + .O(XLXN_92)); + AND2 XLXI_44 (.I0(B_BAR), + .I1(C_BAR), + .O(XLXN_93)); + AND3 XLXI_45 (.I0(A_BAR), + .I1(D), + .I2(C), + .O(XLXN_94)); + XOR2 XLXI_46 (.I0(B), + .I1(A), + .O(XLXN_105)); + OR3 XLXI_47 (.I0(D), + .I1(C_BAR), + .I2(XLXN_105), + .O(XLXN_155)); + AND2 XLXI_48 (.I0(D_BAR), + .I1(C), + .O(XLXN_125)); + AND2 XLXI_49 (.I0(D_BAR), + .I1(B_BAR), + .O(XLXN_126)); + AND2 XLXI_50 (.I0(C), + .I1(B_BAR), + .O(XLXN_113)); + AND3 XLXI_51 (.I0(C_BAR), + .I1(D), + .I2(B), + .O(XLXN_114)); + OR4 XLXI_52 (.I0(XLXN_114), + .I1(XLXN_113), + .I2(XLXN_126), + .I3(XLXN_125), + .O(XLXN_156)); + OR2 XLXI_53 (.I0(XLXN_126), + .I1(XLXN_125), + .O(XLXN_158)); + AND3 XLXI_54 (.I0(C_BAR), + .I1(B), + .I2(A_BAR), + .O(XLXN_128)); + AND3 XLXI_55 (.I0(C), + .I1(B_BAR), + .I2(A), + .O(XLXN_129)); + AND3 XLXI_56 (.I0(D_BAR), + .I1(B), + .I2(A_BAR), + .O(XLXN_130)); + AND2 XLXI_57 (.I0(D_BAR), + .I1(C_BAR), + .O(XLXN_131)); + OR4 XLXI_58 (.I0(XLXN_131), + .I1(XLXN_130), + .I2(XLXN_129), + .I3(XLXN_128), + .O(XLXN_160)); + OR4 XLXI_60 (.I0(XLXN_148), + .I1(XLXN_147), + .I2(XLXN_146), + .I3(XLXN_145), + .O(XLXN_162)); + AND2 XLXI_61 (.I0(C_BAR), + .I1(B), + .O(XLXN_145)); + AND2 XLXI_62 (.I0(D_BAR), + .I1(C), + .O(XLXN_146)); + AND2 XLXI_63 (.I0(B_BAR), + .I1(C), + .O(XLXN_147)); + AND2 XLXI_64 (.I0(D_BAR), + .I1(A), + .O(XLXN_148)); + INV XLXI_65 (.I(XLXN_149), + .O(a_out)); + INV XLXI_66 (.I(XLXN_151), + .O(b_out)); + INV XLXI_67 (.I(XLXN_155), + .O(c_out)); + INV XLXI_68 (.I(XLXN_158), + .O(e_out)); + INV XLXI_69 (.I(XLXN_156), + .O(d_out)); + INV XLXI_70 (.I(XLXN_160), + .O(f_out)); + INV XLXI_71 (.I(XLXN_162), + .O(g_out)); + INV XLXI_72 (.I(A_BAR), + .O(XLXN_165)); + INV XLXI_73 (.I(XLXN_165), + .O(sign)); +endmodule +`timescale 1ns / 1ps + +module ALUSHOW(AN0, + AN1, + AN2, + AN3, + ao, + bo, + co, + do, + eo, + fo, + go, + sign); + + output AN0; + output AN1; + output AN2; + output AN3; + output ao; + output bo; + output co; + output do; + output eo; + output fo; + output go; + output sign; + + wire [3:0] ALU_OUT; + + sev_seg_disp_MUSER_ALUSHOW XLXI_2 (.A(ALU_OUT[0]), + .B(ALU_OUT[1]), + .C(ALU_OUT[2]), + .D(ALU_OUT[3]), + .AN0(AN0), + .AN1(AN1), + .AN2(AN2), + .AN3(AN3), + .a_out(ao), + .b_out(bo), + .c_out(co), + .d_out(do), + .e_out(eo), + .f_out(fo), + .g_out(go), + .sign(sign)); + ALU XLXI_4 (.a(), + .s(), + .o(ALU_OUT[3:0])); +endmodule diff --git a/ALUSHOW.xst b/ALUSHOW.xst new file mode 100755 index 0000000..bc4d1a5 --- /dev/null +++ b/ALUSHOW.xst @@ -0,0 +1,52 @@ +set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn ALUSHOW.prj
+-ofn ALUSHOW
+-ofmt NGC
+-p xc6slx16-3-csg324
+-top ALUSHOW
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/ALUSHOW_envsettings.html b/ALUSHOW_envsettings.html new file mode 100644 index 0000000..2c8f42b --- /dev/null +++ b/ALUSHOW_envsettings.html @@ -0,0 +1,395 @@ +<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD> +<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> +<center><big><big><b>System Settings</b></big></big></center><br> +<A NAME="Environment Settings"></A> + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'> +<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD> +</tr> +<tr bgcolor='#ffff99'> +<td><b>Environment Variable</b></td> +<td><b>xst</b></td> +<td><b>ngdbuild</b></td> +<td><b>map</b></td> +<td><b>par</b></td> +</tr> +<tr> +<td>PATH</td> +<td>C:<br>\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C:<br>\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\PlanAhead\bin;C:<br>\Xilinx\13.3\ISE_DS\ISE\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\ISE\lib\nt64;C:<br>\Xilinx\13.3\ISE_DS\EDK\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\EDK\lib\nt64;C:<br>\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C:<br>\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C:<br>\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C:<br>\Xilinx\13.3\ISE_DS\common\bin\nt64;C:<br>\Xilinx\13.3\ISE_DS\common\lib\nt64;C:<br>\Windows\system32;C:<br>\Windows;C:<br>\Windows\System32\Wbem;C:<br>\Windows\System32\WindowsPowerShell\v1.0\;C:<br>\Program Files\MATLAB\R2011a\runtime\win64;C:<br>\Program Files\MATLAB\R2011a\bin;C:<br>\VXIPNP\WinNT\Bin;C:<br>\Program Files (x86)\Altium Designer Summer 09\System;C:<br>\Program Files (x86)\QuickTime\QTSystem\;C:<br>\Program Files\NetBeans 7.0.1\java\ant\bin;C:<br>\Program Files\Java\jdk1.6.0_27\bin;C:<br>\Program Files\TortoiseSVN\bin;C:<br>\Program Files (x86)\Rational\Rose RealTime\bin\win32;C:<br>\Program Files (x86)\Rational\common;C:<br>\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:<br>\Cadence\SPB_16.5\tools\Capture;C:<br>\Cadence\SPB_16.5\tools\PSpice\Library;C:<br>\Cadence\SPB_16.5\tools\PSpice;C:<br>\Cadence\SPB_16.5\tools\specctra\bin;C:<br>\Cadence\SPB_16.5\tools\fet\bin;C:<br>\Cadence\SPB_16.5\tools\libutil\bin;C:<br>\Cadence\SPB_16.5\tools\bin;C:<br>\Cadence\SPB_16.5\tools\pcb\bin</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>PATHEXT</td> +<td>.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>XILINX</td> +<td>C:<br>\Xilinx\13.3\ISE_DS\ISE\</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>XILINXD_LICENSE_FILE</td> +<td>2100@XilinxLM.bu.edu</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>XILINX_DSP</td> +<td>C:<br>\Xilinx\13.3\ISE_DS\ISE</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>XILINX_EDK</td> +<td>C:<br>\Xilinx\13.3\ISE_DS\EDK</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>XILINX_PLANAHEAD</td> +<td>C:<br>\Xilinx\13.3\ISE_DS\PlanAhead</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +</TABLE> +<A NAME="Synthesis Property Settings"></A> + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'> +<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD> +</tr> +<tr bgcolor='#ffff99'> +<td><b>Switch Name</b></td> +<td><b>Property Name</b></td> +<td><b>Value</b></td> +<td><b>Default Value</b></td> +</tr> +<tr> +<td>-ifn</td> +<td> </td> +<td>ALUSHOW.prj</td> +<td> </td> +</tr> +<tr> +<td>-ofn</td> +<td> </td> +<td>ALUSHOW</td> +<td> </td> +</tr> +<tr> +<td>-ofmt</td> +<td> </td> +<td>NGC</td> +<td>NGC</td> +</tr> +<tr> +<td>-p</td> +<td> </td> +<td>xc6slx16-3-csg324</td> +<td> </td> +</tr> +<tr> +<td>-top</td> +<td> </td> +<td>ALUSHOW</td> +<td> </td> +</tr> +<tr> +<td>-opt_mode</td> +<td>Optimization Goal</td> +<td>Speed</td> +<td>Speed</td> +</tr> +<tr> +<td>-opt_level</td> +<td>Optimization Effort</td> +<td>1</td> +<td>1</td> +</tr> +<tr> +<td>-power</td> +<td>Power Reduction</td> +<td>NO</td> +<td>No</td> +</tr> +<tr> +<td>-iuc</td> +<td>Use synthesis Constraints File</td> +<td>NO</td> +<td>No</td> +</tr> +<tr> +<td>-keep_hierarchy</td> +<td>Keep Hierarchy</td> +<td>No</td> +<td>No</td> +</tr> +<tr> +<td>-netlist_hierarchy</td> +<td>Netlist Hierarchy</td> +<td>As_Optimized</td> +<td>As_Optimized</td> +</tr> +<tr> +<td>-rtlview</td> +<td>Generate RTL Schematic</td> +<td>Yes</td> +<td>No</td> +</tr> +<tr> +<td>-glob_opt</td> +<td>Global Optimization Goal</td> +<td>AllClockNets</td> +<td>AllClockNets</td> +</tr> +<tr> +<td>-read_cores</td> +<td>Read Cores</td> +<td>YES</td> +<td>Yes</td> +</tr> +<tr> +<td>-write_timing_constraints</td> +<td>Write Timing Constraints</td> +<td>NO</td> +<td>No</td> +</tr> +<tr> +<td>-cross_clock_analysis</td> +<td>Cross Clock Analysis</td> +<td>NO</td> +<td>No</td> +</tr> +<tr> +<td>-bus_delimiter</td> +<td>Bus Delimiter</td> +<td><></td> +<td><></td> +</tr> +<tr> +<td>-slice_utilization_ratio</td> +<td>Slice Utilization Ratio</td> +<td>100</td> +<td>100</td> +</tr> +<tr> +<td>-bram_utilization_ratio</td> +<td>BRAM Utilization Ratio</td> +<td>100</td> +<td>100</td> +</tr> +<tr> +<td>-dsp_utilization_ratio</td> +<td>DSP Utilization Ratio</td> +<td>100</td> +<td>100</td> +</tr> +<tr> +<td>-reduce_control_sets</td> +<td> </td> +<td>Auto</td> +<td>Auto</td> +</tr> +<tr> +<td>-fsm_extract</td> +<td> </td> +<td>YES</td> +<td>Yes</td> +</tr> +<tr> +<td>-fsm_encoding</td> +<td> </td> +<td>Auto</td> +<td>Auto</td> +</tr> +<tr> +<td>-safe_implementation</td> +<td> </td> +<td>No</td> +<td>No</td> +</tr> +<tr> +<td>-fsm_style</td> +<td> </td> +<td>LUT</td> +<td>LUT</td> +</tr> +<tr> +<td>-ram_extract</td> +<td> </td> +<td>Yes</td> +<td>Yes</td> +</tr> +<tr> +<td>-ram_style</td> +<td> </td> +<td>Auto</td> +<td>Auto</td> +</tr> +<tr> +<td>-rom_extract</td> +<td> </td> +<td>Yes</td> +<td>Yes</td> +</tr> +<tr> +<td>-shreg_extract</td> +<td> </td> +<td>YES</td> +<td>Yes</td> +</tr> +<tr> +<td>-rom_style</td> +<td> </td> +<td>Auto</td> +<td>Auto</td> +</tr> +<tr> +<td>-auto_bram_packing</td> +<td> </td> +<td>NO</td> +<td>No</td> +</tr> +<tr> +<td>-resource_sharing</td> +<td> </td> +<td>YES</td> +<td>Yes</td> +</tr> +<tr> +<td>-async_to_sync</td> +<td> </td> +<td>NO</td> +<td>No</td> +</tr> +<tr> +<td>-use_dsp48</td> +<td> </td> +<td>Auto</td> +<td>Auto</td> +</tr> +<tr> +<td>-iobuf</td> +<td> </td> +<td>YES</td> +<td>Yes</td> +</tr> +<tr> +<td>-max_fanout</td> +<td> </td> +<td>100000</td> +<td>100000</td> +</tr> +<tr> +<td>-bufg</td> +<td> </td> +<td>16</td> +<td>16</td> +</tr> +<tr> +<td>-register_duplication</td> +<td> </td> +<td>YES</td> +<td>Yes</td> +</tr> +<tr> +<td>-register_balancing</td> +<td> </td> +<td>No</td> +<td>No</td> +</tr> +<tr> +<td>-optimize_primitives</td> +<td> </td> +<td>NO</td> +<td>No</td> +</tr> +<tr> +<td>-use_clock_enable</td> +<td> </td> +<td>Auto</td> +<td>Auto</td> +</tr> +<tr> +<td>-use_sync_set</td> +<td> </td> +<td>Auto</td> +<td>Auto</td> +</tr> +<tr> +<td>-use_sync_reset</td> +<td> </td> +<td>Auto</td> +<td>Auto</td> +</tr> +<tr> +<td>-iob</td> +<td> </td> +<td>Auto</td> +<td>Auto</td> +</tr> +<tr> +<td>-equivalent_register_removal</td> +<td> </td> +<td>YES</td> +<td>Yes</td> +</tr> +<tr> +<td>-slice_utilization_ratio_maxmargin</td> +<td> </td> +<td>5</td> +<td>0</td> +</tr> +</TABLE> +<A NAME="Operating System Information"></A> + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'> +<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD> +</tr> +<tr bgcolor='#ffff99'> +<td><b>Operating System Information</b></td> +<td><b>xst</b></td> +<td><b>ngdbuild</b></td> +<td><b>map</b></td> +<td><b>par</b></td> +</tr> +<tr> +<td>CPU Architecture/Speed</td> +<td>Intel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>Host</td> +<td>ECE-PHO115-09</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>OS Name</td> +<td>Microsoft Windows 7 , 64-bit</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +<tr> +<td>OS Release</td> +<td>Service Pack 1 (build 7601)</td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +<td><font color=gray>< data not available ></font></td> +</tr> +</TABLE> +</BODY> </HTML>
\ No newline at end of file diff --git a/ALUSHOW_summary.html b/ALUSHOW_summary.html new file mode 100644 index 0000000..56bb337 --- /dev/null +++ b/ALUSHOW_summary.html @@ -0,0 +1,84 @@ +<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> +<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> +<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'> +<TD ALIGN=CENTER COLSPAN='4'><B>ALUSHOW Project Status (02/15/2012 - 21:35:26)</B></TD></TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> +<TD>lab2.xise</TD> +<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> +<TD> No Errors </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> +<TD>ALUSHOW</TD> +<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> +<TD>Synthesized</TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> +<TD>xc6slx16-3csg324</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> +<TD> +<font color="red"; face="Arial"><b>X </b></font> +<A HREF_DISABLED='/home/michael/Documents/School/EC311/lab2/_xmsgs/*.xmsgs?&DataKey=Error'>2 Errors (2 new)</A></TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> +<TD ALIGN=LEFT>No Warnings</TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> +<TD>Balanced</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> +<TD> + </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> +<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> +<TD> +<A HREF_DISABLED='/home/michael/Documents/School/EC311/lab2/ALUSHOW_envsettings.html'> +System Settings</A> +</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> +<TD> </TD> +</TR> +</TABLE> + + + + + + + + + + + + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> +<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> +<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> +<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab2/ALUSHOW.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Feb 15 20:30:08 2012</TD><TD ALIGN=LEFT><font color="red"; face="Arial"><b>X </b></font><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab2/_xmsgs/xst.xmsgs?&DataKey=Error'>2 Errors (2 new)</A></TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> +<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +</TABLE> + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> +<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> +</TABLE> + + +<br><center><b>Date Generated:</b> 02/15/2012 - 21:38:21</center> +</BODY></HTML>
\ No newline at end of file diff --git a/ALUSHOW_xst.xrpt b/ALUSHOW_xst.xrpt new file mode 100755 index 0000000..ef3c0f8 --- /dev/null +++ b/ALUSHOW_xst.xrpt @@ -0,0 +1,115 @@ +<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> +<document OS="nt64" product="ISE" version="13.3"> + + <!--The data in this file is primarily intended for consumption by Xilinx tools. + The structure and the elements are likely to change over the next few releases. + This means code written to parse this file will need to be revisited each subsequent release.--> + + <application stringID="Xst" timeStamp="Wed Feb 15 16:04:04 2012"> + <section stringID="User_Env"> + <table stringID="User_EnvVar"> + <column stringID="variable"/> + <column stringID="value"/> + <row stringID="row" value="0"> + <item stringID="variable" value="PATH"/> + <item stringID="value" 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DEFAULT="" label="-ofn" stringID="XST_OFN" value="ALUSHOW"/> + <item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/> + <item DEFAULT="" label="-p" stringID="XST_P" value="xc6slx16-3-csg324"/> + <item DEFAULT="" label="-top" stringID="XST_TOP" value="ALUSHOW"/> + <item DEFAULT="Speed" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/> + <item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/> + <item DEFAULT="No" label="-power" stringID="XST_POWER" value="NO"/> + <item DEFAULT="No" label="-iuc" stringID="XST_IUC" value="NO"/> + <item DEFAULT="No" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/> + <item DEFAULT="As_Optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/> + <item DEFAULT="No" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/> + <item DEFAULT="AllClockNets" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/> + <item DEFAULT="Yes" label="-read_cores" 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stringID="XST_SHREGMINSIZE" value="2"/> + <item DEFAULT="Auto" label="-use_dsp48" stringID="XST_USEDSP48" value="Auto"/> + <item DEFAULT="Yes" label="-iobuf" stringID="XST_IOBUF" value="YES"/> + <item DEFAULT="100000" label="-max_fanout" stringID="XST_MAXFANOUT" value="100000"/> + <item DEFAULT="16" label="-bufg" stringID="XST_BUFG" value="16"/> + <item DEFAULT="Yes" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/> + <item DEFAULT="No" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/> + <item DEFAULT="No" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/> + <item DEFAULT="Auto" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Auto"/> + <item DEFAULT="Auto" label="-use_sync_set" stringID="XST_USESYNCSET" value="Auto"/> + <item DEFAULT="Auto" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Auto"/> + <item DEFAULT="Auto" label="-iob" stringID="XST_IOB" value="Auto"/> + <item DEFAULT="Yes" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/> + <item DEFAULT="0" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/> + </section> + <section stringID="XST_ERRORS_STATISTICS"> + <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="2"/> + <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="0"/> + <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/> + </section> + </application> + +</document> diff --git a/ALU_summary.html b/ALU_summary.html new file mode 100755 index 0000000..4ca0738 --- /dev/null +++ b/ALU_summary.html @@ -0,0 +1,79 @@ +<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> +<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> +<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'> +<TD ALIGN=CENTER COLSPAN='4'><B>ALU Project Status</B></TD></TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> +<TD>lab2.xise</TD> +<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> +<TD> No Errors </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> +<TD>ALU</TD> +<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> +<TD>New (Failed)</TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> +<TD>xc6slx16-3csg324</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.3</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> +<TD>Balanced</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> +<TD> + </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> +<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> +<TD> </TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> +<TD> </TD> +</TR> +</TABLE> + + + + + + + + + + + + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> +<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> +<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> +<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +</TABLE> + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> +<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> +</TABLE> + + +<br><center><b>Date Generated:</b> 02/15/2012 - 16:06:19</center> +</BODY></HTML>
\ No newline at end of file diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs new file mode 100755 index 0000000..2211003 --- /dev/null +++ b/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,12 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated --> +<!-- by the Xilinx ISE software. Any direct editing or --> +<!-- changes made to this file may result in unpredictable --> +<!-- behavior or data corruption. It is strongly advised that --> +<!-- users do not edit the contents of this file. --> +<!-- --> +<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> + +<messages> +</messages> + diff --git a/_xmsgs/xst.xmsgs b/_xmsgs/xst.xmsgs new file mode 100755 index 0000000..8233bd5 --- /dev/null +++ b/_xmsgs/xst.xmsgs @@ -0,0 +1,15 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +<msg type="error" file="HDLCompiler" num="44" delta="new" >"\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 26: <arg fmt="%s" index="1">out3</arg> is not a constant
+</msg>
+ +<msg type="error" file="HDLCompiler" num="598" delta="new" >"\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 21: Module <<arg fmt="%s" index="1">ALU</arg>> ignored due to previous errors.
+</msg>
+ +</messages> +
diff --git a/iseconfig/ALU.xreport b/iseconfig/ALU.xreport new file mode 100755 index 0000000..9524671 --- /dev/null +++ b/iseconfig/ALU.xreport @@ -0,0 +1,215 @@ +<?xml version='1.0' encoding='UTF-8'?> +<report-views version="2.0" > + <header> + <DateModified>2012-02-15T15:36:44</DateModified> + <ModuleName>ALU</ModuleName> + <SummaryTimeStamp>Unknown</SummaryTimeStamp> + <SavedFilePath>X:/My Documents/ec311/lab2/iseconfig/ALU.xreport</SavedFilePath> + <ImplementationReportsDirectory>X:/My Documents/ec311/lab2</ImplementationReportsDirectory> + <DateInitialized>2012-02-15T15:30:47</DateInitialized> + <EnableMessageFiltering>false</EnableMessageFiltering> + </header> + <body> + <viewgroup label="Design Overview" > + <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="ALU_summary.html" label="Summary" > + <toc-item title="Design Overview" target="Design Overview" /> + <toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> + <toc-item title="Performance Summary" target="Performance Summary" /> + <toc-item title="Failing Constraints" target="Failing Constraints" /> + <toc-item title="Detailed Reports" target="Detailed Reports" /> + </view> + <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="ALU_envsettings.html" label="System Settings" /> + <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="ALU_map.xrpt" label="IOB Properties" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="ALU_map.xrpt" label="Control Set Information" /> + <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="ALU_map.xrpt" label="Module Level Utilization" /> + <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="ALU.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" /> + <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="ALU_par.xrpt" label="Pinout Report" /> + <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="ALU_par.xrpt" label="Clock Report" /> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="ALU.twx" label="Static Timing" /> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="ALU_html/fit/report.htm" label="CPLD Fitter Report" /> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="ALU_html/tim/report.htm" label="CPLD Timing Report" /> + </viewgroup> + <viewgroup label="XPS Errors and Warnings" > + <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> + <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> + <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> + </viewgroup> + <viewgroup label="XPS Reports" > + <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" /> + <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> + <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> + <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="ALU.log" label="System Log File" /> + </viewgroup> + <viewgroup label="Errors and Warnings" > + <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> + <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" /> + <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" /> + <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" /> + <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" /> + <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" /> + <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" /> + <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" /> + <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" /> + <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" /> + <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" /> + </viewgroup> + <viewgroup label="Detailed Reports" > + <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="ALU.syr" label="Synthesis Report" > + <toc-item title="Top of Report" target="Copyright " searchDir="Forward" /> + <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> + <toc-item title="HDL Compilation" target=" HDL Compilation " /> + <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> + <toc-item title="HDL Analysis" target=" HDL Analysis " /> + <toc-item title="HDL Parsing" target=" HDL Parsing " /> + <toc-item title="HDL Elaboration" target=" HDL Elaboration " /> + <toc-item title="HDL Synthesis" target=" HDL Synthesis " /> + <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" /> + <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" /> + <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" /> + <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " /> + <toc-item title="Partition Report" target=" Partition Report " /> + <toc-item title="Final Report" target=" Final Report " /> + <toc-item title="Design Summary" target=" Design Summary " /> + <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" /> + <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" /> + <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" /> + <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" /> + <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" /> + <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" /> + <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" /> + <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" /> + <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" /> + </view> + <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="ALU.srr" label="Synplify Report" /> + <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="ALU.prec_log" label="Precision Report" /> + <view inputState="Synthesized" program="ngdbuild" type="Report" file="ALU.bld" label="Translation Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Command Line" target="Command Line:" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> + </view> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="ALU_map.mrp" label="Map Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> + <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" /> + <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" /> + <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" /> + <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" /> + <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" /> + <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" /> + <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" /> + <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" /> + <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" /> + <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" /> + <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" /> + <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="ALU.par" label="Place and Route Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Device Utilization" target="Device Utilization Summary:" /> + <toc-item title="Router Information" target="Starting Router" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Clock Report" target="Generating Clock Report" /> + <toc-item title="Timing Results" target="Timing Score:" /> + <toc-item title="Final Summary" target="Peak Memory Usage:" /> + </view> + <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="ALU.twr" label="Post-PAR Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="ALU.rpt" label="CPLD Fitter Report (Text)" > + <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" /> + <toc-item title="Resources Summary" target="** Mapped Resource Summary **" /> + <toc-item title="Pin Resources" target="** Pin Resources **" /> + <toc-item title="Global Resources" target="** Global Control Resources **" /> + </view> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="ALU.tim" label="CPLD Timing Report (Text)" > + <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> + <toc-item title="Performance Summary" target="Performance Summary:" /> + </view> + <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="ALU.pwr" label="Power Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Power summary" target="Power summary" /> + <toc-item title="Thermal summary" target="Thermal summary" /> + </view> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="ALU.bgn" label="Bitgen Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> + <toc-item title="Final Summary" target="DRC detected" /> + </view> + </viewgroup> + <viewgroup label="Secondary Reports" > + <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> + <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/ALU_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/ALU_translate.nlf" label="Post-Translate Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="ALU_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="ALU_map.map" label="Map Log File" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Design Information" target="Design Information" /> + <toc-item title="Design Summary" target="Design Summary" /> + </view> + <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" /> + <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALU_preroute.twr" label="Post-Map Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/ALU_map.nlf" label="Post-Map Simulation Model Report" /> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALU_map.psr" label="Physical Synthesis Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="ALU_pad.txt" label="Pad Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="ALU.unroutes" label="Unroutes Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALU_preroute.tsi" label="Post-Map Constraints Interaction Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALU.grf" label="Guide Results Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALU.dly" label="Asynchronous Delay Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALU.clk_rgn" label="Clock Region Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALU.tsi" label="Post-Place and Route Constraints Interaction Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="ALU_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" /> + <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/ALU_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="ALU_sta.nlf" label="Primetime Netlist Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="ALU.ibs" label="IBIS Model" > + <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" /> + <toc-item title="Component" target="Component " /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALU.lck" label="Back-annotate Pin Report" > + <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" /> + <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALU.lpc" label="Locked Pin Constraints" > + <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" /> + <toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> + </view> + <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/ALU_timesim.nlf" label="Post-Fit Simulation Model Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" /> + </viewgroup> + </body> +</report-views> diff --git a/iseconfig/ALUSHOW.xreport b/iseconfig/ALUSHOW.xreport new file mode 100644 index 0000000..4332a20 --- /dev/null +++ b/iseconfig/ALUSHOW.xreport @@ -0,0 +1,215 @@ +<?xml version='1.0' encoding='UTF-8'?> +<report-views version="2.0" > + <header> + <DateModified>2012-02-15T21:38:21</DateModified> + <ModuleName>ALUSHOW</ModuleName> + <SummaryTimeStamp>2012-02-15T21:35:26</SummaryTimeStamp> + <SavedFilePath>/home/michael/Documents/School/EC311/lab2/iseconfig/ALUSHOW.xreport</SavedFilePath> + <ImplementationReportsDirectory>/home/michael/Documents/School/EC311/lab2</ImplementationReportsDirectory> + <DateInitialized>2012-02-15T21:18:06</DateInitialized> + <EnableMessageFiltering>false</EnableMessageFiltering> + </header> + <body> + <viewgroup label="Design Overview" > + <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="ALUSHOW_summary.html" label="Summary" > + <toc-item title="Design Overview" target="Design Overview" /> + <toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> + <toc-item title="Performance Summary" target="Performance Summary" /> + <toc-item title="Failing Constraints" target="Failing Constraints" /> + <toc-item title="Detailed Reports" target="Detailed Reports" /> + </view> + <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="ALUSHOW_envsettings.html" label="System Settings" /> + <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="ALUSHOW_map.xrpt" label="IOB Properties" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="ALUSHOW_map.xrpt" label="Control Set Information" /> + <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="ALUSHOW_map.xrpt" label="Module Level Utilization" /> + <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="ALUSHOW.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" /> + <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="ALUSHOW_par.xrpt" label="Pinout Report" /> + <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="ALUSHOW_par.xrpt" label="Clock Report" /> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="ALUSHOW.twx" label="Static Timing" /> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="ALUSHOW_html/fit/report.htm" label="CPLD Fitter Report" /> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="ALUSHOW_html/tim/report.htm" label="CPLD Timing Report" /> + </viewgroup> + <viewgroup label="XPS Errors and Warnings" > + <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> + <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> + <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> + </viewgroup> + <viewgroup label="XPS Reports" > + <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" /> + <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> + <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> + <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="ALUSHOW.log" label="System Log File" /> + </viewgroup> + <viewgroup label="Errors and Warnings" > + <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> + <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" /> + <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" /> + <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" /> + <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" /> + <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" /> + <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" /> + <view inputState="Routed" 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Implementation Messages (CPLD)" /> + </viewgroup> + <viewgroup label="Detailed Reports" > + <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="ALUSHOW.syr" label="Synthesis Report" > + <toc-item title="Top of Report" target="Copyright " searchDir="Forward" /> + <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> + <toc-item title="HDL Compilation" target=" HDL Compilation " /> + <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> + <toc-item title="HDL Analysis" target=" HDL Analysis " /> + <toc-item title="HDL Parsing" target=" HDL Parsing " /> + <toc-item title="HDL Elaboration" target=" HDL Elaboration " /> + <toc-item title="HDL Synthesis" target=" HDL Synthesis " /> + <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" /> + <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " 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<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="ALUSHOW_map.mrp" label="Map Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> + <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" /> + <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" /> + <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" /> + <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" /> + <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" /> + <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" /> + <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" /> + <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" 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summary" /> + </view> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="ALUSHOW.bgn" label="Bitgen Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> + <toc-item title="Final Summary" target="DRC detected" /> + </view> + </viewgroup> + <viewgroup label="Secondary Reports" > + <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> + <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/ALUSHOW_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/ALUSHOW_translate.nlf" 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file="ALUSHOW_map.psr" label="Physical Synthesis Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="ALUSHOW_pad.txt" label="Pad Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="ALUSHOW.unroutes" label="Unroutes Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALUSHOW_preroute.tsi" label="Post-Map Constraints Interaction Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALUSHOW.grf" label="Guide Results Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALUSHOW.dly" label="Asynchronous Delay Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALUSHOW.clk_rgn" label="Clock Region Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALUSHOW.tsi" label="Post-Place and Route Constraints Interaction Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="ALUSHOW_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" /> + <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/ALUSHOW_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="ALUSHOW_sta.nlf" label="Primetime Netlist Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="ALUSHOW.ibs" label="IBIS Model" > + <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" /> + <toc-item title="Component" target="Component " /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALUSHOW.lck" label="Back-annotate Pin Report" > + <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" /> + <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="ALUSHOW.lpc" label="Locked Pin Constraints" > + <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" /> + <toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> + </view> + <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/ALUSHOW_timesim.nlf" label="Post-Fit Simulation Model Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" /> + </viewgroup> + </body> +</report-views> diff --git a/iseconfig/lab2.projectmgr b/iseconfig/lab2.projectmgr new file mode 100755 index 0000000..c48c152 --- /dev/null +++ b/iseconfig/lab2.projectmgr @@ -0,0 +1,106 @@ +<?xml version='1.0' encoding='utf-8'?> +<!--This is an ISE project configuration file.--> +<!--It holds project specific layout data for the projectmgr plugin.--> +<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.--> +<Project version="2" owner="projectmgr" name="lab2" > + <!--This is an ISE project configuration file.--> + <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem>ALUSHOW (/home/michael/Documents/School/EC311/lab2/ALUSHOW.sch)</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000150000000020000000000000000000000000200000064ffffffff000000810000000300000002000001500000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> + <CurrentItem>ALUSHOW (/home/michael/Documents/School/EC311/lab2/ALUSHOW.sch)</CurrentItem> + </ItemView> + <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Design Utilities</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Design Utilities</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000132000000010000000100000000000000000000000064ffffffff000000810000000000000001000001320000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Design Utilities</CurrentItem> + </ItemView> + <ItemView guiview="File" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems/> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000287000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000001bb0000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>ALU.v</CurrentItem> + </ItemView> + <ItemView guiview="Library" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>work</ClosedNode> + </ClosedNodes> + <SelectedItems/> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000117000000010001000100000000000000000000000064ffffffff000000810000000000000001000001170000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>work</CurrentItem> + </ItemView> + <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Configure Target Device</ClosedNode> + <ClosedNode>Implement Design</ClosedNode> + <ClosedNode>Synthesize - XST</ClosedNode> + <ClosedNode>User Constraints</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Create Schematic Symbol</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Create Schematic Symbol</CurrentItem> + </ItemView> + <ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem></SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem></CurrentItem> + </ItemView> + <ItemView engineview="SynthesisOnly" sourcetype="DESUT_SCHEMATIC" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Configure Target Device</ClosedNode> + <ClosedNode>Design Utilities</ClosedNode> + <ClosedNode>Implement Design</ClosedNode> + <ClosedNode>Synthesize - XST</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem></SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem></CurrentItem> + </ItemView> + <SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView> + <CurrentView>Implementation</CurrentView> +</Project> diff --git a/lab2.gise b/lab2.gise new file mode 100755 index 0000000..ec644a8 --- /dev/null +++ b/lab2.gise @@ -0,0 +1,98 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="lab2.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_SPL" xil_pn:name="ALU.spl"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="ALU.sym" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="ALUSHOW.cmd_log"/>
+ <file xil_pn:fileType="FILE_JHD" xil_pn:name="ALUSHOW.jhd"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="ALUSHOW.lso"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ALUSHOW.prj"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="ALUSHOW.syr"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="ALUSHOW.vf"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="ALUSHOW.xst"/>
+ <file xil_pn:fileType="FILE_XRPT" xil_pn:name="ALUSHOW_xst.xrpt"/>
+ <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="sev_seg_disp.sym" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="sev_seg_disp.vf"/>
+ <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
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+ </files>
+
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+ <status xil_pn:value="SuccessfullyRun"/>
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+ <transform xil_pn:end_ts="1329338123" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1329338123">
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+ <status xil_pn:value="OutOfDateForPredecessor"/>
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+ <status xil_pn:value="SuccessfullyRun"/>
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+ <outfile xil_pn:name="ALUSHOW.jhd"/>
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+ <outfile xil_pn:name="ALUSHOW.prj"/>
+ <outfile xil_pn:name="ALUSHOW.syr"/>
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+ <outfile xil_pn:name="ALUSHOW_xst.xrpt"/>
+ <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
+ <outfile xil_pn:name="webtalk_pn.xml"/>
+ <outfile xil_pn:name="xst"/>
+ </transform>
+ </transforms>
+
+</generated_project>
diff --git a/lab2.xise b/lab2.xise new file mode 100755 index 0000000..c5e520e --- /dev/null +++ b/lab2.xise @@ -0,0 +1,370 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="ALU.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> + </file> + <file xil_pn:name="ALUSHOW.sch" xil_pn:type="FILE_SCHEMATIC"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> + <association xil_pn:name="Implementation" xil_pn:seqID="3"/> + </file> + <file xil_pn:name="sev_seg_disp.sch" xil_pn:type="FILE_SCHEMATIC"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="ALUSHOW.ucf" xil_pn:type="FILE_UCF"> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + </file> + </files> + + <properties> + <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> + 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<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Output File Name" xil_pn:value="ALUSHOW" xil_pn:valueState="default"/> + <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="default"/> + <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> + <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> + <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> + <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> + <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="ALUSHOW_map.v" xil_pn:valueState="default"/> + <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="ALUSHOW_timesim.v" xil_pn:valueState="default"/> + <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="ALUSHOW_synthesis.v" xil_pn:valueState="default"/> + <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="ALUSHOW_translate.v" xil_pn:valueState="default"/> + <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> + <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> + <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> + <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/> + <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/> + <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> + <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> + <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> + <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> + <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> + <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> + <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/> + <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> + <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> + <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> + <property xil_pn:name="Target UCF File Name" xil_pn:value="ALU.ucf" xil_pn:valueState="non-default"/> + <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> + <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> + <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> + <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> + <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> + <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> + <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> + <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_DesignName" xil_pn:value="lab2" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-02-15T15:29:59" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="CFA30C52A63E43D8A2FABC7B29B0C236" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/pa.fromHdl.tcl b/pa.fromHdl.tcl new file mode 100755 index 0000000..2112f38 --- /dev/null +++ b/pa.fromHdl.tcl @@ -0,0 +1,19 @@ + +# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator + +create_project -name lab2 -dir "/home/michael/Documents/School/EC311/lab2/planAhead_run_2" -part xc6slx16csg324-3 +set_param project.pinAheadLayout yes +set srcset [get_property srcset [current_run -impl]] +set_property target_constrs_file "ALUSHOW.ucf" [current_fileset -constrset] +set hdlfile [add_files [list {sev_seg_disp.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {ALU.v}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {ALUSHOW.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set_property top ALUSHOW $srcset +add_files [list {ALUSHOW.ucf}] -fileset [get_property constrset [current_run]] +open_rtl_design -part xc6slx16csg324-3 diff --git a/planAhead_run_1/planAhead.jou b/planAhead_run_1/planAhead.jou new file mode 100644 index 0000000..f233ed4 --- /dev/null +++ b/planAhead_run_1/planAhead.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# PlanAhead v13.4 (64-bit) +# Build 157570 by hdbuild on Fri Dec 16 12:49:33 MST 2011 +# Start of session at: Wed Feb 15 21:35:38 2012 +# Process ID: 29568 +# Log file: /home/michael/Documents/School/EC311/lab2/planAhead_run_1/planAhead.log +# Journal file: /home/michael/Documents/School/EC311/lab2/planAhead_run_1/planAhead.jou +#----------------------------------------------------------- +start_gui +source /home/michael/Documents/School/EC311/lab2/pa.fromHdl.tcl +exit +stop_gui diff --git a/planAhead_run_1/planAhead.log b/planAhead_run_1/planAhead.log new file mode 100644 index 0000000..469ec29 --- /dev/null +++ b/planAhead_run_1/planAhead.log @@ -0,0 +1,57 @@ +#----------------------------------------------------------- +# PlanAhead v13.4 (64-bit) +# Build 157570 by hdbuild on Fri Dec 16 12:49:33 MST 2011 +# Start of session at: Wed Feb 15 21:35:38 2012 +# Process ID: 29568 +# Log file: /home/michael/Documents/School/EC311/lab2/planAhead_run_1/planAhead.log +# Journal file: /home/michael/Documents/School/EC311/lab2/planAhead_run_1/planAhead.jou +#----------------------------------------------------------- +INFO: [Common-78] Attempting to get a license: PlanAhead +INFO: [Common-82] Got a license: PlanAhead +INFO: [Device-25] Loading parts and site information from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/arch.xmlParsing RTL primitives file [/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml] +Finished parsing RTL primitives file [/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml] +start_gui +source /home/michael/Documents/School/EC311/lab2/pa.fromHdl.tcl +# create_project -name lab2 -dir "/home/michael/Documents/School/EC311/lab2/planAhead_run_2" -part xc6slx16csg324-3 +Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/verilog.xml]. +Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/verilog.xml]. +Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/vhdl.xml]. +Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/vhdl.xml]. +Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/ucf.xml]. +Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/ucf.xml]. +# set_param project.pinAheadLayout yes +# set srcset [get_property srcset [current_run -impl]] +# set_property target_constrs_file "ALUSHOW.ucf" [current_fileset -constrset] +Adding file '/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf' to fileset 'constrs_1' +# set hdlfile [add_files [list {sev_seg_disp.vf}]] +# set_property file_type Verilog $hdlfile +# set_property library work $hdlfile +# set hdlfile [add_files [list {ALU.v}]] +# set_property file_type Verilog $hdlfile +# set_property library work $hdlfile +# set hdlfile [add_files [list {ALUSHOW.vf}]] +# set_property file_type Verilog $hdlfile +# set_property library work $hdlfile +# set_property top ALUSHOW $srcset +# add_files [list {ALUSHOW.ucf}] -fileset [get_property constrset [current_run]] +# open_rtl_design -part xc6slx16csg324-3 +INFO: [PlanAhead-58] Using Verific elaboration +Parsing VHDL file "/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplify +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab2/ALU.v" into library work +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab2/ALUSHOW.vf" into library work +CRITICAL WARNING: [EDIF-96] Could not resolve non-primitive black box cell 'ALU' defined in file 'ALU.v' instantiated as 'XLXI_4'. +Loading clock regions from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml +Loading clock buffers from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml +Loading package pin functions from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/PinFunctions.xml... +Loading package from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml +Loading io standards from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/./parts/xilinx/spartan6/IOStandards.xml +Loading device configuration modes from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/ConfigModes.xml +Loading list of drcs for the architecture : /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/./parts/xilinx/spartan6/drc.xml +Parsing UCF File [/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf] +Finished Parsing UCF File [/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf] +INFO: [PlanAhead-566] Unisim Transformation Summary: +No Unisim elements were transformed.open_rtl_design: Time (s): 20.520u 0.570s 28.760w. Memory (MB): 4537.992p 149.031g +exit +stop_gui +INFO: [PlanAhead-261] Exiting PlanAhead... +INFO: [Common-83] Releasing license: PlanAhead diff --git a/planAhead_run_1/planAhead_run.log b/planAhead_run_1/planAhead_run.log new file mode 100644 index 0000000..c3acc99 --- /dev/null +++ b/planAhead_run_1/planAhead_run.log @@ -0,0 +1,54 @@ + +****** PlanAhead v13.4 (64-bit) + **** Build 157570 by hdbuild on Fri Dec 16 12:49:33 MST 2011 + ** Copyright 1986-1999, 2001-2011 Xilinx, Inc. All Rights Reserved. + +INFO: [Common-78] Attempting to get a license: PlanAhead +INFO: [Common-82] Got a license: PlanAhead +INFO: [Device-25] Loading parts and site information from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/arch.xmlParsing RTL primitives file [/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml] +Finished parsing RTL primitives file [/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml] +start_gui +starting gui ... +source /home/michael/Documents/School/EC311/lab2/pa.fromHdl.tcl +# create_project -name lab2 -dir "/home/michael/Documents/School/EC311/lab2/planAhead_run_2" -part xc6slx16csg324-3 +Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/verilog.xml]. +Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/verilog.xml]. +Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/vhdl.xml]. +Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/vhdl.xml]. +Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/ucf.xml]. +Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/ucf.xml]. +# set_param project.pinAheadLayout yes +# set srcset [get_property srcset [current_run -impl]] +# set_property target_constrs_file "ALUSHOW.ucf" [current_fileset -constrset] +Adding file '/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf' to fileset 'constrs_1' +# set hdlfile [add_files [list {sev_seg_disp.vf}]] +# set_property file_type Verilog $hdlfile +# set_property library work $hdlfile +# set hdlfile [add_files [list {ALU.v}]] +# set_property file_type Verilog $hdlfile +# set_property library work $hdlfile +# set hdlfile [add_files [list {ALUSHOW.vf}]] +# set_property file_type Verilog $hdlfile +# set_property library work $hdlfile +# set_property top ALUSHOW $srcset +# add_files [list {ALUSHOW.ucf}] -fileset [get_property constrset [current_run]] +# open_rtl_design -part xc6slx16csg324-3 +INFO: [PlanAhead-58] Using Verific elaboration +Parsing VHDL file "/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplify +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab2/ALU.v" into library work +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab2/ALUSHOW.vf" into library work +Loading clock regions from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml +Loading clock buffers from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml +Loading package pin functions from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/PinFunctions.xml... +Loading package from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml +Loading io standards from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/./parts/xilinx/spartan6/IOStandards.xml +Loading device configuration modes from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/ConfigModes.xml +Loading list of drcs for the architecture : /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/./parts/xilinx/spartan6/drc.xml +Parsing UCF File [/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf] +Finished Parsing UCF File [/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf] +INFO: [PlanAhead-566] Unisim Transformation Summary: +No Unisim elements were transformed.open_rtl_design: Time (s): 20.520u 0.570s 28.760w. Memory (MB): 4537.992p 149.031g +exit +stop_gui +INFO: [PlanAhead-261] Exiting PlanAhead... +INFO: [Common-83] Releasing license: PlanAhead diff --git a/planAhead_run_2/lab2.data/constrs_1/fileset.xml b/planAhead_run_2/lab2.data/constrs_1/fileset.xml new file mode 100644 index 0000000..528719e --- /dev/null +++ b/planAhead_run_2/lab2.data/constrs_1/fileset.xml @@ -0,0 +1,25 @@ +<?xml version="1.0" encoding="UTF-8"?> +<DARoots Version="1" + Minor="19"> + <FileSet Name="constrs_1" + Type="Constrs" + RelSrcDir="$PSRCDIR/constrs_1"> + <Filter Type="Constrs"/> + <File Path="$PPRDIR/../ALUSHOW.ucf"> + <FileInfo> + <Attr Name="UsedInSynthesis" + Val="1"/> + <Attr Name="UsedInImplementation" + Val="1"/> + <Attr Name="UsedInSimulation" + Val="1"/> + </FileInfo> + </File> + <Config> + <Option Name="TargetConstrsFile" + Val="$PPRDIR/../ALUSHOW.ucf"/> + <Option Name="ConstrsType" + Val="UCF"/> + </Config> + </FileSet> +</DARoots> diff --git a/planAhead_run_2/lab2.data/sources_1/fileset.xml b/planAhead_run_2/lab2.data/sources_1/fileset.xml new file mode 100644 index 0000000..3358a4c --- /dev/null +++ b/planAhead_run_2/lab2.data/sources_1/fileset.xml @@ -0,0 +1,51 @@ +<?xml version="1.0" encoding="UTF-8"?> +<DARoots Version="1" + Minor="19"> + <FileSet Name="sources_1" + Type="DesignSrcs" + RelSrcDir="$PSRCDIR/sources_1"> + <Filter Type="Srcs"/> + <File Path="$PPRDIR/../sev_seg_disp.vf"> + <FileInfo> + <Attr Name="UsedInSynthesis" + Val="1"/> + <Attr Name="UsedInImplementation" + Val="1"/> + <Attr Name="UsedInSimulation" + Val="1"/> + </FileInfo> + </File> + <File Path="$PPRDIR/../ALU.v"> + <FileInfo> + <Attr Name="UsedInSynthesis" + Val="1"/> + <Attr Name="UsedInImplementation" + Val="1"/> + <Attr Name="UsedInSimulation" + Val="1"/> + </FileInfo> + </File> + <File Path="$PPRDIR/../ALUSHOW.vf"> + <FileInfo> + <Attr Name="UsedInSynthesis" + Val="1"/> + <Attr Name="UsedInImplementation" + Val="1"/> + <Attr Name="UsedInSimulation" + Val="1"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" + Val="RTL"/> + <Option Name="TopModule" + Val="ALUSHOW"/> + <Option Name="TopLib" + Val="work"/> + <Option Name="TopRTLFile" + Val="$PPRDIR/../ALUSHOW.vf"/> + <Option Name="TopAutoSet" + Val="TRUE"/> + </Config> + </FileSet> +</DARoots> diff --git a/planAhead_run_2/lab2.data/wt/webtalk_pa.xml b/planAhead_run_2/lab2.data/wt/webtalk_pa.xml new file mode 100644 index 0000000..f06abbd --- /dev/null +++ b/planAhead_run_2/lab2.data/wt/webtalk_pa.xml @@ -0,0 +1,30 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<document> +<!--The data in this file is primarily intended for consumption by Xilinx tools. +The structure and the elements are likely to change over the next few releases. +This means code written to parse this file will need to be revisited each subsequent release.--> +<application name="pa" timeStamp="Wed Feb 15 21:37:58 2012"> +<section name="Project Information" visible="false"> +<property name="ProjectID" value="f01d355e589f494db7281c1ebb207295" type="ProjectID"/> +<property name="ProjectIteration" value="1" type="ProjectIteration"/> +</section> +<section name="PlanAhead Usage" visible="true"> +<item name="Project Data"> +<property name="SrcSetCount" value="1" type="SrcSetCount"/> +<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/> +<property name="DesignMode" value="RTL" type="DesignMode"/> +<property name="SynthesisStrategy" value="PlanAhead Defaults" type="SynthesisStrategy"/> +<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/> +</item> +<item name="Java Command Handlers"> +<property name="FileExit" value="1" type="JavaHandler"/> +</item> +<item name="Other"> +<property name="GuiMode" value="0" type="GuiMode"/> +<property name="BatchMode" value="0" type="BatchMode"/> +<property name="TclMode" value="0" type="TclMode"/> +<property name="ISEMode" value="2" type="ISEMode"/> +</item> +</section> +</application> +</document> diff --git a/planAhead_run_2/lab2.ppr b/planAhead_run_2/lab2.ppr new file mode 100644 index 0000000..99df0f9 --- /dev/null +++ b/planAhead_run_2/lab2.ppr @@ -0,0 +1,13 @@ +<?xml version="1.0"?> +<Project Version="4" Minor="27"> + <FileSet Dir="sources_1" File="fileset.xml"/> + <FileSet Dir="constrs_1" File="fileset.xml"/> + <DefaultLaunch Dir="$PRUNDIR"/> + <DefaultPromote Dir="$PROMOTEDIR"/> + <Config> + <Option Name="Part" Val="xc6slx16csg324-3"/> + <Option Name="TargetLanguage" Val="Verilog"/> + <Option Name="SourceMgmtMode" Val="All"/> + </Config> +</Project> + diff --git a/sch2HdlBatchFile b/sch2HdlBatchFile new file mode 100644 index 0000000..f4ab378 --- /dev/null +++ b/sch2HdlBatchFile @@ -0,0 +1,2 @@ +sch2hdl,-intstyle,ise,-family,spartan6,-verilog,/home/michael/Documents/School/EC311/lab2/ALUSHOW.vf,-w,/home/michael/Documents/School/EC311/lab2/ALUSHOW.sch +sch2hdl,-intstyle,ise,-family,spartan6,-verilog,/home/michael/Documents/School/EC311/lab2/sev_seg_disp.vf,-w,/home/michael/Documents/School/EC311/lab2/sev_seg_disp.sch diff --git a/sev_seg_disp.jhd b/sev_seg_disp.jhd new file mode 100755 index 0000000..30cf3b6 --- /dev/null +++ b/sev_seg_disp.jhd @@ -0,0 +1 @@ +MODULE sev_seg_disp
diff --git a/sev_seg_disp.sch b/sev_seg_disp.sch new file mode 100755 index 0000000..58d0e07 --- /dev/null +++ b/sev_seg_disp.sch @@ -0,0 +1,976 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<drawing version="7">
+ <attr value="spartan6" name="DeviceFamilyName">
+ <trait delete="all:0" />
+ <trait editname="all:0" />
+ <trait edittrait="all:0" />
+ </attr>
+ <netlist>
+ <signal name="XLXN_61" />
+ <signal name="XLXN_62" />
+ <signal name="XLXN_63" />
+ <signal name="XLXN_64" />
+ <signal name="XLXN_65" />
+ <signal name="A" />
+ <signal name="B" />
+ <signal name="C" />
+ <signal name="D" />
+ <signal name="A_BAR" />
+ <signal name="B_BAR" />
+ <signal name="C_BAR" />
+ <signal name="D_BAR" />
+ <signal name="XLXN_91" />
+ <signal name="XLXN_92" />
+ <signal name="XLXN_93" />
+ <signal name="XLXN_94" />
+ <signal name="XLXN_105" />
+ <signal name="XLXN_113" />
+ <signal name="XLXN_114" />
+ <signal name="XLXN_125" />
+ <signal name="XLXN_126" />
+ <signal name="XLXN_128" />
+ <signal name="XLXN_129" />
+ <signal name="XLXN_130" />
+ <signal name="XLXN_131" />
+ <signal name="XLXN_145" />
+ <signal name="XLXN_146" />
+ <signal name="XLXN_147" />
+ <signal name="XLXN_148" />
+ <signal name="XLXN_149" />
+ <signal name="a_out" />
+ <signal name="XLXN_151" />
+ <signal name="b_out" />
+ <signal name="c_out" />
+ <signal name="XLXN_155" />
+ <signal name="XLXN_156" />
+ <signal name="d_out" />
+ <signal name="XLXN_158" />
+ <signal name="e_out" />
+ <signal name="XLXN_160" />
+ <signal name="f_out" />
+ <signal name="XLXN_162" />
+ <signal name="g_out" />
+ <signal name="XLXN_165" />
+ <signal name="sign" />
+ <signal name="XLXN_166" />
+ <signal name="XLXN_14" />
+ <signal name="AN0" />
+ <signal name="AN1" />
+ <signal name="AN2" />
+ <signal name="AN3" />
+ <signal name="XLXN_24" />
+ <port polarity="Input" name="A" />
+ <port polarity="Input" name="B" />
+ <port polarity="Input" name="C" />
+ <port polarity="Input" name="D" />
+ <port polarity="Output" name="a_out" />
+ <port polarity="Output" name="b_out" />
+ <port polarity="Output" name="c_out" />
+ <port polarity="Output" name="d_out" />
+ <port polarity="Output" name="e_out" />
+ <port polarity="Output" name="f_out" />
+ <port polarity="Output" name="g_out" />
+ <port polarity="Output" name="sign" />
+ <port polarity="Output" name="AN0" />
+ <port polarity="Output" name="AN1" />
+ <port polarity="Output" name="AN2" />
+ <port polarity="Output" name="AN3" />
+ <blockdef name="or3">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="48" y1="-64" y2="-64" x1="0" />
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+ <line x2="48" y1="-176" y2="-176" x1="112" />
+ </blockdef>
+ <blockdef name="xnor2">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-64" y2="-64" x1="0" />
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+ <circle r="8" cx="220" cy="-96" />
+ <line x2="256" y1="-96" y2="-96" x1="228" />
+ <line x2="60" y1="-28" y2="-28" x1="60" />
+ </blockdef>
+ <blockdef name="inv">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-32" y2="-32" x1="0" />
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+ <circle r="16" cx="144" cy="-32" />
+ </blockdef>
+ <blockdef name="xor2">
+ <timestamp>2000-1-1T10:10:10</timestamp>
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+ <arc ex="208" ey="-96" sx="128" sy="-48" r="88" cx="132" cy="-136" />
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+ <blockdef name="and2">
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+ </blockdef>
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+ </blockdef>
+ <blockdef name="or4">
+ <timestamp>2000-1-1T10:10:10</timestamp>
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+ </blockdef>
+ <blockdef name="and3">
+ <timestamp>2000-1-1T10:10:10</timestamp>
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+ </blockdef>
+ <blockdef name="or5">
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+ </blockdef>
+ <blockdef name="buf">
+ <timestamp>2000-1-1T10:10:10</timestamp>
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+ <line x2="64" y1="-64" y2="0" x1="64" />
+ </blockdef>
+ <blockdef name="gnd">
+ <timestamp>2000-1-1T10:10:10</timestamp>
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+ </blockdef>
+ <blockdef name="vcc">
+ <timestamp>2000-1-1T10:10:10</timestamp>
+ <line x2="64" y1="-32" y2="-64" x1="64" />
+ <line x2="64" y1="0" y2="-32" x1="64" />
+ <line x2="32" y1="-64" y2="-64" x1="96" />
+ </blockdef>
+ <block symbolname="and3" name="XLXI_30">
+ <blockpin signalname="B" name="I0" />
+ <blockpin signalname="C_BAR" name="I1" />
+ <blockpin signalname="D" name="I2" />
+ <blockpin signalname="XLXN_61" name="O" />
+ </block>
+ <block symbolname="and3" name="XLXI_31">
+ <blockpin signalname="A_BAR" name="I0" />
+ <blockpin signalname="D" name="I1" />
+ <blockpin signalname="C" name="I2" />
+ <blockpin signalname="XLXN_62" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_32">
+ <blockpin signalname="B_BAR" name="I0" />
+ <blockpin signalname="D_BAR" name="I1" />
+ <blockpin signalname="XLXN_63" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_33">
+ <blockpin signalname="C" name="I0" />
+ <blockpin signalname="D_BAR" name="I1" />
+ <blockpin signalname="XLXN_64" name="O" />
+ </block>
+ <block symbolname="or5" name="XLXI_34">
+ <blockpin signalname="XLXN_65" name="I0" />
+ <blockpin signalname="XLXN_64" name="I1" />
+ <blockpin signalname="XLXN_63" name="I2" />
+ <blockpin signalname="XLXN_62" name="I3" />
+ <blockpin signalname="XLXN_61" name="I4" />
+ <blockpin signalname="XLXN_149" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_35">
+ <blockpin signalname="B_BAR" name="I0" />
+ <blockpin signalname="A" name="I1" />
+ <blockpin signalname="XLXN_65" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_37">
+ <blockpin signalname="A" name="I" />
+ <blockpin signalname="A_BAR" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_38">
+ <blockpin signalname="B" name="I" />
+ <blockpin signalname="B_BAR" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_39">
+ <blockpin signalname="C" name="I" />
+ <blockpin signalname="C_BAR" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_40">
+ <blockpin signalname="D" name="I" />
+ <blockpin signalname="D_BAR" name="O" />
+ </block>
+ <block symbolname="or4" name="XLXI_41">
+ <blockpin signalname="XLXN_94" name="I0" />
+ <blockpin signalname="XLXN_93" name="I1" />
+ <blockpin signalname="XLXN_92" name="I2" />
+ <blockpin signalname="XLXN_91" name="I3" />
+ <blockpin signalname="XLXN_151" name="O" />
+ </block>
+ <block symbolname="xnor2" name="XLXI_42">
+ <blockpin signalname="B" name="I0" />
+ <blockpin signalname="A" name="I1" />
+ <blockpin signalname="XLXN_91" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_43">
+ <blockpin signalname="D_BAR" name="I0" />
+ <blockpin signalname="C_BAR" name="I1" />
+ <blockpin signalname="XLXN_92" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_44">
+ <blockpin signalname="B_BAR" name="I0" />
+ <blockpin signalname="C_BAR" name="I1" />
+ <blockpin signalname="XLXN_93" name="O" />
+ </block>
+ <block symbolname="and3" name="XLXI_45">
+ <blockpin signalname="A_BAR" name="I0" />
+ <blockpin signalname="D" name="I1" />
+ <blockpin signalname="C" name="I2" />
+ <blockpin signalname="XLXN_94" name="O" />
+ </block>
+ <block symbolname="xor2" name="XLXI_46">
+ <blockpin signalname="B" name="I0" />
+ <blockpin signalname="A" name="I1" />
+ <blockpin signalname="XLXN_105" name="O" />
+ </block>
+ <block symbolname="or3" name="XLXI_47">
+ <blockpin signalname="D" name="I0" />
+ <blockpin signalname="C_BAR" name="I1" />
+ <blockpin signalname="XLXN_105" name="I2" />
+ <blockpin signalname="XLXN_155" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_48">
+ <blockpin signalname="D_BAR" name="I0" />
+ <blockpin signalname="C" name="I1" />
+ <blockpin signalname="XLXN_125" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_49">
+ <blockpin signalname="D_BAR" name="I0" />
+ <blockpin signalname="B_BAR" name="I1" />
+ <blockpin signalname="XLXN_126" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_50">
+ <blockpin signalname="C" name="I0" />
+ <blockpin signalname="B_BAR" name="I1" />
+ <blockpin signalname="XLXN_113" name="O" />
+ </block>
+ <block symbolname="and3" name="XLXI_51">
+ <blockpin signalname="C_BAR" name="I0" />
+ <blockpin signalname="D" name="I1" />
+ <blockpin signalname="B" name="I2" />
+ <blockpin signalname="XLXN_114" name="O" />
+ </block>
+ <block symbolname="or4" name="XLXI_52">
+ <blockpin signalname="XLXN_114" name="I0" />
+ <blockpin signalname="XLXN_113" name="I1" />
+ <blockpin signalname="XLXN_126" name="I2" />
+ <blockpin signalname="XLXN_125" name="I3" />
+ <blockpin signalname="XLXN_156" name="O" />
+ </block>
+ <block symbolname="or2" name="XLXI_53">
+ <blockpin signalname="XLXN_126" name="I0" />
+ <blockpin signalname="XLXN_125" name="I1" />
+ <blockpin signalname="XLXN_158" name="O" />
+ </block>
+ <block symbolname="and3" name="XLXI_54">
+ <blockpin signalname="C_BAR" name="I0" />
+ <blockpin signalname="B" name="I1" />
+ <blockpin signalname="A_BAR" name="I2" />
+ <blockpin signalname="XLXN_128" name="O" />
+ </block>
+ <block symbolname="and3" name="XLXI_55">
+ <blockpin signalname="C" name="I0" />
+ <blockpin signalname="B_BAR" name="I1" />
+ <blockpin signalname="A" name="I2" />
+ <blockpin signalname="XLXN_129" name="O" />
+ </block>
+ <block symbolname="and3" name="XLXI_56">
+ <blockpin signalname="D_BAR" name="I0" />
+ <blockpin signalname="B" name="I1" />
+ <blockpin signalname="A_BAR" name="I2" />
+ <blockpin signalname="XLXN_130" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_57">
+ <blockpin signalname="D_BAR" name="I0" />
+ <blockpin signalname="C_BAR" name="I1" />
+ <blockpin signalname="XLXN_131" name="O" />
+ </block>
+ <block symbolname="or4" name="XLXI_58">
+ <blockpin signalname="XLXN_131" name="I0" />
+ <blockpin signalname="XLXN_130" name="I1" />
+ <blockpin signalname="XLXN_129" name="I2" />
+ <blockpin signalname="XLXN_128" name="I3" />
+ <blockpin signalname="XLXN_160" name="O" />
+ </block>
+ <block symbolname="or4" name="XLXI_60">
+ <blockpin signalname="XLXN_148" name="I0" />
+ <blockpin signalname="XLXN_147" name="I1" />
+ <blockpin signalname="XLXN_146" name="I2" />
+ <blockpin signalname="XLXN_145" name="I3" />
+ <blockpin signalname="XLXN_162" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_61">
+ <blockpin signalname="C_BAR" name="I0" />
+ <blockpin signalname="B" name="I1" />
+ <blockpin signalname="XLXN_145" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_62">
+ <blockpin signalname="D_BAR" name="I0" />
+ <blockpin signalname="C" name="I1" />
+ <blockpin signalname="XLXN_146" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_63">
+ <blockpin signalname="B_BAR" name="I0" />
+ <blockpin signalname="C" name="I1" />
+ <blockpin signalname="XLXN_147" name="O" />
+ </block>
+ <block symbolname="and2" name="XLXI_64">
+ <blockpin signalname="D_BAR" name="I0" />
+ <blockpin signalname="A" name="I1" />
+ <blockpin signalname="XLXN_148" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_65">
+ <blockpin signalname="XLXN_149" name="I" />
+ <blockpin signalname="a_out" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_66">
+ <blockpin signalname="XLXN_151" name="I" />
+ <blockpin signalname="b_out" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_67">
+ <blockpin signalname="XLXN_155" name="I" />
+ <blockpin signalname="c_out" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_68">
+ <blockpin signalname="XLXN_158" name="I" />
+ <blockpin signalname="e_out" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_69">
+ <blockpin signalname="XLXN_156" name="I" />
+ <blockpin signalname="d_out" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_70">
+ <blockpin signalname="XLXN_160" name="I" />
+ <blockpin signalname="f_out" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_71">
+ <blockpin signalname="XLXN_162" name="I" />
+ <blockpin signalname="g_out" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_72">
+ <blockpin signalname="A_BAR" name="I" />
+ <blockpin signalname="XLXN_165" name="O" />
+ </block>
+ <block symbolname="inv" name="XLXI_73">
+ <blockpin signalname="XLXN_165" name="I" />
+ <blockpin signalname="sign" name="O" />
+ </block>
+ <block symbolname="buf" name="XLXI_5">
+ <blockpin signalname="XLXN_14" name="I" />
+ <blockpin signalname="AN0" name="O" />
+ </block>
+ <block symbolname="buf" name="XLXI_6">
+ <blockpin signalname="XLXN_14" name="I" />
+ <blockpin signalname="AN1" name="O" />
+ </block>
+ <block symbolname="buf" name="XLXI_7">
+ <blockpin signalname="XLXN_14" name="I" />
+ <blockpin signalname="AN2" name="O" />
+ </block>
+ <block symbolname="buf" name="XLXI_8">
+ <blockpin signalname="XLXN_24" name="I" />
+ <blockpin signalname="AN3" name="O" />
+ </block>
+ <block symbolname="gnd" name="XLXI_11">
+ <blockpin signalname="XLXN_24" name="G" />
+ </block>
+ <block symbolname="vcc" name="XLXI_12">
+ <blockpin signalname="XLXN_14" name="P" />
+ </block>
+ </netlist>
+ <sheet sheetnum="1" width="3520" height="2720">
+ <instance x="400" y="272" name="XLXI_30" orien="R0" />
+ <instance x="400" y="496" name="XLXI_31" orien="R0" />
+ <instance x="384" y="656" name="XLXI_32" orien="R0" />
+ <instance x="384" y="864" name="XLXI_33" orien="R0" />
+ <instance x="800" y="608" name="XLXI_34" orien="R0" />
+ <instance x="416" y="1056" name="XLXI_35" orien="R0" />
+ <branch name="XLXN_61">
+ <wire x2="800" y1="144" y2="144" x1="656" />
+ <wire x2="800" y1="144" y2="288" x1="800" />
+ </branch>
+ <branch name="XLXN_62">
+ <wire x2="720" y1="368" y2="368" x1="656" />
+ <wire x2="720" y1="352" y2="368" x1="720" />
+ <wire x2="800" y1="352" y2="352" x1="720" />
+ </branch>
+ <branch name="XLXN_63">
+ <wire x2="720" y1="560" y2="560" x1="640" />
+ <wire x2="720" y1="416" y2="560" x1="720" />
+ <wire x2="800" y1="416" y2="416" x1="720" />
+ </branch>
+ <branch name="XLXN_64">
+ <wire x2="736" y1="768" y2="768" x1="640" />
+ <wire x2="736" y1="480" y2="768" x1="736" />
+ <wire x2="800" y1="480" y2="480" x1="736" />
+ </branch>
+ <branch name="XLXN_65">
+ <wire x2="800" y1="960" y2="960" x1="672" />
+ <wire x2="800" y1="544" y2="960" x1="800" />
+ </branch>
+ <instance x="384" y="1280" name="XLXI_37" orien="R0" />
+ <instance x="384" y="1424" name="XLXI_38" orien="R0" />
+ <instance x="384" y="1568" name="XLXI_39" orien="R0" />
+ <instance x="384" y="1712" name="XLXI_40" orien="R0" />
+ <branch name="A">
+ <wire x2="384" y1="1248" y2="1248" x1="304" />
+ </branch>
+ <branch name="B">
+ <wire x2="384" y1="1392" y2="1392" x1="304" />
+ </branch>
+ <branch name="C">
+ <wire x2="384" y1="1536" y2="1536" x1="304" />
+ </branch>
+ <branch name="D">
+ <wire x2="384" y1="1680" y2="1680" x1="320" />
+ </branch>
+ <branch name="B_BAR">
+ <wire x2="688" y1="1392" y2="1392" x1="608" />
+ </branch>
+ <branch name="C_BAR">
+ <wire x2="688" y1="1536" y2="1536" x1="608" />
+ </branch>
+ <branch name="D_BAR">
+ <wire x2="688" y1="1680" y2="1680" x1="608" />
+ </branch>
+ <iomarker fontsize="28" x="304" y="1248" name="A" orien="R180" />
+ <iomarker fontsize="28" x="304" y="1392" name="B" orien="R180" />
+ <iomarker fontsize="28" x="304" y="1536" name="C" orien="R180" />
+ <iomarker fontsize="28" x="320" y="1680" name="D" orien="R180" />
+ <branch name="D">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="304" y="80" type="branch" />
+ <wire x2="400" y1="80" y2="80" x1="304" />
+ </branch>
+ <branch name="C_BAR">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="304" y="144" type="branch" />
+ <wire x2="400" y1="144" y2="144" x1="304" />
+ </branch>
+ <branch name="B">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="320" y="224" type="branch" />
+ <wire x2="400" y1="224" y2="224" x1="320" />
+ <wire x2="400" y1="208" y2="224" x1="400" />
+ </branch>
+ <branch name="C">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="304" y="304" type="branch" />
+ <wire x2="400" y1="304" y2="304" x1="304" />
+ </branch>
+ <branch name="D">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="304" y="368" type="branch" />
+ <wire x2="400" y1="368" y2="368" x1="304" />
+ </branch>
+ <branch name="A_BAR">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="304" y="432" type="branch" />
+ <wire x2="400" y1="432" y2="432" x1="304" />
+ </branch>
+ <branch name="D_BAR">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="304" y="528" type="branch" />
+ <wire x2="384" y1="528" y2="528" x1="304" />
+ </branch>
+ <branch name="B_BAR">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="304" y="592" type="branch" />
+ <wire x2="384" y1="592" y2="592" x1="304" />
+ </branch>
+ <branch name="D_BAR">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="320" y="736" type="branch" />
+ <wire x2="384" y1="736" y2="736" x1="320" />
+ </branch>
+ <branch name="C">
+ <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="320" y="800" type="branch" />
+ <wire x2="384" y1="800" y2="800" x1="320" />
+ <wire x2="320" y1="800" y2="816" x1="320" />
+ </branch>
+ <branch name="A">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="336" y="928" type="branch" />
+ <wire x2="416" y1="928" y2="928" x1="336" />
+ </branch>
+ <branch name="B_BAR">
+ <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="336" y="992" type="branch" />
+ <wire x2="416" y1="992" y2="992" x1="336" />
+ <wire x2="336" y1="992" y2="1008" x1="336" />
+ </branch>
+ <instance x="1968" y="528" name="XLXI_41" orien="R0" />
+ <instance x="1440" y="336" name="XLXI_42" orien="R0" />
+ <instance x="1456" y="528" name="XLXI_43" orien="R0" />
+ <instance x="1456" y="704" name="XLXI_44" orien="R0" />
+ <instance x="1456" y="944" name="XLXI_45" orien="R0" />
+ <branch name="XLXN_91">
+ <wire x2="1968" y1="240" y2="240" x1="1696" />
+ <wire x2="1968" y1="240" y2="272" x1="1968" />
+ </branch>
+ <branch name="XLXN_92">
+ <wire x2="1840" y1="432" y2="432" x1="1712" />
+ <wire x2="1840" y1="336" y2="432" x1="1840" />
+ <wire x2="1968" y1="336" y2="336" x1="1840" />
+ </branch>
+ <branch name="XLXN_93">
+ <wire x2="1856" y1="608" y2="608" x1="1712" />
+ <wire x2="1856" y1="400" y2="608" x1="1856" />
+ <wire x2="1968" y1="400" y2="400" x1="1856" />
+ </branch>
+ <branch name="XLXN_94">
+ <wire x2="1968" y1="816" y2="816" x1="1712" />
+ <wire x2="1968" y1="464" y2="816" x1="1968" />
+ </branch>
+ <branch name="A">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="1264" y="208" type="branch" />
+ <wire x2="1440" y1="208" y2="208" x1="1264" />
+ </branch>
+ <branch name="B">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="1280" y="272" type="branch" />
+ <wire x2="1440" y1="272" y2="272" x1="1280" />
+ </branch>
+ <branch name="C_BAR">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="1376" y="400" type="branch" />
+ <wire x2="1456" y1="400" y2="400" x1="1376" />
+ </branch>
+ <branch name="D_BAR">
+ <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1392" y="464" type="branch" />
+ <wire x2="1456" y1="464" y2="464" x1="1392" />
+ <wire x2="1392" y1="464" y2="480" x1="1392" />
+ </branch>
+ <branch name="C_BAR">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="1344" y="576" type="branch" />
+ <wire x2="1456" y1="576" y2="576" x1="1344" />
+ </branch>
+ <branch name="B_BAR">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="1344" y="640" type="branch" />
+ <wire x2="1456" y1="640" y2="640" x1="1344" />
+ </branch>
+ <branch name="C">
+ <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1360" y="752" type="branch" />
+ <wire x2="1456" y1="752" y2="752" x1="1360" />
+ <wire x2="1360" y1="752" y2="768" x1="1360" />
+ </branch>
+ <branch name="D">
+ <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1344" y="816" type="branch" />
+ <wire x2="1456" y1="816" y2="816" x1="1344" />
+ <wire x2="1344" y1="816" y2="832" x1="1344" />
+ </branch>
+ <branch name="A_BAR">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="1360" y="880" type="branch" />
+ <wire x2="1456" y1="880" y2="880" x1="1360" />
+ </branch>
+ <instance x="1312" y="1232" name="XLXI_46" orien="R0" />
+ <instance x="1696" y="1312" name="XLXI_47" orien="R0" />
+ <branch name="XLXN_105">
+ <wire x2="1632" y1="1136" y2="1136" x1="1568" />
+ <wire x2="1632" y1="1120" y2="1136" x1="1632" />
+ <wire x2="1696" y1="1120" y2="1120" x1="1632" />
+ </branch>
+ <branch name="C_BAR">
+ <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1584" y="1184" type="branch" />
+ <wire x2="1696" y1="1184" y2="1184" x1="1584" />
+ <wire x2="1584" y1="1184" y2="1200" x1="1584" />
+ </branch>
+ <branch name="D">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="1552" y="1264" type="branch" />
+ <wire x2="1696" y1="1264" y2="1264" x1="1552" />
+ <wire x2="1696" y1="1248" y2="1264" x1="1696" />
+ </branch>
+ <branch name="A">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="1232" y="1104" type="branch" />
+ <wire x2="1312" y1="1104" y2="1104" x1="1232" />
+ </branch>
+ <branch name="B">
+ <attrtext style="alignment:SOFT-RIGHT;fontsize:28;fontname:Arial" attrname="Name" x="1232" y="1168" type="branch" />
+ <wire x2="1312" y1="1168" y2="1168" x1="1232" />
+ </branch>
+ <instance x="1408" y="1520" name="XLXI_48" orien="R0" />
+ <instance x="1424" y="1712" name="XLXI_49" orien="R0" />
+ <instance x="1440" y="1904" name="XLXI_50" orien="R0" />
+ <instance x="1456" y="2128" name="XLXI_51" orien="R0" />
+ <instance x="1840" y="1776" name="XLXI_52" orien="R0" />
+ <branch name="XLXN_113">
+ <wire x2="1760" y1="1808" y2="1808" x1="1696" />
+ <wire x2="1760" y1="1648" y2="1808" x1="1760" />
+ <wire x2="1840" y1="1648" y2="1648" x1="1760" />
+ </branch>
+ <branch name="XLXN_114">
+ <wire x2="1840" y1="2000" y2="2000" x1="1712" />
+ <wire x2="1840" y1="1712" y2="2000" x1="1840" />
+ </branch>
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+ <branch name="B">
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+ <wire x2="2960" y1="416" y2="432" x1="2960" />
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+ <wire x2="2656" y1="416" y2="416" x1="2560" />
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+ <wire x2="3008" y1="1552" y2="1664" x1="3008" />
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+ <wire x2="2944" y1="1728" y2="1744" x1="2944" />
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+ <wire x2="2960" y1="1792" y2="1936" x1="2960" />
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+ <branch name="B">
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+ <wire x2="2640" y1="1712" y2="1712" x1="2544" />
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+ <branch name="D_BAR">
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+ <wire x2="2640" y1="1776" y2="1776" x1="2544" />
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+ <wire x2="2672" y1="1904" y2="1904" x1="2576" />
+ </branch>
+ <branch name="B_BAR">
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+ <wire x2="2672" y1="1968" y2="1968" x1="2592" />
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+ <wire x2="2688" y1="2080" y2="2080" x1="2576" />
+ </branch>
+ <branch name="D_BAR">
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+ <wire x2="2688" y1="2144" y2="2144" x1="2576" />
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+ <instance x="928" y="800" name="XLXI_65" orien="R0" />
+ <instance x="2112" y="688" name="XLXI_66" orien="R0" />
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+ <instance x="2480" y="1232" name="XLXI_68" orien="R0" />
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+ <iomarker fontsize="28" x="1184" y="768" name="a_out" orien="R0" />
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+ <wire x2="624" y1="2176" y2="2256" x1="624" />
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+ </branch>
+ <iomarker fontsize="28" x="896" y="2000" name="AN0" orien="R0" />
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+ <iomarker fontsize="28" x="896" y="2256" name="AN3" orien="R0" />
+ </sheet>
+</drawing>
\ No newline at end of file diff --git a/sev_seg_disp.sym b/sev_seg_disp.sym new file mode 100755 index 0000000..f408003 --- /dev/null +++ b/sev_seg_disp.sym @@ -0,0 +1,57 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="sev_seg_disp">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2012-2-8T3:29:18</timestamp>
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+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-512" type="pin B" />
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+ <line x2="384" y1="-544" y2="-544" x1="320" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-480" type="pin e_out" />
+ <line x2="384" y1="-480" y2="-480" x1="320" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-416" type="pin f_out" />
+ <line x2="384" y1="-416" y2="-416" x1="320" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-352" type="pin g_out" />
+ <line x2="384" y1="-352" y2="-352" x1="320" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-288" type="pin sign" />
+ <line x2="384" y1="-288" y2="-288" x1="320" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-224" type="pin AN0" />
+ <line x2="384" y1="-224" y2="-224" x1="320" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin AN1" />
+ <line x2="384" y1="-160" y2="-160" x1="320" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin AN2" />
+ <line x2="384" y1="-96" y2="-96" x1="320" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin AN3" />
+ <line x2="384" y1="-32" y2="-32" x1="320" />
+ </graph>
+</symbol>
diff --git a/sev_seg_disp.vf b/sev_seg_disp.vf new file mode 100644 index 0000000..abe413c --- /dev/null +++ b/sev_seg_disp.vf @@ -0,0 +1,236 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 13.4 +// \ \ Application : sch2hdl +// / / Filename : sev_seg_disp.vf +// /___/ /\ Timestamp : 02/15/2012 21:35:26 +// \ \ / \ +// \___\/\___\ +// +//Command: sch2hdl -intstyle ise -family spartan6 -verilog /home/michael/Documents/School/EC311/lab2/sev_seg_disp.vf -w /home/michael/Documents/School/EC311/lab2/sev_seg_disp.sch +//Design Name: sev_seg_disp +//Device: spartan6 +//Purpose: +// This verilog netlist is translated from an ECS schematic.It can be +// synthesized and simulated, but it should not be modified. +// +`timescale 1ns / 1ps + +module sev_seg_disp(A, + B, + C, + D, + AN0, + AN1, + AN2, + AN3, + a_out, + b_out, + c_out, + d_out, + e_out, + f_out, + g_out, + sign); + + input A; + input B; + input C; + input D; + output AN0; + output AN1; + output AN2; + output AN3; + output a_out; + output b_out; + output c_out; + output d_out; + output e_out; + output f_out; + output g_out; + output sign; + + wire A_BAR; + wire B_BAR; + wire C_BAR; + wire D_BAR; + wire XLXN_14; + wire XLXN_24; + wire XLXN_61; + wire XLXN_62; + wire XLXN_63; + wire XLXN_64; + wire XLXN_65; + wire XLXN_91; + wire XLXN_92; + wire XLXN_93; + wire XLXN_94; + wire XLXN_105; + wire XLXN_113; + wire XLXN_114; + wire XLXN_125; + wire XLXN_126; + wire XLXN_128; + wire XLXN_129; + wire XLXN_130; + wire XLXN_131; + wire XLXN_145; + wire XLXN_146; + wire XLXN_147; + wire XLXN_148; + wire XLXN_149; + wire XLXN_151; + wire XLXN_155; + wire XLXN_156; + wire XLXN_158; + wire XLXN_160; + wire XLXN_162; + wire XLXN_165; + + BUF XLXI_5 (.I(XLXN_14), + .O(AN0)); + BUF XLXI_6 (.I(XLXN_14), + .O(AN1)); + BUF XLXI_7 (.I(XLXN_14), + .O(AN2)); + BUF XLXI_8 (.I(XLXN_24), + .O(AN3)); + GND XLXI_11 (.G(XLXN_24)); + VCC XLXI_12 (.P(XLXN_14)); + AND3 XLXI_30 (.I0(B), + .I1(C_BAR), + .I2(D), + .O(XLXN_61)); + AND3 XLXI_31 (.I0(A_BAR), + .I1(D), + .I2(C), + .O(XLXN_62)); + AND2 XLXI_32 (.I0(B_BAR), + .I1(D_BAR), + .O(XLXN_63)); + AND2 XLXI_33 (.I0(C), + .I1(D_BAR), + .O(XLXN_64)); + OR5 XLXI_34 (.I0(XLXN_65), + .I1(XLXN_64), + .I2(XLXN_63), + .I3(XLXN_62), + .I4(XLXN_61), + .O(XLXN_149)); + AND2 XLXI_35 (.I0(B_BAR), + .I1(A), + .O(XLXN_65)); + INV XLXI_37 (.I(A), + .O(A_BAR)); + INV XLXI_38 (.I(B), + .O(B_BAR)); + INV XLXI_39 (.I(C), + .O(C_BAR)); + INV XLXI_40 (.I(D), + .O(D_BAR)); + OR4 XLXI_41 (.I0(XLXN_94), + .I1(XLXN_93), + .I2(XLXN_92), + .I3(XLXN_91), + .O(XLXN_151)); + XNOR2 XLXI_42 (.I0(B), + .I1(A), + .O(XLXN_91)); + AND2 XLXI_43 (.I0(D_BAR), + .I1(C_BAR), + .O(XLXN_92)); + AND2 XLXI_44 (.I0(B_BAR), + .I1(C_BAR), + .O(XLXN_93)); + AND3 XLXI_45 (.I0(A_BAR), + .I1(D), + .I2(C), + .O(XLXN_94)); + XOR2 XLXI_46 (.I0(B), + .I1(A), + .O(XLXN_105)); + OR3 XLXI_47 (.I0(D), + .I1(C_BAR), + .I2(XLXN_105), + .O(XLXN_155)); + AND2 XLXI_48 (.I0(D_BAR), + .I1(C), + .O(XLXN_125)); + AND2 XLXI_49 (.I0(D_BAR), + .I1(B_BAR), + .O(XLXN_126)); + AND2 XLXI_50 (.I0(C), + .I1(B_BAR), + .O(XLXN_113)); + AND3 XLXI_51 (.I0(C_BAR), + .I1(D), + .I2(B), + .O(XLXN_114)); + OR4 XLXI_52 (.I0(XLXN_114), + .I1(XLXN_113), + .I2(XLXN_126), + .I3(XLXN_125), + .O(XLXN_156)); + OR2 XLXI_53 (.I0(XLXN_126), + .I1(XLXN_125), + .O(XLXN_158)); + AND3 XLXI_54 (.I0(C_BAR), + .I1(B), + .I2(A_BAR), + .O(XLXN_128)); + AND3 XLXI_55 (.I0(C), + .I1(B_BAR), + .I2(A), + .O(XLXN_129)); + AND3 XLXI_56 (.I0(D_BAR), + .I1(B), + .I2(A_BAR), + .O(XLXN_130)); + AND2 XLXI_57 (.I0(D_BAR), + .I1(C_BAR), + .O(XLXN_131)); + OR4 XLXI_58 (.I0(XLXN_131), + .I1(XLXN_130), + .I2(XLXN_129), + .I3(XLXN_128), + .O(XLXN_160)); + OR4 XLXI_60 (.I0(XLXN_148), + .I1(XLXN_147), + .I2(XLXN_146), + .I3(XLXN_145), + .O(XLXN_162)); + AND2 XLXI_61 (.I0(C_BAR), + .I1(B), + .O(XLXN_145)); + AND2 XLXI_62 (.I0(D_BAR), + .I1(C), + .O(XLXN_146)); + AND2 XLXI_63 (.I0(B_BAR), + .I1(C), + .O(XLXN_147)); + AND2 XLXI_64 (.I0(D_BAR), + .I1(A), + .O(XLXN_148)); + INV XLXI_65 (.I(XLXN_149), + .O(a_out)); + INV XLXI_66 (.I(XLXN_151), + .O(b_out)); + INV XLXI_67 (.I(XLXN_155), + .O(c_out)); + INV XLXI_68 (.I(XLXN_158), + .O(e_out)); + INV XLXI_69 (.I(XLXN_156), + .O(d_out)); + INV XLXI_70 (.I(XLXN_160), + .O(f_out)); + INV XLXI_71 (.I(XLXN_162), + .O(g_out)); + INV XLXI_72 (.I(A_BAR), + .O(XLXN_165)); + INV XLXI_73 (.I(XLXN_165), + .O(sign)); +endmodule diff --git a/webtalk_pn.xml b/webtalk_pn.xml new file mode 100755 index 0000000..7067f28 --- /dev/null +++ b/webtalk_pn.xml @@ -0,0 +1,43 @@ +<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pn" timeStamp="Wed Feb 15 16:04:01 2012">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="CFA30C52A63E43D8A2FABC7B29B0C236" type="project"/>
+<property name="ProjectIteration" value="0" type="project"/>
+<property name="ProjectFile" value="X:/My Documents/ec311/lab2/lab2.xise" type="project"/>
+<property name="ProjectCreationTimestamp" value="2012-02-15T15:29:59" type="project"/>
+</section>
+<section name="Project Statistics" visible="true">
+<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
+<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
+<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
+<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
+<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
+<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
+<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
+<property name="PROP_SynthTopFile" value="changed" type="process"/>
+<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
+<property name="PROP_UseSmartGuide" value="false" type="design"/>
+<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
+<property name="PROP_intProjectCreationTimestamp" value="2012-02-15T15:29:59" type="design"/>
+<property name="PROP_intWbtProjectID" value="CFA30C52A63E43D8A2FABC7B29B0C236" type="design"/>
+<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
+<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
+<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
+<property name="PROP_AutoTop" value="true" type="design"/>
+<property name="PROP_DevFamily" value="Spartan6" type="design"/>
+<property name="PROP_DevDevice" value="xc6slx16" type="design"/>
+<property name="PROP_DevFamilyPMName" value="spartan6" type="design"/>
+<property name="PROP_DevPackage" value="csg324" type="design"/>
+<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
+<property name="PROP_DevSpeed" value="-3" type="design"/>
+<property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
+<property name="FILE_SCHEMATIC" value="2" type="source"/>
+<property name="FILE_UCF" value="1" type="source"/>
+<property name="FILE_VERILOG" value="1" type="source"/>
+</section>
+</application>
+</document>
|