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| author | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:55 -0500 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:55 -0500 |
| commit | 0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a (patch) | |
| tree | 0546ba14ba410a565b6bff722a23b26860744825 | |
| download | ec311-lab2-0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a.tar.gz ec311-lab2-0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a.tar.bz2 ec311-lab2-0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a.zip | |
initial commit
39 files changed, 4018 insertions, 0 deletions
diff --git a/ALU.cmd_log b/ALU.cmd_log new file mode 100755 index 0000000..044741b --- /dev/null +++ b/ALU.cmd_log @@ -0,0 +1,10 @@ +vhdtdtfi -lib work {X:/My Documents/ec311/lab2/ALU.v} -lang verilog -prj lab2 -o ALU.spl -module ALU -template C:/Xilinx/13.3/ISE_DS/ISE//data/splveri.tft -deleteonerror
+spl2sym -intstyle ise -family spartan6 ALU.spl {X:/My Documents/ec311/lab2/ALU.sym}
+vhdtdtfi -lib work {X:/My Documents/ec311/lab2/ALU.v} -lang verilog -prj lab2 -o ALU.spl -module ALU -template C:/Xilinx/13.3/ISE_DS/ISE//data/splveri.tft -deleteonerror
+spl2sym -intstyle ise -family spartan6 ALU.spl {X:/My Documents/ec311/lab2/ALU.sym}
+vhdtdtfi -lib work /home/michael/Documents/School/EC311/lab2/ALU.v -lang verilog -prj lab2 -o ALU.spl -module ALU -template /home/michael/opt/Xilinx/13.4/ISE_DS/ISE//data/splveri.tft -deleteonerror +spl2sym -intstyle ise -family spartan6 ALU.spl /home/michael/Documents/School/EC311/lab2/ALU.sym +vhdtdtfi -lib work /home/michael/Documents/School/EC311/lab2/ALU.v -lang verilog -prj lab2 -o ALU.spl -module ALU -template /home/michael/opt/Xilinx/13.4/ISE_DS/ISE//data/splveri.tft -deleteonerror +spl2sym -intstyle ise -family spartan6 -w ALU.spl /home/michael/Documents/School/EC311/lab2/ALU.sym +vhdtdtfi -lib work /home/michael/Documents/School/EC311/lab2/ALU.v -lang verilog -prj lab2 -o ALU.spl -module ALU -template /home/michael/opt/Xilinx/13.4/ISE_DS/ISE//data/splveri.tft -deleteonerror +spl2sym -intstyle ise -family spartan6 -w ALU.spl /home/michael/Documents/School/EC311/lab2/ALU.sym @@ -0,0 +1,9 @@ +[Inputs] +=s[1:0]= +=a[3:0]= +[Outputs] +=o[3:0]= +[BiDir] +[ATTRIBUTES] +VeriModel ALU + @@ -0,0 +1,22 @@ +<?xml version="1.0" encoding="UTF-8"?> +<symbol version="7" name="ALU"> + <symboltype>BLOCK</symboltype> + <timestamp>2012-2-16T2:38:45</timestamp> + <attr value="ALU" name="VeriModel" /> + <pin polarity="Input" x="0" y="416" name="s(1:0)" /> + <pin polarity="Input" x="0" y="480" name="a(3:0)" /> + <pin polarity="Output" x="384" y="416" name="o(3:0)" /> + <graph> + <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-136" type="symbol" /> + <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="416" type="pin s(1:0)" /> + <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="480" type="pin a(3:0)" /> + <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="416" type="pin o(3:0)" /> + <rect width="64" x="0" y="404" height="24" /> + <line x2="0" y1="416" y2="416" x1="64" /> + <rect width="64" x="0" y="468" height="24" /> + <line x2="0" y1="480" y2="480" x1="64" /> + <rect width="64" x="320" y="404" height="24" /> + <line x2="384" y1="416" y2="416" x1="320" /> + <rect width="256" x="64" y="-128" height="640" /> + </graph> +</symbol> @@ -0,0 +1,38 @@ +`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 15:30:47 02/15/2012
+// Design Name:
+// Module Name: ALU
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+module ALU(
+ input [1:0] s, + input [3:0] a,
+ output [3:0] o
+ );
+ +reg [3:0] o;
+
+always @ ( * )
+begin
+ case ( s )
+ 2'd0 : o = a;
+ 2'd1 : o = ~a+1;
+ 2'd2 : o = a >> 1;
+ 2'd3 : o = a % 3;
+ endcase
+end
+endmodule
diff --git a/ALUSHOW.cmd_log b/ALUSHOW.cmd_log new file mode 100755 index 0000000..bf0d338 --- /dev/null +++ b/ALUSHOW.cmd_log @@ -0,0 +1 @@ +xst -intstyle ise -ifn "X:/My Documents/ec311/lab2/ALUSHOW.xst" -ofn "X:/My Documents/ec311/lab2/ALUSHOW.syr"
diff --git a/ALUSHOW.jhd b/ALUSHOW.jhd new file mode 100755 index 0000000..5a366ed --- /dev/null +++ b/ALUSHOW.jhd @@ -0,0 +1,5 @@ +MODULE ALUSHOW + SUBMODULE sev_seg_disp + INSTANCE XLXI_2 + SUBMODULE ALU + INSTANCE XLXI_4 diff --git a/ALUSHOW.lso b/ALUSHOW.lso new file mode 100755 index 0000000..22de730 --- /dev/null +++ b/ALUSHOW.lso @@ -0,0 +1 @@ +work
diff --git a/ALUSHOW.prj b/ALUSHOW.prj new file mode 100755 index 0000000..714802f --- /dev/null +++ b/ALUSHOW.prj @@ -0,0 +1,3 @@ +verilog work "sev_seg_disp.vf"
+verilog work "ALU.v"
+verilog work "ALUSHOW.vf"
diff --git a/ALUSHOW.sch b/ALUSHOW.sch new file mode 100755 index 0000000..ba21753 --- /dev/null +++ b/ALUSHOW.sch @@ -0,0 +1,189 @@ +<?xml version="1.0" encoding="UTF-8"?> +<drawing version="7"> + <attr value="spartan6" name="DeviceFamilyName"> + <trait delete="all:0" /> + <trait editname="all:0" /> + <trait edittrait="all:0" /> + </attr> + <netlist> + <signal name="ao" /> + <signal name="bo" /> + <signal name="co" /> + <signal name="do" /> + <signal name="eo" /> + <signal name="fo" /> + <signal name="go" /> + <signal name="sign" /> + <signal name="AN0" /> + <signal name="AN1" /> + <signal name="AN2" /> + <signal name="AN3" /> + <signal name="ALU_OUT(3:0)" /> + <signal name="ALU_OUT(0)" /> + <signal name="ALU_OUT(1)" /> + <signal name="ALU_OUT(2)" /> + <signal name="ALU_OUT(3)" /> + <signal name="A(3:0)" /> + <signal name="S(1:0)" /> + <port polarity="Output" name="ao" /> + <port polarity="Output" name="bo" /> + <port polarity="Output" name="co" /> + <port polarity="Output" name="do" /> + <port polarity="Output" name="eo" /> + <port polarity="Output" name="fo" /> + <port polarity="Output" name="go" /> + <port polarity="Output" name="sign" /> + <port polarity="Output" name="AN0" /> + <port polarity="Output" name="AN1" /> + <port polarity="Output" name="AN2" /> + <port polarity="Output" name="AN3" /> + <port polarity="Input" name="A(3:0)" /> + <port polarity="Input" name="S(1:0)" /> + <blockdef name="sev_seg_disp"> + <timestamp>2012-2-15T18:55:28</timestamp> + <rect width="256" x="64" y="-768" height="768" /> + <line x2="0" y1="-736" y2="-736" x1="64" /> + <line x2="0" y1="-512" y2="-512" x1="64" /> + <line x2="0" y1="-288" y2="-288" x1="64" /> + <line x2="0" y1="-64" y2="-64" x1="64" /> + <line x2="384" y1="-736" y2="-736" x1="320" /> + <line x2="384" y1="-672" y2="-672" x1="320" /> + <line x2="384" y1="-608" y2="-608" x1="320" /> + <line x2="384" y1="-544" y2="-544" x1="320" /> + <line x2="384" y1="-480" y2="-480" x1="320" /> + <line x2="384" y1="-416" y2="-416" x1="320" /> + <line x2="384" y1="-352" y2="-352" x1="320" /> + <line x2="384" y1="-288" y2="-288" x1="320" /> + <line x2="384" y1="-224" y2="-224" x1="320" /> + <line x2="384" y1="-160" y2="-160" x1="320" /> + <line x2="384" y1="-96" y2="-96" x1="320" /> + <line x2="384" y1="-32" y2="-32" x1="320" /> + </blockdef> + <blockdef name="ALU"> + <timestamp>2012-2-16T2:38:45</timestamp> + <rect width="64" x="0" y="404" height="24" /> + <line x2="0" y1="416" y2="416" x1="64" /> + <rect width="64" x="0" y="468" height="24" /> + <line x2="0" y1="480" y2="480" x1="64" /> + <rect width="64" x="320" y="404" height="24" /> + <line x2="384" y1="416" y2="416" x1="320" /> + <rect width="256" x="64" y="-128" height="640" /> + </blockdef> + <block symbolname="sev_seg_disp" name="XLXI_2"> + <blockpin signalname="ALU_OUT(0)" name="A" /> + <blockpin signalname="ALU_OUT(1)" name="B" /> + <blockpin signalname="ALU_OUT(2)" name="C" /> + <blockpin signalname="ALU_OUT(3)" name="D" /> + <blockpin signalname="ao" name="a_out" /> + <blockpin signalname="bo" name="b_out" /> + <blockpin signalname="co" name="c_out" /> + <blockpin signalname="do" name="d_out" /> + <blockpin signalname="eo" name="e_out" /> + <blockpin signalname="fo" name="f_out" /> + <blockpin signalname="go" name="g_out" /> + <blockpin signalname="sign" name="sign" /> + <blockpin signalname="AN0" name="AN0" /> + <blockpin signalname="AN1" name="AN1" /> + <blockpin signalname="AN2" name="AN2" /> + <blockpin signalname="AN3" name="AN3" /> + </block> + <block symbolname="ALU" name="XLXI_4"> + <blockpin signalname="S(1:0)" name="s(1:0)" /> + <blockpin signalname="A(3:0)" name="a(3:0)" /> + <blockpin signalname="ALU_OUT(3:0)" name="o(3:0)" /> + </block> + </netlist> + <sheet sheetnum="1" width="3520" height="2720"> + <instance x="1728" y="1536" name="XLXI_2" orien="R0"> + </instance> + <branch name="ao"> + <wire x2="2144" y1="800" y2="800" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="800" name="ao" orien="R0" /> + <branch name="bo"> + <wire x2="2144" y1="864" y2="864" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="864" name="bo" orien="R0" /> + <branch name="co"> + <wire x2="2144" y1="928" y2="928" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="928" name="co" orien="R0" /> + <branch name="do"> + <wire x2="2144" y1="992" y2="992" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="992" name="do" orien="R0" /> + <branch name="eo"> + <wire x2="2144" y1="1056" y2="1056" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1056" name="eo" orien="R0" /> + <branch name="fo"> + <wire x2="2144" y1="1120" y2="1120" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1120" name="fo" orien="R0" /> + <branch name="go"> + <wire x2="2144" y1="1184" y2="1184" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1184" name="go" orien="R0" /> + <branch name="sign"> + <wire x2="2144" y1="1248" y2="1248" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1248" name="sign" orien="R0" /> + <branch name="AN0"> + <wire x2="2144" y1="1312" y2="1312" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1312" name="AN0" orien="R0" /> + <branch name="AN1"> + <wire x2="2144" y1="1376" y2="1376" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1376" name="AN1" orien="R0" /> + <branch name="AN2"> + <wire x2="2144" y1="1440" y2="1440" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1440" name="AN2" orien="R0" /> + <branch name="AN3"> + <wire x2="2144" y1="1504" y2="1504" x1="2112" /> + </branch> + <iomarker fontsize="28" x="2144" y="1504" name="AN3" orien="R0" /> + <instance x="880" y="1152" name="XLXI_4" orien="R0"> + </instance> + <branch name="ALU_OUT(3:0)"> + <wire x2="1376" y1="1568" y2="1568" x1="1264" /> + <wire x2="1376" y1="800" y2="1024" x1="1376" /> + <wire x2="1376" y1="1024" y2="1248" x1="1376" /> + <wire x2="1376" y1="1248" y2="1472" x1="1376" /> + <wire x2="1376" y1="1472" y2="1568" x1="1376" /> + </branch> + <bustap x2="1472" y1="800" y2="800" x1="1376" /> + <branch name="ALU_OUT(0)"> + <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1664" y="800" type="branch" /> + <wire x2="1664" y1="800" y2="800" x1="1472" /> + <wire x2="1728" y1="800" y2="800" x1="1664" /> + </branch> + <bustap x2="1472" y1="1024" y2="1024" x1="1376" /> + <branch name="ALU_OUT(1)"> + <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1632" y="1024" type="branch" /> + <wire x2="1632" y1="1024" y2="1024" x1="1472" /> + <wire x2="1728" y1="1024" y2="1024" x1="1632" /> + </branch> + <bustap x2="1472" y1="1248" y2="1248" x1="1376" /> + <branch name="ALU_OUT(2)"> + <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1568" y="1248" type="branch" /> + <wire x2="1568" y1="1248" y2="1248" x1="1472" /> + <wire x2="1728" y1="1248" y2="1248" x1="1568" /> + </branch> + <bustap x2="1472" y1="1472" y2="1472" x1="1376" /> + <branch name="ALU_OUT(3)"> + <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1568" y="1472" type="branch" /> + <wire x2="1568" y1="1472" y2="1472" x1="1472" /> + <wire x2="1728" y1="1472" y2="1472" x1="1568" /> + </branch> + <branch name="A(3:0)"> + <wire x2="880" y1="1632" y2="1632" x1="848" /> + </branch> + <iomarker fontsize="28" x="848" y="1632" name="A(3:0)" orien="R180" /> + <branch name="S(1:0)"> + <wire x2="880" y1="1568" y2="1568" x1="848" /> + </branch> + <iomarker fontsize="28" x="848" y="1568" name="S(1:0)" orien="R180" /> + </sheet> +</drawing>
\ No newline at end of file diff --git a/ALUSHOW.syr b/ALUSHOW.syr new file mode 100755 index 0000000..f10b0f6 --- /dev/null +++ b/ALUSHOW.syr @@ -0,0 +1,122 @@ +Release 13.3 - xst O.76xd (nt64) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to xst/projnav.tmp + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.11 secs + +--> Parameter xsthdpdir set to xst + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.12 secs + +--> Reading design: ALUSHOW.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Parsing + 3) HDL Elaboration + 4) HDL Synthesis + 4.1) HDL Synthesis Report + 5) Advanced HDL Synthesis + 5.1) Advanced HDL Synthesis Report + 6) Low Level Synthesis + 7) Partition Report + 8) Design Summary + 8.1) Primitive and Black Box Usage + 8.2) Device utilization summary + 8.3) Partition Resource Summary + 8.4) Timing Report + 8.4.1) Clock Information + 8.4.2) Asynchronous Control Signals Information + 8.4.3) Timing Summary + 8.4.4) Timing Details + 8.4.5) Cross Clock Domains Report + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "ALUSHOW.prj" +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "ALUSHOW" +Output Format : NGC +Target Device : xc6slx16-3-csg324 + +---- Source Options +Top Module Name : ALUSHOW +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : LUT +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Shift Register Extraction : YES +ROM Style : Auto +Resource Sharing : YES +Asynchronous To Synchronous : NO +Shift Register Minimum Size : 2 +Use DSP Block : Auto +Automatic Register Balancing : No + +---- Target Options +LUT Combining : Auto +Reduce Control Sets : Auto +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : Auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Power Reduction : NO +Keep Hierarchy : No +Netlist Hierarchy : As_Optimized +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : YES +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : Maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + + +========================================================================= +* HDL Parsing * +========================================================================= +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\sev_seg_disp.vf" into library work +Parsing module <sev_seg_disp>. +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" into library work +Parsing module <ALU>. +ERROR:HDLCompiler:44 - "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 26: out3 is not a constant +ERROR:HDLCompiler:598 - "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 21: Module <ALU> ignored due to previous errors. +Verilog file \\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v ignored due to errors +--> + +Total memory usage is 201016 kilobytes + +Number of errors : 2 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) + diff --git a/ALUSHOW.ucf b/ALUSHOW.ucf new file mode 100755 index 0000000..e69de29 --- /dev/null +++ b/ALUSHOW.ucf diff --git a/ALUSHOW.vf b/ALUSHOW.vf new file mode 100644 index 0000000..8662af8 --- /dev/null +++ b/ALUSHOW.vf @@ -0,0 +1,286 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 13.4 +// \ \ Application : sch2hdl +// / / Filename : ALUSHOW.vf +// /___/ /\ Timestamp : 02/15/2012 21:35:26 +// \ \ / \ +// \___\/\___\ +// +//Command: sch2hdl -intstyle ise -family spartan6 -verilog /home/michael/Documents/School/EC311/lab2/ALUSHOW.vf -w /home/michael/Documents/School/EC311/lab2/ALUSHOW.sch +//Design Name: ALUSHOW +//Device: spartan6 +//Purpose: +// This verilog netlist is translated from an ECS schematic.It can be +// synthesized and simulated, but it should not be modified. +// +`timescale 1ns / 1ps + +module sev_seg_disp_MUSER_ALUSHOW(A, + B, + C, + D, + AN0, + AN1, + AN2, + AN3, + a_out, + b_out, + c_out, + d_out, + e_out, + f_out, + g_out, + sign); + + input A; + input B; + input C; + input D; + output AN0; + output AN1; + output AN2; + output AN3; + output a_out; + output b_out; + output c_out; + output d_out; + output e_out; + output f_out; + output g_out; + output sign; + + wire A_BAR; + wire B_BAR; + wire C_BAR; + wire D_BAR; + wire XLXN_14; + wire XLXN_24; + wire XLXN_61; + wire XLXN_62; + wire XLXN_63; + wire XLXN_64; + wire XLXN_65; + wire XLXN_91; + wire XLXN_92; + wire XLXN_93; + wire XLXN_94; + wire XLXN_105; + wire XLXN_113; + wire XLXN_114; + wire XLXN_125; + wire XLXN_126; + wire XLXN_128; + wire XLXN_129; + wire XLXN_130; + wire XLXN_131; + wire XLXN_145; + wire XLXN_146; + wire XLXN_147; + wire XLXN_148; + wire XLXN_149; + wire XLXN_151; + wire XLXN_155; + wire XLXN_156; + wire XLXN_158; + wire XLXN_160; + wire XLXN_162; + wire XLXN_165; + + BUF XLXI_5 (.I(XLXN_14), + .O(AN0)); + BUF XLXI_6 (.I(XLXN_14), + .O(AN1)); + BUF XLXI_7 (.I(XLXN_14), + .O(AN2)); + BUF XLXI_8 (.I(XLXN_24), + .O(AN3)); + GND XLXI_11 (.G(XLXN_24)); + VCC XLXI_12 (.P(XLXN_14)); + AND3 XLXI_30 (.I0(B), + .I1(C_BAR), + .I2(D), + .O(XLXN_61)); + AND3 XLXI_31 (.I0(A_BAR), + .I1(D), + .I2(C), + .O(XLXN_62)); + AND2 XLXI_32 (.I0(B_BAR), + .I1(D_BAR), + .O(XLXN_63)); + AND2 XLXI_33 (.I0(C), + .I1(D_BAR), + .O(XLXN_64)); + OR5 XLXI_34 (.I0(XLXN_65), + .I1(XLXN_64), + .I2(XLXN_63), + .I3(XLXN_62), + .I4(XLXN_61), + .O(XLXN_149)); + AND2 XLXI_35 (.I0(B_BAR), + .I1(A), + .O(XLXN_65)); + INV XLXI_37 (.I(A), + .O(A_BAR)); + INV XLXI_38 (.I(B), + .O(B_BAR)); + INV XLXI_39 (.I(C), + .O(C_BAR)); + INV XLXI_40 (.I(D), + .O(D_BAR)); + OR4 XLXI_41 (.I0(XLXN_94), + .I1(XLXN_93), + .I2(XLXN_92), + .I3(XLXN_91), + .O(XLXN_151)); + XNOR2 XLXI_42 (.I0(B), + .I1(A), + .O(XLXN_91)); + AND2 XLXI_43 (.I0(D_BAR), + .I1(C_BAR), + .O(XLXN_92)); + AND2 XLXI_44 (.I0(B_BAR), + .I1(C_BAR), + .O(XLXN_93)); + AND3 XLXI_45 (.I0(A_BAR), + .I1(D), + .I2(C), + .O(XLXN_94)); + XOR2 XLXI_46 (.I0(B), + .I1(A), + .O(XLXN_105)); + OR3 XLXI_47 (.I0(D), + .I1(C_BAR), + .I2(XLXN_105), + .O(XLXN_155)); + AND2 XLXI_48 (.I0(D_BAR), + .I1(C), + .O(XLXN_125)); + AND2 XLXI_49 (.I0(D_BAR), + .I1(B_BAR), + .O(XLXN_126)); + AND2 XLXI_50 (.I0(C), + .I1(B_BAR), + .O(XLXN_113)); + AND3 XLXI_51 (.I0(C_BAR), + .I1(D), + .I2(B), + .O(XLXN_114)); + OR4 XLXI_52 (.I0(XLXN_114), + .I1(XLXN_113), + .I2(XLXN_126), + .I3(XLXN_125), + .O(XLXN_156)); + OR2 XLXI_53 (.I0(XLXN_126), + .I1(XLXN_125), + .O(XLXN_158)); + AND3 XLXI_54 (.I0(C_BAR), + .I1(B), + .I2(A_BAR), + .O(XLXN_128)); + AND3 XLXI_55 (.I0(C), + .I1(B_BAR), + .I2(A), + .O(XLXN_129)); + AND3 XLXI_56 (.I0(D_BAR), + .I1(B), + .I2(A_BAR), + .O(XLXN_130)); + AND2 XLXI_57 (.I0(D_BAR), + .I1(C_BAR), + .O(XLXN_131)); + OR4 XLXI_58 (.I0(XLXN_131), + .I1(XLXN_130), + .I2(XLXN_129), + .I3(XLXN_128), + .O(XLXN_160)); + OR4 XLXI_60 (.I0(XLXN_148), + .I1(XLXN_147), + .I2(XLXN_146), + .I3(XLXN_145), + .O(XLXN_162)); + AND2 XLXI_61 (.I0(C_BAR), + .I1(B), + .O(XLXN_145)); + AND2 XLXI_62 (.I0(D_BAR), + .I1(C), + .O(XLXN_146)); + AND2 XLXI_63 (.I0(B_BAR), + .I1(C), + .O(XLXN_147)); + AND2 XLXI_64 (.I0(D_BAR), + .I1(A), + .O(XLXN_148)); + INV XLXI_65 (.I(XLXN_149), + .O(a_out)); + INV XLXI_66 (.I(XLXN_151), + .O(b_out)); + INV XLXI_67 (.I(XLXN_155), + .O(c_out)); + INV XLXI_68 (.I(XLXN_158), + .O(e_out)); + INV XLXI_69 (.I(XLXN_156), + .O(d_out)); + INV XLXI_70 (.I(XLXN_160), + .O(f_out)); + INV XLXI_71 (.I(XLXN_162), + .O(g_out)); + INV XLXI_72 (.I(A_BAR), + .O(XLXN_165)); + INV XLXI_73 (.I(XLXN_165), + .O(sign)); +endmodule +`timescale 1ns / 1ps + +module ALUSHOW(AN0, + AN1, |