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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:16:12 03/16/2012 
+// Design Name: 
+// Module Name:    Bin2BCD 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Bin2BCD(
+    input [7:0] bin,
+    output [3:0] one,
+    output [3:0] ten,
+    output [3:0] hun
+    );
+
+reg [3:0] one, ten, hun;
+reg [19:0] work;
+reg [3:0] i;
+
+always @( bin ) begin
+	hun = 0; ten = 0; one = 0;
+	work = {hun, ten, one, bin};
+
+	for (i = 0; i < 7; i = i +1) begin
+		work = work << 1;
+		if (work[19:16] >= 5) begin
+			work[19:16] = work[19:16] + 3;
+		end
+		if (work[15:12] >= 5) begin
+			work[15:12] = work[15:12] + 3;
+		end
+		if (work[11:8] >= 5) begin
+			work[11:8] = work[11:8] + 3;
+		end
+	end
+	
+	work = work << 1;
+	
+	hun = work[19:16];
+	ten = work[15:12];
+	one = work[11:8];	
+end
+
+endmodule