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| author | Michael Abed <michaelabed@gmail.com> | 2012-03-21 13:17:47 -0400 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-03-21 13:17:47 -0400 |
| commit | 2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4 (patch) | |
| tree | 9819721233275cee6e39483867818a54299a4fc1 | |
| download | ec311-lab4-2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4.tar.gz ec311-lab4-2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4.tar.bz2 ec311-lab4-2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4.zip | |
Initial Commit
111 files changed, 8339 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..57cdc36 --- /dev/null +++ b/.gitignore @@ -0,0 +1,4 @@ + +*.wdb +*.exe +*.un~ diff --git a/BCD2Bin.v b/BCD2Bin.v new file mode 100644 index 0000000..06a38c8 --- /dev/null +++ b/BCD2Bin.v @@ -0,0 +1,58 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:39:02 03/16/2012 +// Design Name: +// Module Name: BCD2Bin +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module BCD2Bin( + input [3:0] hun, + input [3:0] ten, + input [3:0] one, + output [7:0] bin + ); + +reg [7:0] bin = 0; +reg [2:0] i = 0; + +reg [19:0] work; + +always @ ( hun, ten, one ) begin + + work = {hun, ten, one, bin}; + + //work = work >> 1; + + for (i = 0; i < 7; i = i + 1) begin + work = work >> 1; + if (work[19:16] >= 5) begin + work[19:16] = work[19:16] - 3; + end + if (work[15:12] >= 5) begin + work[15:12] = work[15:12] - 3; + end + if (work[11:8] >= 5) begin + work [11:8] = work[11:8] - 3; + end + end + + work = work >> 1; + + bin = work[7:0]; + +end + +endmodule diff --git a/Bin2BCD.v b/Bin2BCD.v new file mode 100644 index 0000000..ce79f2b --- /dev/null +++ b/Bin2BCD.v @@ -0,0 +1,56 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 10:16:12 03/16/2012 +// Design Name: +// Module Name: Bin2BCD +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Bin2BCD( + input [7:0] bin, + output [3:0] one, + output [3:0] ten, + output [3:0] hun + ); + +reg [3:0] one, ten, hun; +reg [19:0] work; +reg [3:0] i; + +always @( bin ) begin + hun = 0; ten = 0; one = 0; + work = {hun, ten, one, bin}; + + for (i = 0; i < 7; i = i +1) begin + work = work << 1; + if (work[19:16] >= 5) begin + work[19:16] = work[19:16] + 3; + end + if (work[15:12] >= 5) begin + work[15:12] = work[15:12] + 3; + end + if (work[11:8] >= 5) begin + work[11:8] = work[11:8] + 3; + end + end + + work = work << 1; + + hun = work[19:16]; + ten = work[15:12]; + one = work[11:8]; +end + +endmodule diff --git a/Bin2BCD_beh.prj b/Bin2BCD_beh.prj new file mode 100644 index 0000000..837a173 --- /dev/null +++ b/Bin2BCD_beh.prj @@ -0,0 +1,2 @@ +verilog work "Bin2BCD.v" +verilog work "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/Bin2BCD_summary.html b/Bin2BCD_summary.html new file mode 100644 index 0000000..f11693f --- /dev/null +++ b/Bin2BCD_summary.html @@ -0,0 +1,79 @@ +<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> +<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> +<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'> +<TD ALIGN=CENTER COLSPAN='4'><B>Bin2BCD Project Status</B></TD></TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> +<TD>lab4.xise</TD> +<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> +<TD> No Errors </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> +<TD>Bin2BCD</TD> +<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> +<TD>New</TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> +<TD>xc6slx16-3csg324</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> +<TD>Balanced</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> +<TD> + </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> +<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> +<TD> </TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> +<TD> </TD> +</TR> +</TABLE> + + + + + + + + + + + + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> +<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> +<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> +<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +</TABLE> + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> +<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> +</TABLE> + + +<br><center><b>Date Generated:</b> 03/16/2012 - 11:06:11</center> +</BODY></HTML>
\ No newline at end of file diff --git a/ClockDivider.v b/ClockDivider.v new file mode 100644 index 0000000..2447e7e --- /dev/null +++ b/ClockDivider.v @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:24:11 03/16/2012 +// Design Name: +// Module Name: ClockDivider +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ClockDivider( + input clk_in, + input rst, + input [23:0] count, + output clk_out + ); + +reg clk_out = 0; +reg [23:0] c = 0; + +always @(posedge clk_in or posedge rst) begin + if (rst == 1) begin + c = 0; + clk_out = 0; + end else if (c == count) begin + clk_out = ~clk_out; + c = 0; + end else begin + c = c + 1; + end + + +end + + + +endmodule diff --git a/Countdown.v b/Countdown.v new file mode 100644 index 0000000..78e4162 --- /dev/null +++ b/Countdown.v @@ -0,0 +1,57 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:51:02 03/16/2012 +// Design Name: +// Module Name: Countdown +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Countdown( + input clk_1hz, + input rst, + input start, + input [7:0] init, + output [7:0] t + ); + +reg [7:0] t; +reg running = 0; + +always @(init) begin + if (!running) begin + t = init; + end else begin + t = t; + end +end + +always @(posedge clk_1hz) begin + if (running) begin + t <= t - 1; + end else begin + t <= init; + end +end + +always @(posedge start) begin + running = 1; +end + +always @(rst) begin + running = 0; + t = 0; +end + +endmodule diff --git a/CountdownController.v b/CountdownController.v new file mode 100644 index 0000000..b06fa4b --- /dev/null +++ b/CountdownController.v @@ -0,0 +1,79 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:21:11 03/16/2012 +// Design Name: +// Module Name: CountdownController +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module CountdownController( + input btnA, + input btnB, + input btnC, + input clk, + input rst, + output [6:0] ssd, + output [3:0] AN + ); + +reg [6:0] ssd; +reg [3:0] AN; + +wire [6:0] ssdo; +wire [3:0] ANo; + +// clocks +wire seconds; +wire dbclk; +wire dispclk; + +// buttons +wire a, b; + +// bcd things +wire [3:0] ad, bd; +wire [3:0] ado, bdo, cdo; + +// time +wire [7:0] init; +wire [7:0] tout; + +ClockDivider dbc(.count(100), .rst(rst), .clk_in(clk), .clk_out(dbclk)); +ClockDivider sec(.count(100), .rst(rst), .clk_in(clk), .clk_out(seconds)); +ClockDivider dcc(.count(50), .rst(rst), .clk_in(clk), .clk_out(dispclk)); + +debouncer dbA(.dout(a), .din(btnA), .rst(rst), .clk_1M(dbclk)); +debouncer dbB(.dout(b), .din(btnB), .rst(rst), .clk_1M(dbclk)); + +//Increment inc1(.value(ad), .btn(a)); +//Increment inc2(.value(bd), .btn(b)); + +Increment inc1(.value(ad), .btn(btnA)); +Increment inc2(.value(bd), .btn(btnB)); + +BCD2Bin bcd2b(.hun(0), .ten(ad), .one(bd), .bin(init)); + +Countdown cntdwn(.t(tout), .rst(rst), .init(init), .clk_1hz(seconds), .start(btnC)); + +Bin2BCD b2bcb(.hun(cdo), .ten(ado), .one(bdo), .bin(tout)); + +DisplayController dispcont(.result(ssdo), .AN(ANo), .A(ado), .B(bdo), .clk_in(dispclk), .rst(rst)); + + +always @(posedge clk) begin + ssd <= ssdo; + AN <= ANo; +end +endmodule diff --git a/CountdownController_summary.html b/CountdownController_summary.html new file mode 100644 index 0000000..8dcf2d2 --- /dev/null +++ b/CountdownController_summary.html @@ -0,0 +1,80 @@ +<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> +<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> +<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'> +<TD ALIGN=CENTER COLSPAN='4'><B>CountdownController Project Status</B></TD></TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> +<TD>lab4.xise</TD> +<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> +<TD> No Errors </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> +<TD>CountdownController</TD> +<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> +<TD>New</TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> +<TD>xc6slx16-3csg324</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> +<TD>Balanced</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> +<TD> + </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> +<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> +<TD> </TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> +<TD> </TD> +</TR> +</TABLE> + + + + + + + + + + + + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> +<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> +<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> +<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +</TABLE> + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> +<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> +<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab4/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>Tue Mar 20 18:13:57 2012</TD></TR> +</TABLE> + + +<br><center><b>Date Generated:</b> 03/21/2012 - 11:25:15</center> +</BODY></HTML>
\ No newline at end of file diff --git a/DisplayController.v b/DisplayController.v new file mode 100644 index 0000000..1ea2bf1 --- /dev/null +++ b/DisplayController.v @@ -0,0 +1,48 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:03:47 03/16/2012 +// Design Name: +// Module Name: DisplayController +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module DisplayController( + input [3:0] A, + input [3:0] B, + input clk_in, + input rst, + output [6:0] result, + output [3:0] AN + ); + +reg [3:0] AN; +reg [6:0] result = 0; + +wire [6:0] ssd1; +wire [6:0] ssd2; + +reg prev = 0; + +SevSegDisp d1(.A(A), .out(ssd1)); +SevSegDisp d2(.A(B), .out(ssd2)); + +always @( posedge clk_in ) begin + prev <= ~prev; + result <= prev ? ssd1 : ssd2; + AN <= { 2'b11, prev, ~prev }; +end + + +endmodule diff --git a/DisplayController_summary.html b/DisplayController_summary.html new file mode 100644 index 0000000..2b4b547 --- /dev/null +++ b/DisplayController_summary.html @@ -0,0 +1,80 @@ +<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> +<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> +<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'> +<TD ALIGN=CENTER COLSPAN='4'><B>DisplayController Project Status</B></TD></TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> +<TD>lab4.xise</TD> +<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> +<TD> No Errors </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> +<TD>DisplayController</TD> +<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> +<TD>New</TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> +<TD>xc6slx16-3csg324</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> +<TD>Balanced</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> +<TD> + </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> +<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> +<TD> </TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> +<TD> </TD> +</TR> +</TABLE> + + + + + + + + + + + + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> +<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> +<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> +<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +</TABLE> + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> +<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> +<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab4/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri Mar 16 16:17:01 2012</TD></TR> +</TABLE> + + +<br><center><b>Date Generated:</b> 03/16/2012 - 17:11:20</center> +</BODY></HTML>
\ No newline at end of file diff --git a/Increment.v b/Increment.v new file mode 100644 index 0000000..b386d13 --- /dev/null +++ b/Increment.v @@ -0,0 +1,32 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:21:53 03/16/2012 +// Design Name: +// Module Name: Increment +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Increment( + input btn, + output [3:0] value + ); + +reg [3:0] value = 0; + +always @ ( posedge btn ) begin + value = value == 9 ? 0 : value + 1; +end + +endmodule diff --git a/SevSegDisp.v b/SevSegDisp.v new file mode 100644 index 0000000..f0b6ee9 --- /dev/null +++ b/SevSegDisp.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:01:14 03/16/2012 +// Design Name: +// Module Name: SevSegDisp +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module SevSegDisp( + input [3:0] A, + output [6:0] out + ); + +reg [6:0] out = 0; + +always @ ( * ) begin + case ( A ) + 4'b0000 : out = 7'b0000001; + 4'b0001 : out = 7'b1001111; + 4'b0010 : out = 7'b0010010; + 4'b0011 : out = 7'b0000110; + 4'b0100 : out = 7'b1001100; + 4'b0101 : out = 7'b0100100; + 4'b0110 : out = 7'b0100000; + 4'b0111 : out = 7'b0001111; + 4'b1000 : out = 7'b0000000; + 4'b1001 : out = 7'b0001100; + default : out = 7'b0011010; + endcase +end + +endmodule diff --git a/SevSegDisp_stx_beh.prj b/SevSegDisp_stx_beh.prj new file mode 100644 index 0000000..6dbd776 --- /dev/null +++ b/SevSegDisp_stx_beh.prj @@ -0,0 +1,2 @@ +verilog isim_temp "SevSegDisp.v" +verilog isim_temp "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/TEST_BCD2Bin.v b/TEST_BCD2Bin.v new file mode 100644 index 0000000..56edd04 --- /dev/null +++ b/TEST_BCD2Bin.v @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:42:39 03/16/2012 +// Design Name: BCD2Bin +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_BCD2Bin.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: BCD2Bin +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_BCD2Bin; + + // Inputs + reg [3:0] hun; + reg [3:0] ten; + reg [3:0] one; + wire [7:0] bin; + + // Instantiate the Unit Under Test (UUT) + BCD2Bin uut ( + .hun(hun), + .ten(ten), + .one(one), + .bin(bin) + ); + + initial begin + // Initialize Inputs + hun = 0; + ten = 0; + one = 0; + + // Wait 100 ns for global reset to finish + #100; + + one = 5; ten = 2; hun = 1; #10; + one = 4; ten = 7; hun = 1; #10; + one = 8; ten = 2; hun = 0; #10; + one = 3; ten = 1; hun = 0; #10; + one = 2; ten = 0; hun = 0; #10; + + // Add stimulus here + + end + +endmodule + diff --git a/TEST_Bin2BCD.v b/TEST_Bin2BCD.v new file mode 100644 index 0000000..e13ee07 --- /dev/null +++ b/TEST_Bin2BCD.v @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 10:35:33 03/16/2012 +// Design Name: Bin2BCD +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_Bin2BCD.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: Bin2BCD +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_Bin2BCD; + + // Inputs + reg [7:0] bin; + + // Outputs + wire [3:0] one; + wire [3:0] ten; + wire [3:0] hun; + + // Instantiate the Unit Under Test (UUT) + Bin2BCD uut ( + .bin(bin), + .one(one), + .ten(ten), + .hun(hun) + ); + + initial begin + // Initialize Inputs + bin = 0; + #10 bin = 3; + #10 bin = 9; + #10 bin = 15; + #10 bin = 124; + #10 bin = 174; + #10 bin = 234; + + // Wait 100 ns for global reset to finish + #100; + + // Add stimulus here + + end + +endmodule + diff --git a/TEST_Bin2BCD_stx_beh.prj b/TEST_Bin2BCD_stx_beh.prj new file mode 100644 index 0000000..e2ff8e3 --- /dev/null +++ b/TEST_Bin2BCD_stx_beh.prj @@ -0,0 +1,3 @@ +verilog isim_temp "Bin2BCD.v" +verilog isim_temp "TEST_Bin2BCD.v" +verilog isim_temp "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/TEST_ClockDivider.v b/TEST_ClockDivider.v new file mode 100644 index 0000000..e7f6cfe --- /dev/null +++ b/TEST_ClockDivider.v @@ -0,0 +1,65 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:29:06 03/16/2012 +// Design Name: ClockDivider +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_ClockDivider.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: ClockDivider +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_ClockDivider; + + // Inputs + reg clk_in; + reg rst; + reg [23:0] count; + + // Outputs + wire clk_out; + + // Instantiate the Unit Under Test (UUT) + ClockDivider uut ( + .clk_in(clk_in), + .rst(rst), + .count(count), + .clk_out(clk_out) + ); + + reg [15:0] i = 0; + + initial begin + // Initialize Inputs + clk_in = 0; + rst = 0; + count = 0; + + // Wait 100 ns for global reset to finish + #50; + + // Add stimulus here + + count = 15; + + for (i = 0; i < 200; i = i + 1) begin + #5; clk_in = ~clk_in; + end + + end + +endmodule + diff --git a/TEST_Countdown.v b/TEST_Countdown.v new file mode 100644 index 0000000..5f47c07 --- /dev/null +++ b/TEST_Countdown.v @@ -0,0 +1,70 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:57:17 03/16/2012 +// Design Name: Countdown +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_Countdown.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: Countdown +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_Countdown; + + // Inputs + reg clk_1hz; + reg rst; + reg start; + reg [7:0] init; + + // Outputs + wire [7:0] t; + + reg [7:0] i=0; + // Instantiate the Unit Under Test (UUT) + Countdown uut ( + .clk_1hz(clk_1hz), + .rst(rst), + .start(start), + .init(init), + .t(t) + ); + + initial begin + // Initialize Inputs + clk_1hz = 0; + rst = 0; + start = 0; + init = 0; + + // Wait 50 ns for global reset to finish + #50; + + // Add stimulus here + + init = 218; #50; + + for (i = 0; i < 255; i = i + 1) begin + #5; clk_1hz = ~clk_1hz; + if (i == 10) begin + start = 1; #5; clk_1hz = ~clk_1hz; start = 0; + end + end + + end + +endmodule + diff --git a/TEST_DisplayController.v b/TEST_DisplayController.v new file mode 100644 index 0000000..74ce40a --- /dev/null +++ b/TEST_DisplayController.v @@ -0,0 +1,71 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:39:11 03/16/2012 +// Design Name: DisplayController +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_DisplayController.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: DisplayController +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_DisplayController; + + // Inputs + reg [3:0] A; + reg [3:0] B; + reg clk_in; + reg rst; + + // Outputs + wire [6:0] result; + wire [3:0] AN; + + // Instantiate the Unit Under Test (UUT) + DisplayController uut ( + .A(A), + .B(B), + .clk_in(clk_in), + .rst(rst), + .result(result), + .AN(AN) + ); + + initial begin + // Initialize Inputs + A = 0; + B = 0; + clk_in = 0; + rst = 0; + + // Wait 100 ns for global reset to finish + #100; + + // Add stimulus here + + A = 4'd7; + B = 4'd9; + + #10; + + while (1) begin + clk_in = ~clk_in; #10; + end + + end + +endmodule + diff --git a/TEST_DisplayController_stx_beh.prj b/TEST_DisplayController_stx_beh.prj new file mode 100644 index 0000000..70a1bcc --- /dev/null +++ b/TEST_DisplayController_stx_beh.prj @@ -0,0 +1,5 @@ +verilog isim_temp "SevSegDisp.v" +verilog isim_temp "ClockDivider.v" +verilog isim_temp "DisplayController.v" +verilog isim_temp "TEST_DisplayController.v" +verilog isim_temp "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/TEST_Increment.v b/TEST_Increment.v new file mode 100644 index 0000000..2ff393a --- /dev/null +++ b/TEST_Increment.v @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:24:49 03/16/2012 +// Design Name: Increment +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_Increment.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: Increment +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_Increment; + + // Inputs + reg btn; + + // Outputs + wire [3 :0] value; + + // count + reg [4:0] i; + + + // Instantiate the Unit Under Test (UUT) + Increment uut ( + .btn(btn), + .value(value) + ); + + initial begin + // Initialize Inputs + btn = 0; + + // Wait 100 ns for global reset to finish + #100; + + for (i = 0; i < 20; i = i + 1) begin + btn = 1; #10; + btn = 0; #10; + end + + #100; + // Add stimulus here + + end + +endmodule + diff --git a/TEST_SevSegDisp.v b/TEST_SevSegDisp.v new file mode 100644 index 0000000..a818547 --- /dev/null +++ b/TEST_SevSegDisp.v @@ -0,0 +1,55 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:48:24 03/16/2012 +// Design Name: SevSegDisp +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_SevSegDisp.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: SevSegDisp +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_SevSegDisp; + + // Inputs + reg [3:0] A; + + // Outputs + wire [6:0] out; + + // Instantiate the Unit Under Test (UUT) + SevSegDisp uut ( + .A(A), + .out(out) + ); + reg [3:0] i = 0; + initial begin + // Initialize Inputs + A = 0; + + // Wait 100 ns for global reset to finish + #100; + + // Add stimulus here + + for (i = 0; i < 10; i = i + 1) begin + A = A + 1; #50; + end + + end + +endmodule + diff --git a/Test_ContdownController.v b/Test_ContdownController.v new file mode 100644 index 0000000..ba3b63c --- /dev/null +++ b/Test_ContdownController.v @@ -0,0 +1,94 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:21:16 03/16/2012 +// Design Name: CountdownController +// Module Name: /home/michael/Documents/School/EC311/lab4/Test_ContdownController.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: CountdownController +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module Test_ContdownController; + + // Inputs + reg btnA; + reg btnB; + reg btnC; + reg clk; + reg rst; + + // Outputs + wire [6:0] ssd; + wire [3:0] AN; + + // Instantiate the Unit Under Test (UUT) + CountdownController uut ( + .btnA(btnA), + .btnB(btnB), + .btnC(btnC), + .clk(clk), + .rst(rst), + .ssd(ssd), + .AN(AN) + ); + + reg [31:0] i = 0; + reg [3:0] j = 0; + initial begin + // Initialize Inputs + btnA = 0; + btnB = 0; + btnC = 0; + clk = 0; + rst = 0; + + // Wait 100 ns for global reset to finish + #100; + + // Add stimulus here + + + + + while (11) begin + clk = ~clk; #1; + if (i < 100) begin + i = i + 1; + if (i == 50) begin + for (j = 0; j < 5; j = j + 1) begin + btnA = 1; #1 + clk = ~clk; + btnA = 0; #1; + clk = ~clk; + end + for (j = 0; j < 2; j = j + 1) begin + btnB = 1; #1; + clk = ~clk; + btnB = 0; #1; + clk = ~clk; + end + end + if (i == 90) begin + btnC = 1; #1; clk = ~clk; btnC = 0; + end + end + end + + end + +endmodule + diff --git a/Test_ContdownController_beh.prj b/Test_ContdownController_beh.prj new file mode 100644 index 0000000..9f8f6b9 --- /dev/null +++ b/Test_ContdownController_beh.prj @@ -0,0 +1,11 @@ +verilog work "SevSegDisp.v" +verilog work "Increment.v" +verilog work "DisplayController.v" +verilog work "debouncer.v" +verilog work "Countdown.v" +verilog work "ClockDivider.v" +verilog work "Bin2BCD.v" +verilog work "BCD2Bin.v" +verilog work "CountdownController.v" +verilog work "Test_ContdownController.v" +verilog work "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..009b8f5 --- /dev/null +++ b/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated --> +<!-- by the Xilinx ISE software. Any direct editing or --> +<!-- changes made to this file may result in unpredictable --> +<!-- behavior or data corruption. It is strongly advised that --> +<!-- users do not edit the contents of this file. --> +<!-- --> +<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> + +<messages> +<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Countdown.v" into library work</arg> +</msg> + +</messages> + diff --git a/clockdiv.wcfg b/clockdiv.wcfg new file mode 100644 index 0000000..ca45f5a --- /dev/null +++ b/clockdiv.wcfg @@ -0,0 +1,36 @@ +<?xml version="1.0" encoding="UTF-8"?> +<wave_config> + <wave_state> + </wave_state> + <db_ref_list> + <db_ref path="/home/michael/Documents/School/EC311/lab4/TEST_ClockDivider_isim_beh1.wdb" id="1" type="auto"> + <top_modules> + <top_module name="TEST_ClockDivider" /> + <top_module name="glbl" /> + </top_modules> + </db_ref> + </db_ref_list> + <WVObjectSize size="5" /> + <wvobject fp_name="/TEST_ClockDivider/clk_out" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">clk_out</obj_property> + <obj_property name="ObjectShortName">clk_out</obj_property> + </wvobject> + <wvobject fp_name="/TEST_ClockDivider/clk_in" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">clk_in</obj_property> + <obj_property name="ObjectShortName">clk_in</obj_property> + </wvobject> + <wvobject fp_name="/TEST_ClockDivider/rst" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">rst</obj_property> + <obj_property name="ObjectShortName">rst</obj_property> + </wvobject> + <wvobject fp_name="/TEST_ClockDivider/count" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">count[23:0]</obj_property> + <obj_property name="ObjectShortName">count[23:0]</obj_property> + <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property> + </wvobject> + <wvobject fp_name="/TEST_ClockDivider/i" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">i[15:0]</obj_property> + <obj_property name="ObjectShortName">i[15:0]</obj_property> + <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property> + </wvobject> +</wave_config> diff --git a/countdown.wcfg b/countdown.wcfg new file mode 100644 index 0000000..9935ede --- /dev/null +++ b/countdown.wcfg @@ -0,0 +1,40 @@ +<?xml version="1.0" encoding="UTF-8"?> +<wave_config> + <wave_state> + </wave_state> + <db_ref_list> + <db_ref path="/home/michael/Documents/School/EC311/lab4/TEST_Countdown_isim_beh.wdb" id="1" type="auto"> + <top_modules> + <top_module name="TEST_Countdown" /> + <top_module name="glbl" /> + </top_modules> + </db_ref> + </db_ref_list> + <WVObjectSize size="6" /> + <wvobject fp_name="/TEST_Countdown/t" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">t[7:0]</obj_property> + <obj_property name="ObjectShortName">t[7:0]</obj_property> + <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property> + </wvobject> + <wvobject fp_name="/TEST_Countdown/clk_1hz" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">clk_1hz</obj_property> + <obj_property name="ObjectShortName">clk_1hz</obj_property> + </wvobject> + <wvobject fp_name="/TEST_Countdown/rst" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">rst</obj_property> + <obj_property name="ObjectShortName">rst</obj_property> + </wvobject> + <wvobject fp_name="/TEST_Countdown/start" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">start</obj_property> + <obj_property name="ObjectShortName">start</obj_property> + </wvobject> + <wvobject fp_name="/TEST_Countdown/init" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">init[7:0]</obj_property> + <obj_property name="ObjectShortName">init[7:0]</obj_property> + </wvobject> + <wvobject fp_name="/TEST_Countdown/i" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">i[7:0]</obj_property> + <obj_property name="ObjectShortName">i[7:0]</obj_property> + <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property> + </wvobject> +</wave_config> diff --git a/debouncer.v b/debouncer.v new file mode 100644 index 0000000..d37cf6d --- /dev/null +++ b/debouncer.v @@ -0,0 +1,56 @@ +module debouncer(clk_1M, rst, din, dout);
+ input clk_1M;
+ input rst;
+ input din;
+ output dout;
+
+ reg dout;
+ reg [21:0] count;
+
+ reg sync0; // first stage of synchronizer
+ reg sync1; // second stage of synchronizer
+
+ reg prev; // register for edge detection
+
+ // synchronize input. (Synchronizers will be discussed in a future lab.)
+ always @(posedge clk_1M or posedge rst) begin
+ if (rst == 1) begin
+ sync0 <= 0;
+ sync1 <= 0;
+ end
+ else begin
+ sync0 <= din;
+ sync1 <= sync0;
+ end
+ end // always
+
+ // perform an edge detect on the synchronized input.
+ always @(posedge clk_1M or posedge rst) begin
+ if (rst == 1) begin
+ prev <= 0;
+ end
+ else begin
+ prev <= sync1;
+ end
+ end // always
+
+ // state machine/counter for timing the debouncing.
+ always @(posedge clk_1M or posedge rst) begin
+ if (rst == 1) begin
+ count <= 0;
+ end
+ else begin
+ if (count == 0) begin
+ if (sync1 == 1 && prev == 0) begin // rising edge detect
+ count <= 22'd100000; // 100,000 us = 100ms delay
+ end
+ dout <= 0;
+ end
+ else begin
+ count <= count - 22'd1;
+ dout <= 1;
+ end
+ end
+ end // always
+
+endmodule
diff --git a/fuse.log b/fuse.log new file mode 100644 index 0000000..d9cd2af --- /dev/null +++ b/fuse.log @@ -0,0 +1,52 @@ +Running: /home/michael/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o /home/michael/Documents/School/EC311/lab4/Test_ContdownController_isim_beh.exe -prj /home/michael/Documents/School/EC311/lab4/Test_ContdownController_beh.prj work.Test_ContdownController work.glbl +ISim O.87xd (signature 0x8ddf5b5d) +Number of CPUs detected in this system: 2 +Turning on mult-threading, number of parallel sub-compilation jobs: 4 +Determining compilation order of HDL files +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/SevSegDisp.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/SevSegDisp.v" Line 27: Redeclaration of ansi port out is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Increment.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/Increment.v" Line 26: Redeclaration of ansi port value is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/DisplayController.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 30: Redeclaration of ansi port AN is not allowed +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 31: Redeclaration of ansi port result is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/debouncer.v" into library work +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Countdown.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/Countdown.v" Line 29: Redeclaration of ansi port t is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/ClockDivider.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/ClockDivider.v" Line 28: Redeclaration of ansi port clk_out is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Bin2BCD.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/Bin2BCD.v" Line 28: Redeclaration of ansi port one is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/BCD2Bin.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/BCD2Bin.v" Line 28: Redeclaration of ansi port bin is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/CountdownController.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 31: Redeclaration of ansi port ssd is not allowed +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 32: Redeclaration of ansi port AN is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Test_ContdownController.v" into library work +Analyzing Verilog file "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" into library work +Starting static elaboration +WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 54: Size mismatch in connection of port <count>. Formal port size is 24-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 55: Size mismatch in connection of port <count>. Formal port size is 24-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 53: Size mismatch in connection of port <count>. Formal port size is 24-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 66: Size mismatch in connection of port <hun>. Formal port size is 4-bit while actual signal size is 32-bit. +Completed static elaboration +Fuse Memory Usage: 95008 KB +Fuse CPU Usage: 1560 ms +Compiling module ClockDivider +Compiling module debouncer +Compiling module Increment +Compiling module BCD2Bin +Compiling module Countdown +Compiling module Bin2BCD +Compiling module SevSegDisp +Compiling module DisplayController +Compiling module CountdownController +Compiling module Test_ContdownController +Compiling module glbl +Time Resolution for simulation is 1ps. +Waiting for 8 sub-compilation(s) to finish... +Compiled 11 Verilog Units +Built simulation executable /home/michael/Documents/School/EC311/lab4/Test_ContdownController_isim_beh.exe +Fuse Memory Usage: 393132 KB +Fuse CPU Usage: 1610 ms +GCC CPU Usage: 1250 ms diff --git a/fuse.xmsgs b/fuse.xmsgs new file mode 100644 index 0000000..39e40a2 --- /dev/null +++ b/fuse.xmsgs @@ -0,0 +1,51 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated + by the Xilinx ISE software. Any direct editing or + changes made to this file may result in unpredictable + behavior or data corruption. It is strongly advised that + users do not edit the contents of this file. --> +<messages> +<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab4/SevSegDisp.v" Line 27: Redeclaration of ansi port <arg fmt="%s" index="1">out</arg> is not allowed +</msg> + +<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab4/Increment.v" Line 26: Redeclaration of ansi port <arg fmt="%s" index="1">value</arg> is not allowed +</msg> + +<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 30: Redeclaration of ansi port <arg fmt="%s" index="1">AN</arg> is not allowed +</msg> + +<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 31: Redeclaration of ansi port <arg fmt="%s" index="1">result</arg> is not allowed +</msg> + +<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab4/Countdown.v" Line 29: Redeclaration of ansi port <arg fmt="%s" index="1">t</arg> is not allowed +</msg> + +<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab4/ClockDivider.v" Line 28: Redeclaration of ansi port <arg fmt="%s" index="1">clk_out</arg> is not allowed +</msg> + +<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab4/Bin2BCD.v" Line 28: Redeclaration of ansi port <arg fmt="%s" index="1">one</arg> is not allowed +</msg> + +<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab4/BCD2Bin.v" Line 28: Redeclaration of ansi port <arg fmt="%s" index="1">bin</arg> is not allowed +</msg> + +<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 31: Redeclaration of ansi port <arg fmt="%s" index="1">ssd</arg> is not allowed +</msg> + +<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 32: Redeclaration of ansi port <arg fmt="%s" index="1">AN</arg> is not allowed +</msg> + +<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 54: Size mismatch in connection of port <<arg fmt="%s" index="3">count</arg>>. Formal port size is <arg fmt="%d" index="2">24</arg>-bit while actual signal size is <arg fmt="%d" index="1">32</arg>-bit. +</msg> + +<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 55: Size mismatch in connection of port <<arg fmt="%s" index="3">count</arg>>. Formal port size is <arg fmt="%d" index="2">24</arg>-bit while actual signal size is <arg fmt="%d" index="1">32</arg>-bit. +</msg> + +<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 53: Size mismatch in connection of port <<arg fmt="%s" index="3">count</arg>>. Formal port size is <arg fmt="%d" index="2">24</arg>-bit while actual signal size is <arg fmt="%d" index="1">32</arg>-bit. +</msg> + +<msg type="warning" file="HDLCompiler" num="189" delta="unknown" >"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 66: Size mismatch in connection of port <<arg fmt="%s" index="3">hun</arg>>. Formal port size is <arg fmt="%d" index="2">4</arg>-bit while actual signal size is <arg fmt="%d" index="1">32</arg>-bit. +</msg> + +</messages> + diff --git a/fuseRelaunch.cmd b/fuseRelaunch.cmd new file mode 100644 index 0000000..2314a76 --- /dev/null +++ b/fuseRelaunch.cmd @@ -0,0 +1 @@ +-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "/home/michael/Documents/School/EC311/lab4/Test_ContdownController_isim_beh.exe" -prj "/home/michael/Documents/School/EC311/lab4/Test_ContdownController_beh.prj" "work.Test_ContdownController" "work.glbl" diff --git a/iseconfig/Bin2BCD.xreport b/iseconfig/Bin2BCD.xreport new file mode 100644 index 0000000..606b2bb --- /dev/null +++ b/iseconfig/Bin2BCD.xreport @@ -0,0 +1,215 @@ +<?xml version='1.0' encoding='UTF-8'?> +<report-views version="2.0" > + <header> + <DateModified>2012-03-16T10:16:13</DateModified> + <ModuleName>Bin2BCD</ModuleName> + <SummaryTimeStamp>Unknown</SummaryTimeStamp> + <SavedFilePath>/home/michael/Documents/School/EC311/lab4/iseconfig/Bin2BCD.xreport</SavedFilePath> + <ImplementationReportsDirectory>/home/michael/Documents/School/EC311/lab4</ImplementationReportsDirectory> + <DateInitialized>2012-03-16T10:16:12</DateInitialized> + <EnableMessageFiltering>false</EnableMessageFiltering> + </header> + <body> + <viewgroup label="Design Overview" > + <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="Bin2BCD_summary.html" label="Summary" > + <toc-item title="Design Overview" target="Design Overview" /> + <toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> + <toc-item title="Performance Summary" target="Performance Summary" /> + <toc-item title="Failing Constraints" target="Failing Constraints" /> + <toc-item title="Detailed Reports" target="Detailed Reports" /> + </view> + <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="Bin2BCD_envsettings.html" label="System Settings" /> + <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="Bin2BCD_map.xrpt" label="IOB Properties" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="Bin2BCD_map.xrpt" label="Control Set Information" /> + <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="Bin2BCD_map.xrpt" label="Module Level Utilization" /> + <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="Bin2BCD.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" /> + <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="Bin2BCD_par.xrpt" label="Pinout Report" /> + <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="Bin2BCD_par.xrpt" label="Clock Report" /> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="Bin2BCD.twx" label="Static Timing" /> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="Bin2BCD_html/fit/report.htm" label="CPLD Fitter Report" /> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="Bin2BCD_html/tim/report.htm" label="CPLD Timing Report" /> + </viewgroup> + <viewgroup label="XPS Errors and Warnings" > + <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> + <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> + <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> + </viewgroup> + <viewgroup label="XPS Reports" > + <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" /> + <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> + <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> + <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="Bin2BCD.log" label="System Log File" /> + </viewgroup> + <viewgroup label="Errors and Warnings" > + <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> + <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" /> + <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" /> + <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" /> + <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" /> + <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" /> + <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" /> + <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" /> + <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" /> + <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" /> + <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" /> + </viewgroup> + <viewgroup label="Detailed Reports" > + <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="Bin2BCD.syr" label="Synthesis Report" > + <toc-item title="Top of Report" target="Copyright " searchDir="Forward" /> + <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> + <toc-item title="HDL Compilation" target=" HDL Compilation " /> + <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> + <toc-item title="HDL Analysis" target=" HDL Analysis " /> + <toc-item title="HDL Parsing" target=" HDL Parsing " /> + <toc-item title="HDL Elaboration" target=" HDL Elaboration " /> + <toc-item title="HDL Synthesis" target=" HDL Synthesis " /> + <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" /> + <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" /> + <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" /> + <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " /> + <toc-item title="Partition Report" target=" Partition Report " /> + <toc-item title="Final Report" target=" Final Report " /> + <toc-item title="Design Summary" target=" Design Summary " /> + <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" /> + <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" /> + <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" /> + <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" /> + <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" /> + <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" /> + <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" /> + <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" /> + <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" /> + </view> + <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="Bin2BCD.srr" label="Synplify Report" /> + <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="Bin2BCD.prec_log" label="Precision Report" /> + <view inputState="Synthesized" program="ngdbuild" type="Report" file="Bin2BCD.bld" label="Translation Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Command Line" target="Command Line:" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> + </view> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="Bin2BCD_map.mrp" label="Map Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> + <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" /> + <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" /> + <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" /> + <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" /> + <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" /> + <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" /> + <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" /> + <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" /> + <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" /> + <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" /> + <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" /> + <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="Bin2BCD.par" label="Place and Route Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Device Utilization" target="Device Utilization Summary:" /> + <toc-item title="Router Information" target="Starting Router" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Clock Report" target="Generating Clock Report" /> + <toc-item title="Timing Results" target="Timing Score:" /> + <toc-item title="Final Summary" target="Peak Memory Usage:" /> + </view> + <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="Bin2BCD.twr" label="Post-PAR Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="Bin2BCD.rpt" label="CPLD Fitter Report (Text)" > + <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" /> + <toc-item title="Resources Summary" target="** Mapped Resource Summary **" /> + <toc-item title="Pin Resources" target="** Pin Resources **" /> + <toc-item title="Global Resources" target="** Global Control Resources **" /> + </view> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="Bin2BCD.tim" label="CPLD Timing Report (Text)" > + <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> + <toc-item title="Performance Summary" target="Performance Summary:" /> + </view> + <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="Bin2BCD.pwr" label="Power Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Power summary" target="Power summary" /> + <toc-item title="Thermal summary" target="Thermal summary" /> + </view> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="Bin2BCD.bgn" label="Bitgen Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> + <toc-item title="Final Summary" target="DRC detected" /> + </view> + </viewgroup> + <viewgroup label="Secondary Reports" > + <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> + <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/Bin2BCD_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/Bin2BCD_translate.nlf" label="Post-Translate Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="Bin2BCD_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="Bin2BCD_map.map" label="Map Log File" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Design Information" target="Design Information" /> + <toc-item title="Design Summary" target="Design Summary" /> + </view> + <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" /> + <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD_preroute.twr" label="Post-Map Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/Bin2BCD_map.nlf" label="Post-Map Simulation Model Report" /> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD_map.psr" label="Physical Synthesis Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="Bin2BCD_pad.txt" label="Pad Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="Bin2BCD.unroutes" label="Unroutes Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD_preroute.tsi" label="Post-Map Constraints Interaction Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD.grf" label="Guide Results Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD.dly" label="Asynchronous Delay Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD.clk_rgn" label="Clock Region Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD.tsi" label="Post-Place and Route Constraints Interaction Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="Bin2BCD_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" /> + <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/Bin2BCD_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="Bin2BCD_sta.nlf" label="Primetime Netlist Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="Bin2BCD.ibs" label="IBIS Model" > + <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" /> + <toc-item title="Component" target="Component " /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD.lck" label="Back-annotate Pin Report" > + <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" /> + <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD.lpc" label="Locked Pin Constraints" > + <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" /> + <toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> + </view> + <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/Bin2BCD_timesim.nlf" label="Post-Fit Simulation Model Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" /> + </viewgroup> + </body> +</report-views> diff --git a/iseconfig/CountdownController.xreport b/iseconfig/CountdownController.xreport new file mode 100644 index 0000000..81912a7 --- /dev/null +++ b/iseconfig/CountdownController.xreport @@ -0,0 +1,215 @@ +<?xml version='1.0' encoding='UTF-8'?> +<report-views version="2.0" > + <header> + <DateModified>2012-03-21T11:25:15</DateModified> + <ModuleName>CountdownController</ModuleName> + <SummaryTimeStamp>Unknown</SummaryTimeStamp> + <SavedFilePath>/home/michael/Documents/School/EC311/lab4/iseconfig/CountdownController.xreport</SavedFilePath> + <ImplementationReportsDirectory>/home/michael/Documents/School/EC311/lab4/</ImplementationReportsDirectory> + <DateInitialized>2012-03-17T11:17:09</DateInitialized> + <EnableMessageFiltering>false</EnableMessageFiltering> + </header> + <body> + <viewgroup label="Design Overview" > + <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="CountdownController_summary.html" label="Summary" > + <toc-item title="Design Overview" target="Design Overview" /> + <toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> + <toc-item title="Performance Summary" target="Performance Summary" /> + <toc-item title="Failing Constraints" target="Failing Constraints" /> + <toc-item title="Detailed Reports" target="Detailed Reports" /> + </view> + <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="CountdownController_envsettings.html" label="System Settings" /> + <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="CountdownController_map.xrpt" label="IOB Properties" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="CountdownController_map.xrpt" label="Control Set Information" /> + <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="CountdownController_map.xrpt" label="Module Level Utilization" /> + <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="CountdownController.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" /> + <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="CountdownController_par.xrpt" label="Pinout Report" /> + <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="CountdownController_par.xrpt" label="Clock Report" /> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="CountdownController.twx" label="Static Timing" /> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="CountdownController_html/fit/report.htm" label="CPLD Fitter Report" /> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="CountdownController_html/tim/report.htm" label="CPLD Timing Report" /> + </viewgroup> + <viewgroup label="XPS Errors and Warnings" > + <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> + <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> + <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> + </viewgroup> + <viewgroup label="XPS Reports" > + <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" /> + <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> + <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> + <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="CountdownController.log" label="System Log File" /> + </viewgroup> + <viewgroup label="Errors and Warnings" > + <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> + <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" /> + <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" /> + <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" /> + <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" /> + <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" /> + <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" /> + <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" /> + <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" /> + <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" /> + <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" /> + </viewgroup> + <viewgroup label="Detailed Reports" > + <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="CountdownController.syr" label="Synthesis Report" > + <toc-item title="Top of Report" target="Copyright " searchDir="Forward" /> + <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> + <toc-item title="HDL Compilation" target=" HDL Compilation " /> + <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> + <toc-item title="HDL Analysis" target=" HDL Analysis " /> + <toc-item title="HDL Parsing" target=" HDL Parsing " /> + <toc-item title="HDL Elaboration" target=" HDL Elaboration " /> + <toc-item title="HDL Synthesis" target=" HDL Synthesis " /> + <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" /> + <toc-item title="Advanced HDL Synthesis" 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<toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="CountdownController.rpt" label="CPLD Fitter Report (Text)" > + <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" /> + <toc-item title="Resources Summary" target="** Mapped Resource Summary **" /> + <toc-item title="Pin Resources" target="** Pin Resources **" /> + <toc-item title="Global Resources" target="** Global Control Resources **" /> + </view> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="CountdownController.tim" label="CPLD Timing Report (Text)" > + <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> + <toc-item title="Performance Summary" target="Performance Summary:" /> + </view> + <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="CountdownController.pwr" label="Power Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Power summary" target="Power summary" /> + <toc-item title="Thermal summary" target="Thermal summary" /> + </view> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="CountdownController.bgn" label="Bitgen Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> + <toc-item title="Final Summary" target="DRC detected" /> + </view> + </viewgroup> + <viewgroup label="Secondary Reports" > + <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> + <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/CountdownController_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/CountdownController_translate.nlf" label="Post-Translate Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="CountdownController_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="CountdownController_map.map" label="Map Log File" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Design Information" target="Design Information" /> + <toc-item title="Design Summary" target="Design Summary" /> + </view> + <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" /> + <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController_preroute.twr" label="Post-Map Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/CountdownController_map.nlf" label="Post-Map Simulation Model Report" /> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController_map.psr" label="Physical Synthesis Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="CountdownController_pad.txt" label="Pad Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="CountdownController.unroutes" label="Unroutes Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController_preroute.tsi" label="Post-Map Constraints Interaction Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.grf" label="Guide Results Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.dly" label="Asynchronous Delay Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.clk_rgn" label="Clock Region Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.tsi" label="Post-Place and Route Constraints Interaction Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="CountdownController_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" /> + <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/CountdownController_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="CountdownController_sta.nlf" label="Primetime Netlist Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="CountdownController.ibs" label="IBIS Model" > + <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" /> + <toc-item title="Component" target="Component " /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.lck" label="Back-annotate Pin Report" > + <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" /> + <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.lpc" label="Locked Pin Constraints" > + <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" /> + <toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> + </view> + <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/CountdownController_timesim.nlf" label="Post-Fit Simulation Model Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" /> + </viewgroup> + </body> +</report-views> diff --git a/iseconfig/lab4.projectmgr b/iseconfig/lab4.projectmgr new file mode 100644 index 0000000..a85babe --- /dev/null +++ b/iseconfig/lab4.projectmgr @@ -0,0 +1,213 @@ +<?xml version='1.0' encoding='utf-8'?> +<!--This is an ISE project configuration file.--> +<!--It holds project specific layout data for the projectmgr plugin.--> +<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.--> +<Project version="2" owner="projectmgr" name="lab4" > + <!--This is an ISE project configuration file.--> + <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + <ClosedNode>/CountdownController |home|michael|Documents|School|EC311|lab4|CountdownController.v/DisplayController - DisplayController</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>cntdwn - Countdown (/home/michael/Documents/School/EC311/lab4/Countdown.v)</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000017a000000020000000000000000000000000200000064ffffffff0000008100000003000000020000017a0000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> + <CurrentItem>cntdwn - Countdown (/home/michael/Documents/School/EC311/lab4/Countdown.v)</CurrentItem> + </ItemView> + <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Design Utilities</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem/> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem/> + </ItemView> + <ItemView guiview="File" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem>debouncer.v</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000287000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004a0000000100000000000000640000000100000000000000790000000100000000000001600000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>debouncer.v</CurrentItem> + </ItemView> + <ItemView guiview="Library" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>work</ClosedNode> + </ClosedNodes> + <SelectedItems/> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000117000000010001000100000000000000000000000064ffffffff000000810000000000000001000001170000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>work</CurrentItem> + </ItemView> + <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Configure Target Device</ClosedNode> + <ClosedNode>Implement Design/Map</ClosedNode> + <ClosedNode>Implement Design/Place & Route/Back-annotate Pin Locations</ClosedNode> + <ClosedNode>Implement Design/Place & Route/Generate IBIS Model</ClosedNode> + <ClosedNode>Implement Design/Place & Route/Generate Post-Place & Route Static Timing</ClosedNode> + <ClosedNode>Implement Design/Translate</ClosedNode> + <ClosedNode>User Constraints</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem></SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem></CurrentItem> + </ItemView> + <ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + <ClosedNode>/CountdownController |home|michael|Documents|School|EC311|lab4|CountdownController.v/DisplayController - DisplayController</ClosedNode> + <ClosedNode>/DisplayController |home|michael|Documents|School|EC311|lab4|DisplayController.v</ClosedNode> + <ClosedNode>/TEST_BCD2Bin |home|michael|Documents|School|EC311|lab4|TEST_BCD2Bin.v</ClosedNode> + <ClosedNode>/TEST_Bin2BCD |home|michael|Documents|School|EC311|lab4|TEST_Bin2BCD.v</ClosedNode> + <ClosedNode>/TEST_ClockDivider |home|michael|Documents|School|EC311|lab4|TEST_ClockDivider.v</ClosedNode> + <ClosedNode>/TEST_Countdown |home|michael|Documents|School|EC311|lab4|TEST_Countdown.v</ClosedNode> + <ClosedNode>/TEST_DisplayController |home|michael|Documents|School|EC311|lab4|TEST_DisplayController.v</ClosedNode> + <ClosedNode>/TEST_DisplayController |home|michael|Documents|School|EC311|lab4|TEST_DisplayController.v/uut - DisplayController</ClosedNode> + <ClosedNode>/TEST_Increment |home|michael|Documents|School|EC311|lab4|TEST_Increment.v</ClosedNode> + <ClosedNode>/TEST_SevSegDisp |home|michael|Documents|School|EC311|lab4|TEST_SevSegDisp.v</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Test_ContdownController (/home/michael/Documents/School/EC311/lab4/Test_ContdownController.v)</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >3</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000018f000000020000000000000000000000000200000064ffffffff0000008100000003000000020000018f0000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> + <CurrentItem>Test_ContdownController (/home/michael/Documents/School/EC311/lab4/Test_ContdownController.v)</CurrentItem> + </ItemView> + <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem/> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem/> + </ItemView> + <ItemView engineview="BehavioralSim" sourcetype="DESUT_VERILOG" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem></SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem></CurrentItem> + </ItemView> + <ItemView engineview="PostTransSim" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + <ClosedNode>/TEST_Bin2BCD |home|michael|Documents|School|EC311|lab4|TEST_Bin2BCD.v</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Unassigned User Library Modules</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000010d0000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Unassigned User Library Modules</CurrentItem> + </ItemView> + <ItemView engineview="PostTransSim" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Compile HDL Simulation Libraries</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Compile HDL Simulation Libraries</CurrentItem> + </ItemView> + <ItemView engineview="PostMapSim" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + <ClosedNode>/TEST_Bin2BCD |home|michael|Documents|School|EC311|lab4|TEST_Bin2BCD.v</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Unassigned User Library Modules</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000010d0000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Unassigned User Library Modules</CurrentItem> + </ItemView> + <ItemView engineview="PostMapSim" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Compile HDL Simulation Libraries</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Compile HDL Simulation Libraries</CurrentItem> + </ItemView> + <ItemView engineview="PostRouteSim" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + <ClosedNode>/TEST_Bin2BCD |home|michael|Documents|School|EC311|lab4|TEST_Bin2BCD.v</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Unassigned User Library Modules</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000010d0000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Unassigned User Library Modules</CurrentItem> + </ItemView> + <ItemView engineview="PostRouteSim" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Compile HDL Simulation Libraries</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Compile HDL Simulation Libraries</CurrentItem> + </ItemView> + <SourceProcessView>000000ff00000000000000020000010a0000009d01000000060100000002</SourceProcessView> + <CurrentView>Behavioral Simulation</CurrentView> +</Project> diff --git a/isim.cmd b/isim.cmd new file mode 100644 index 0000000..12836cc --- /dev/null +++ b/isim.cmd @@ -0,0 +1,3 @@ +onerror {resume} +wave add / +run 1000ns; diff --git a/isim.log b/isim.log new file mode 100644 index 0000000..5c43038 --- /dev/null +++ b/isim.log @@ -0,0 +1,18 @@ +ISim log file +Running: /home/michael/Documents/School/EC311/lab4/Test_ContdownController_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/michael/Documents/School/EC311/lab4/Test_ContdownController_isim_beh.wdb +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +WARNING: For instance uut/dbc/, width 24 of formal port count is not equal to width 32 of actual constant. +WARNING: For instance uut/sec/, width 24 of formal port count is not equal to width 32 of actual constant. +WARNING: For instance uut/dcc/, width 24 of formal port count is not equal to width 32 of actual constant. +WARNING: For instance uut/bcd2b/, width 4 of formal port hun is not equal to width 32 of actual constant. +Time resolution is 1 ps +# onerror resume +# wave add / +# run 1000ns +Simulator is doing circuit initialization process. +Finished circuit initialization process. +# exit 0 diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg b/isim/TEST_Countdown_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg Binary files differnew file mode 100644 index 0000000..909cd06 --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/isimcrash.log b/isim/TEST_Countdown_isim_beh.exe.sim/isimcrash.log new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/isimcrash.log diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/isimkernel.log b/isim/TEST_Countdown_isim_beh.exe.sim/isimkernel.log new file mode 100644 index 0000000..cfb9573 --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/isimkernel.log @@ -0,0 +1,29 @@ +Command line: + TEST_Countdown_isim_beh.exe + -simmode gui + -simrunnum 0 + -socket 46742 + +Wed Mar 21 13:10:41 2012 + + + Elaboration Time: 0.01 sec + + Current Memory Usage: 181.268 Meg + + Total Signals : 18 + Total Nets : 32 + Total Signal Drivers : 10 + Total Blocks : 3 + Total Primitive Blocks : 2 + Total Processes : 16 + Total Traceable Variables : 25 + Total Scalar Nets and Variables : 140 +Total Line Count : 40 + + Total Simulation Time: 0.29 sec + + Current Memory Usage: 256.77 Meg + +Wed Mar 21 13:11:31 2012 + diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/netId.dat b/isim/TEST_Countdown_isim_beh.exe.sim/netId.dat Binary files differnew file mode 100644 index 0000000..20588b3 --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/netId.dat diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/tmp_save/_1 b/isim/TEST_Countdown_isim_beh.exe.sim/tmp_save/_1 Binary files differnew file mode 100644 index 0000000..9bcf6d7 --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/tmp_save/_1 diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/work/TEST_Countdown_isim_beh.exe_main.c b/isim/TEST_Countdown_isim_beh.exe.sim/work/TEST_Countdown_isim_beh.exe_main.c new file mode 100644 index 0000000..e25a621 --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/work/TEST_Countdown_isim_beh.exe_main.c @@ -0,0 +1,36 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +#include "xsi.h" + +struct XSI_INFO xsi_info; + + + +int main(int argc, char **argv) +{ + xsi_init_design(argc, argv); + xsi_register_info(&xsi_info); + + xsi_register_min_prec_unit(-12); + work_m_06453055231304268951_4281377536_init(); + work_m_01236816096418509971_3448823162_init(); + work_m_16541823861846354283_2073120511_init(); + + + xsi_register_tops("work_m_01236816096418509971_3448823162"); + xsi_register_tops("work_m_16541823861846354283_2073120511"); + + + return xsi_run_simulation(argc, argv); + +} diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/work/TEST_Countdown_isim_beh.exe_main.lin64.o b/isim/TEST_Countdown_isim_beh.exe.sim/work/TEST_Countdown_isim_beh.exe_main.lin64.o Binary files differnew file mode 100644 index 0000000..4fde3cb --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/work/TEST_Countdown_isim_beh.exe_main.lin64.o diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/work/m_01236816096418509971_3448823162.c b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_01236816096418509971_3448823162.c new file mode 100644 index 0000000..b813dd5 --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_01236816096418509971_3448823162.c @@ -0,0 +1,329 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab4/TEST_Countdown.v"; +static int ng1[] = {0, 0}; +static int ng2[] = {218, 0}; +static int ng3[] = {255, 0}; +static int ng4[] = {10, 0}; +static int ng5[] = {1, 0}; + + + +static void Initial_46_0(char *t0) +{ + char t6[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t7; + char *t8; + char *t9; + char *t10; + unsigned int t11; + unsigned int t12; + unsigned int t13; + unsigned int t14; + unsigned int t15; + char *t16; + unsigned int t17; + unsigned int t18; + unsigned int t19; + unsigned int t20; + unsigned int t21; + unsigned int t22; + unsigned int t23; + unsigned int t24; + unsigned int t25; + unsigned int t26; + unsigned int t27; + unsigned int t28; + char *t29; + +LAB0: t1 = (t0 + 3000U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(46, ng0); + +LAB4: xsi_set_current_line(48, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1448); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(49, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1608); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(50, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1768); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(51, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 8); + xsi_set_current_line(54, ng0); + t2 = (t0 + 2808); + xsi_process_wait(t2, 50000LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(58, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 8); + xsi_set_current_line(58, ng0); + t2 = (t0 + 2808); + xsi_process_wait(t2, 50000LL); + *((char **)t1) = &&LAB6; + goto LAB1; + +LAB6: xsi_set_current_line(60, ng0); + xsi_set_current_line(60, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 2088); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 8); + +LAB7: t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = ((char*)((ng3))); + memset(t6, 0, 8); + t7 = (t4 + 4); + if (*((unsigned int *)t7) != 0) + goto LAB9; + +LAB8: t8 = (t5 + 4); + if (*((unsigned int *)t8) != 0) + goto LAB9; + +LAB12: if (*((unsigned int *)t4) < *((unsigned int *)t5)) + goto LAB10; + +LAB11: t10 = (t6 + 4); + t11 = *((unsigned int *)t10); + t12 = (~(t11)); + t13 = *((unsigned int *)t6); + t14 = (t13 & t12); + t15 = (t14 != 0); + if (t15 > 0) + goto LAB13; + +LAB14: goto LAB1; + +LAB9: t9 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t9) = 1; + goto LAB11; + +LAB10: *((unsigned int *)t6) = 1; + goto LAB11; + +LAB13: xsi_set_current_line(60, ng0); + +LAB15: xsi_set_current_line(61, ng0); + t16 = (t0 + 2808); + xsi_process_wait(t16, 5000LL); + *((char **)t1) = &&LAB16; + goto LAB1; + +LAB16: xsi_set_current_line(61, ng0); + t2 = (t0 + 1448); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t4 + 4); + t11 = *((unsigned int *)t5); + t12 = (~(t11)); + t13 = *((unsigned int *)t4); + t14 = (t13 & t12); + t15 = (t14 & 1U); + if (t15 != 0) + goto LAB20; + +LAB18: if (*((unsigned int *)t5) == 0) + goto LAB17; + +LAB19: t7 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t7) = 1; + +LAB20: t8 = (t6 + 4); + t9 = (t4 + 4); + t17 = *((unsigned int *)t4); + t18 = (~(t17)); + *((unsigned int *)t6) = t18; + *((unsigned int *)t8) = 0; + if (*((unsigned int *)t9) != 0) + goto LAB22; + +LAB21: t23 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t23 & 1U); + t24 = *((unsigned int *)t8); + *((unsigned int *)t8) = (t24 & 1U); + t10 = (t0 + 1448); + xsi_vlogvar_assign_value(t10, t6, 0, 0, 1); + xsi_set_current_line(62, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = ((char*)((ng4))); + memset(t6, 0, 8); + t7 = (t4 + 4); + t8 = (t5 + 4); + t11 = *((unsigned int *)t4); + t12 = *((unsigned int *)t5); + t13 = (t11 ^ t12); + t14 = *((unsigned int *)t7); + t15 = *((unsigned int *)t8); + t17 = (t14 ^ t15); + t18 = (t13 | t17); + t19 = *((unsigned int *)t7); + t20 = *((unsigned int *)t8); + t21 = (t19 | t20); + t22 = (~(t21)); + t23 = (t18 & t22); + if (t23 != 0) + goto LAB26; + +LAB23: if (t21 != 0) + goto LAB25; + +LAB24: *((unsigned int *)t6) = 1; + +LAB26: t10 = (t6 + 4); + t24 = *((unsigned int *)t10); + t25 = (~(t24)); + t26 = *((unsigned int *)t6); + t27 = (t26 & t25); + t28 = (t27 != 0); + if (t28 > 0) + goto LAB27; + +LAB28: +LAB29: xsi_set_current_line(60, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = ((char*)((ng5))); + memset(t6, 0, 8); + xsi_vlog_unsigned_add(t6, 32, t4, 8, t5, 32); + t7 = (t0 + 2088); + xsi_vlogvar_assign_value(t7, t6, 0, 0, 8); + goto LAB7; + +LAB17: *((unsigned int *)t6) = 1; + goto LAB20; + +LAB22: t19 = *((unsigned int *)t6); + t20 = *((unsigned int *)t9); + *((unsigned int *)t6) = (t19 | t20); + t21 = *((unsigned int *)t8); + t22 = *((unsigned int *)t9); + *((unsigned int *)t8) = (t21 | t22); + goto LAB21; + +LAB25: t9 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t9) = 1; + goto LAB26; + +LAB27: xsi_set_current_line(62, ng0); + +LAB30: xsi_set_current_line(63, ng0); + t16 = ((char*)((ng5))); + t29 = (t0 + 1768); + xsi_vlogvar_assign_value(t29, t16, 0, 0, 1); + xsi_set_current_line(63, ng0); + t2 = (t0 + 2808); + xsi_process_wait(t2, 5000LL); + *((char **)t1) = &&LAB31; + goto LAB1; + +LAB31: xsi_set_current_line(63, ng0); + t2 = (t0 + 1448); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t4 + 4); + t11 = *((unsigned int *)t5); + t12 = (~(t11)); + t13 = *((unsigned int *)t4); + t14 = (t13 & t12); + t15 = (t14 & 1U); + if (t15 != 0) + goto LAB35; + +LAB33: if (*((unsigned int *)t5) == 0) + goto LAB32; + +LAB34: t7 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t7) = 1; + +LAB35: t8 = (t6 + 4); + t9 = (t4 + 4); + t17 = *((unsigned int *)t4); + t18 = (~(t17)); + *((unsigned int *)t6) = t18; + *((unsigned int *)t8) = 0; + if (*((unsigned int *)t9) != 0) + goto LAB37; + +LAB36: t23 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t23 & 1U); + t24 = *((unsigned int *)t8); + *((unsigned int *)t8) = (t24 & 1U); + t10 = (t0 + 1448); + xsi_vlogvar_assign_value(t10, t6, 0, 0, 1); + xsi_set_current_line(63, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1768); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + goto LAB29; + +LAB32: *((unsigned int *)t6) = 1; + goto LAB35; + +LAB37: t19 = *((unsigned int *)t6); + t20 = *((unsigned int *)t9); + *((unsigned int *)t6) = (t19 | t20); + t21 = *((unsigned int *)t8); + t22 = *((unsigned int *)t9); + *((unsigned int *)t8) = (t21 | t22); + goto LAB36; + +} + + +extern void work_m_01236816096418509971_3448823162_init() +{ + static char *pe[] = {(void *)Initial_46_0}; + xsi_register_didat("work_m_01236816096418509971_3448823162", "isim/TEST_Countdown_isim_beh.exe.sim/work/m_01236816096418509971_3448823162.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/work/m_01236816096418509971_3448823162.didat b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_01236816096418509971_3448823162.didat Binary files differnew file mode 100644 index 0000000..beb4669 --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_01236816096418509971_3448823162.didat diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/work/m_01236816096418509971_3448823162.lin64.o b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_01236816096418509971_3448823162.lin64.o Binary files differnew file mode 100644 index 0000000..34389cf --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_01236816096418509971_3448823162.lin64.o diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.c b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.c new file mode 100644 index 0000000..a5af715 --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.c @@ -0,0 +1,279 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab4/Countdown.v"; +static int ng1[] = {1, 0}; +static int ng2[] = {0, 0}; + + + +static void Always_32_0(char *t0) +{ + char t4[8]; + char *t1; + char *t2; + char *t3; + char *t5; + char *t6; + char *t7; + char *t8; + unsigned int t9; + unsigned int t10; + unsigned int t11; + unsigned int t12; + unsigned int t13; + char *t14; + char *t15; + unsigned int t16; + unsigned int t17; + unsigned int t18; + unsigned int t19; + unsigned int t20; + char *t21; + char *t22; + +LAB0: t1 = (t0 + 3000U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(32, ng0); + t2 = (t0 + 4064); + *((int *)t2) = 1; + t3 = (t0 + 3032); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(32, ng0); + +LAB5: xsi_set_current_line(33, ng0); + t5 = (t0 + 2088); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memset(t4, 0, 8); + t8 = (t7 + 4); + t9 = *((unsigned int *)t8); + t10 = (~(t9)); + t11 = *((unsigned int *)t7); + t12 = (t11 & t10); + t13 = (t12 & 1U); + if (t13 != 0) + goto LAB9; + +LAB7: if (*((unsigned int *)t8) == 0) + goto LAB6; + +LAB8: t14 = (t4 + 4); + *((unsigned int *)t4) = 1; + *((unsigned int *)t14) = 1; + +LAB9: t15 = (t4 + 4); + t16 = *((unsigned int *)t15); + t17 = (~(t16)); + t18 = *((unsigned int *)t4); + t19 = (t18 & t17); + t20 = (t19 != 0); + if (t20 > 0) + goto LAB10; + +LAB11: xsi_set_current_line(35, ng0); + +LAB14: xsi_set_current_line(36, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t5 = *((char **)t3); + t6 = (t0 + 1928); + xsi_vlogvar_assign_value(t6, t5, 0, 0, 8); + +LAB12: goto LAB2; + +LAB6: *((unsigned int *)t4) = 1; + goto LAB9; + +LAB10: xsi_set_current_line(33, ng0); + +LAB13: xsi_set_current_line(34, ng0); + t21 = (t0 + 1528U); + t22 = *((char **)t21); + t21 = (t0 + 1928); + xsi_vlogvar_assign_value(t21, t22, 0, 0, 8); + goto LAB12; + +} + +static void Always_40_1(char *t0) +{ + char t17[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + unsigned int t10; + unsigned int t11; + unsigned int t12; + char *t13; + char *t14; + char *t15; + char *t16; + char *t18; + +LAB0: t1 = (t0 + 3248U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(40, ng0); + t2 = (t0 + 4080); + *((int *)t2) = 1; + t3 = (t0 + 3280); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(40, ng0); + +LAB5: xsi_set_current_line(41, ng0); + t4 = (t0 + 2088); + t5 = (t4 + 56U); + t6 = *((char **)t5); + t7 = (t6 + 4); + t8 = *((unsigned int *)t7); + t9 = (~(t8)); + t10 = *((unsigned int *)t6); + t11 = (t10 & t9); + t12 = (t11 != 0); + if (t12 > 0) + goto LAB6; + +LAB7: xsi_set_current_line(43, ng0); + +LAB10: xsi_set_current_line(44, ng0); + t2 = (t0 + 1528U); + t3 = *((char **)t2); + t2 = (t0 + 1928); + xsi_vlogvar_wait_assign_value(t2, t3, 0, 0, 8, 0LL); + +LAB8: goto LAB2; + +LAB6: xsi_set_current_line(41, ng0); + +LAB9: xsi_set_current_line(42, ng0); + t13 = (t0 + 1928); + t14 = (t13 + 56U); + t15 = *((char **)t14); + t16 = ((char*)((ng1))); + memset(t17, 0, 8); + xsi_vlog_unsigned_minus(t17, 32, t15, 8, t16, 32); + t18 = (t0 + 1928); + xsi_vlogvar_wait_assign_value(t18, t17, 0, 0, 8, 0LL); + goto LAB8; + +} + +static void Always_48_2(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + +LAB0: t1 = (t0 + 3496U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(48, ng0); + t2 = (t0 + 4096); + *((int *)t2) = 1; + t3 = (t0 + 3528); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(48, ng0); + +LAB5: xsi_set_current_line(49, ng0); + t4 = ((char*)((ng1))); + t5 = (t0 + 2088); + xsi_vlogvar_assign_value(t5, t4, 0, 0, 1); + goto LAB2; + +} + +static void Always_52_3(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + +LAB0: t1 = (t0 + 3744U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(52, ng0); + t2 = (t0 + 4112); + *((int *)t2) = 1; + t3 = (t0 + 3776); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(52, ng0); + +LAB5: xsi_set_current_line(53, ng0); + t4 = ((char*)((ng2))); + t5 = (t0 + 2088); + xsi_vlogvar_assign_value(t5, t4, 0, 0, 1); + xsi_set_current_line(54, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 8); + goto LAB2; + +} + + +extern void work_m_06453055231304268951_4281377536_init() +{ + static char *pe[] = {(void *)Always_32_0,(void *)Always_40_1,(void *)Always_48_2,(void *)Always_52_3}; + xsi_register_didat("work_m_06453055231304268951_4281377536", "isim/TEST_Countdown_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.didat b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.didat Binary files differnew file mode 100644 index 0000000..94c37ef --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.didat diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.lin64.o b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.lin64.o Binary files differnew file mode 100644 index 0000000..f3118d5 --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.lin64.o diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c new file mode 100644 index 0000000..e4b1ef9 --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c @@ -0,0 +1,337 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/verilog/src/glbl.v"; +static unsigned int ng1[] = {1U, 0U}; +static unsigned int ng2[] = {0U, 0U}; + + + +static void NetDecl_16_0(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + char *t10; + unsigned int t11; + unsigned int t12; + char *t13; + unsigned int t14; + unsigned int t15; + char *t16; + +LAB0: t1 = (t0 + 6952U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(16, ng0); + t2 = (t0 + 1960U); + t3 = *((char **)t2); + t2 = (t0 + 8640); + t4 = (t2 + 56U); + t5 = *((char **)t4); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memset(t7, 0, 8); + t8 = 1U; + t9 = t8; + t10 = (t3 + 4); + t11 = *((unsigned int *)t3); + t8 = (t8 & t11); + t12 = *((unsigned int *)t10); + t9 = (t9 & t12); + t13 = (t7 + 4); + t14 = *((unsigned int *)t7); + *((unsigned int *)t7) = (t14 | t8); + t15 = *((unsigned int *)t13); + *((unsigned int *)t13) = (t15 | t9); + xsi_driver_vfirst_trans(t2, 0, 0U); + t16 = (t0 + 8512); + *((int *)t16) = 1; + +LAB1: return; +} + +static void Cont_48_1(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7200U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(48, ng0); + t2 = (t0 + 3640); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8704); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8528); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Cont_49_2(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7448U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(49, ng0); + t2 = (t0 + 3800); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8768); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8544); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Cont_50_3(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7696U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(50, ng0); + t2 = (t0 + 3960); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8832); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8560); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Initial_52_4(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + +LAB0: t1 = (t0 + 7944U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(52, ng0); + +LAB4: xsi_set_current_line(53, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3640); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(54, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3960); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(55, ng0); + t2 = (t0 + 7752); + xsi_process_wait(t2, 100000LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(56, ng0); + t3 = ((char*)((ng2))); + t4 = (t0 + 3640); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + xsi_set_current_line(57, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 3960); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + goto LAB1; + +} + +static void Initial_60_5(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + +LAB0: t1 = (t0 + 8192U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(60, ng0); + +LAB4: xsi_set_current_line(61, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3800); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(62, ng0); + t2 = (t0 + 8000); + xsi_process_wait(t2, 0LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(63, ng0); + t3 = ((char*)((ng2))); + t4 = (t0 + 3800); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + goto LAB1; + +} + + +extern void work_m_16541823861846354283_2073120511_init() +{ + static char *pe[] = {(void *)NetDecl_16_0,(void *)Cont_48_1,(void *)Cont_49_2,(void *)Cont_50_3,(void *)Initial_52_4,(void *)Initial_60_5}; + xsi_register_didat("work_m_16541823861846354283_2073120511", "isim/TEST_Countdown_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat Binary files differnew file mode 100644 index 0000000..0d3c6aa --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat diff --git a/isim/TEST_Countdown_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o Binary files differnew file mode 100644 index 0000000..2c70287 --- /dev/null +++ b/isim/TEST_Countdown_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg b/isim/Test_ContdownController_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg Binary files differnew file mode 100644 index 0000000..63c0de9 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/isimcrash.log b/isim/Test_ContdownController_isim_beh.exe.sim/isimcrash.log new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/isimcrash.log diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/isimkernel.log b/isim/Test_ContdownController_isim_beh.exe.sim/isimkernel.log new file mode 100644 index 0000000..f0d01ab --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/isimkernel.log @@ -0,0 +1,29 @@ +Command line: + Test_ContdownController_isim_beh.exe + -simmode gui + -simrunnum 0 + -socket 59475 + +Wed Mar 21 13:13:02 2012 + + + Elaboration Time: 0.02 sec + + Current Memory Usage: 181.703 Meg + + Total Signals : 67 + Total Nets : 223 + Total Signal Drivers : 32 + Total Blocks : 16 + Total Primitive Blocks : 13 + Total Processes : 55 + Total Traceable Variables : 60 + Total Scalar Nets and Variables : 592 +Total Line Count : 190 + + Total Simulation Time: 0.07 sec + + Current Memory Usage: 257.204 Meg + +Wed Mar 21 13:14:04 2012 + diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/netId.dat b/isim/Test_ContdownController_isim_beh.exe.sim/netId.dat Binary files differnew file mode 100644 index 0000000..71bf847 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/netId.dat diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/tmp_save/_1 b/isim/Test_ContdownController_isim_beh.exe.sim/tmp_save/_1 Binary files differnew file mode 100644 index 0000000..30c7155 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/tmp_save/_1 diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/Test_ContdownController_isim_beh.exe_main.c b/isim/Test_ContdownController_isim_beh.exe.sim/work/Test_ContdownController_isim_beh.exe_main.c new file mode 100644 index 0000000..c54e658 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/Test_ContdownController_isim_beh.exe_main.c @@ -0,0 +1,44 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +#include "xsi.h" + +struct XSI_INFO xsi_info; + + + +int main(int argc, char **argv) +{ + xsi_init_design(argc, argv); + xsi_register_info(&xsi_info); + + xsi_register_min_prec_unit(-12); + work_m_09461933616065074075_2531671071_init(); + work_m_06185630164696979556_3598138731_init(); + work_m_14878824473863214981_2647877144_init(); + work_m_17579661360444318263_0092613024_init(); + work_m_06453055231304268951_4281377536_init(); + work_m_14079594305330756291_2618506667_init(); + work_m_01832328269938973087_1606112044_init(); + work_m_14181161885881575918_3845763652_init(); + work_m_08578567565259243700_1151371814_init(); + work_m_09637473393135046702_3413554552_init(); + work_m_16541823861846354283_2073120511_init(); + + + xsi_register_tops("work_m_09637473393135046702_3413554552"); + xsi_register_tops("work_m_16541823861846354283_2073120511"); + + + return xsi_run_simulation(argc, argv); + +} diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/Test_ContdownController_isim_beh.exe_main.lin64.o b/isim/Test_ContdownController_isim_beh.exe.sim/work/Test_ContdownController_isim_beh.exe_main.lin64.o Binary files differnew file mode 100644 index 0000000..602f1f5 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/Test_ContdownController_isim_beh.exe_main.lin64.o diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_01832328269938973087_1606112044.c b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_01832328269938973087_1606112044.c new file mode 100644 index 0000000..e594c98 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_01832328269938973087_1606112044.c @@ -0,0 +1,205 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab4/SevSegDisp.v"; +static unsigned int ng1[] = {0U, 0U}; +static unsigned int ng2[] = {1U, 0U}; +static unsigned int ng3[] = {79U, 0U}; +static unsigned int ng4[] = {2U, 0U}; +static unsigned int ng5[] = {18U, 0U}; +static unsigned int ng6[] = {3U, 0U}; +static unsigned int ng7[] = {6U, 0U}; +static unsigned int ng8[] = {4U, 0U}; +static unsigned int ng9[] = {76U, 0U}; +static unsigned int ng10[] = {5U, 0U}; +static unsigned int ng11[] = {36U, 0U}; +static unsigned int ng12[] = {32U, 0U}; +static unsigned int ng13[] = {7U, 0U}; +static unsigned int ng14[] = {15U, 0U}; +static unsigned int ng15[] = {8U, 0U}; +static unsigned int ng16[] = {9U, 0U}; +static unsigned int ng17[] = {12U, 0U}; +static unsigned int ng18[] = {26U, 0U}; + + + +static void Always_29_0(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + int t6; + char *t7; + char *t8; + +LAB0: t1 = (t0 + 2360U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(29, ng0); + t2 = (t0 + 2680); + *((int *)t2) = 1; + t3 = (t0 + 2392); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(29, ng0); + +LAB5: xsi_set_current_line(30, ng0); + t4 = (t0 + 1048U); + t5 = *((char **)t4); + +LAB6: t4 = ((char*)((ng1))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t4, 4); + if (t6 == 1) + goto LAB7; + +LAB8: t2 = ((char*)((ng2))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB9; + +LAB10: t2 = ((char*)((ng4))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB11; + +LAB12: t2 = ((char*)((ng6))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB13; + +LAB14: t2 = ((char*)((ng8))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB15; + +LAB16: t2 = ((char*)((ng10))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB17; + +LAB18: t2 = ((char*)((ng7))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB19; + +LAB20: t2 = ((char*)((ng13))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB21; + +LAB22: t2 = ((char*)((ng15))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB23; + +LAB24: t2 = ((char*)((ng16))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB25; + +LAB26: +LAB28: +LAB27: xsi_set_current_line(41, ng0); + t2 = ((char*)((ng18))); + t3 = (t0 + 1448); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 7); + +LAB29: goto LAB2; + +LAB7: xsi_set_current_line(31, ng0); + t7 = ((char*)((ng2))); + t8 = (t0 + 1448); + xsi_vlogvar_assign_value(t8, t7, 0, 0, 7); + goto LAB29; + +LAB9: xsi_set_current_line(32, ng0); + t3 = ((char*)((ng3))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB11: xsi_set_current_line(33, ng0); + t3 = ((char*)((ng5))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB13: xsi_set_current_line(34, ng0); + t3 = ((char*)((ng7))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB15: xsi_set_current_line(35, ng0); + t3 = ((char*)((ng9))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB17: xsi_set_current_line(36, ng0); + t3 = ((char*)((ng11))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB19: xsi_set_current_line(37, ng0); + t3 = ((char*)((ng12))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB21: xsi_set_current_line(38, ng0); + t3 = ((char*)((ng14))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB23: xsi_set_current_line(39, ng0); + t3 = ((char*)((ng1))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB25: xsi_set_current_line(40, ng0); + t3 = ((char*)((ng17))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +} + + +extern void work_m_01832328269938973087_1606112044_init() +{ + static char *pe[] = {(void *)Always_29_0}; + xsi_register_didat("work_m_01832328269938973087_1606112044", "isim/Test_ContdownController_isim_beh.exe.sim/work/m_01832328269938973087_1606112044.didat"); + xsi_register_executes(pe); +} diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_01832328269938973087_1606112044.didat b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_01832328269938973087_1606112044.didat Binary files differnew file mode 100644 index 0000000..a25c52c --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_01832328269938973087_1606112044.didat diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_01832328269938973087_1606112044.lin64.o b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_01832328269938973087_1606112044.lin64.o Binary files differnew file mode 100644 index 0000000..305d62a --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_01832328269938973087_1606112044.lin64.o diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06185630164696979556_3598138731.c b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06185630164696979556_3598138731.c new file mode 100644 index 0000000..c798e64 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06185630164696979556_3598138731.c @@ -0,0 +1,718 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab4/debouncer.v"; +static int ng1[] = {1, 0}; +static int ng2[] = {0, 0}; +static unsigned int ng3[] = {100000U, 0U}; +static unsigned int ng4[] = {1U, 0U}; + + + +static void Always_16_0(char *t0) +{ + char t6[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t7; + char *t8; + unsigned int t9; + unsigned int t10; + unsigned int t11; + unsigned int t12; + unsigned int t13; + unsigned int t14; + unsigned int t15; + unsigned int t16; + unsigned int t17; + unsigned int t18; + unsigned int t19; + unsigned int t20; + char *t21; + char *t22; + unsigned int t23; + unsigned int t24; + unsigned int t25; + unsigned int t26; + unsigned int t27; + char *t28; + char *t29; + +LAB0: t1 = (t0 + 3320U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(16, ng0); + t2 = (t0 + 4136); + *((int *)t2) = 1; + t3 = (t0 + 3352); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(16, ng0); + +LAB5: xsi_set_current_line(17, ng0); + t4 = (t0 + 1208U); + t5 = *((char **)t4); + t4 = ((char*)((ng1))); + memset(t6, 0, 8); + t7 = (t5 + 4); + t8 = (t4 + 4); + t9 = *((unsigned int *)t5); + t10 = *((unsigned int *)t4); + t11 = (t9 ^ t10); + t12 = *((unsigned int *)t7); + t13 = *((unsigned int *)t8); + t14 = (t12 ^ t13); + t15 = (t11 | t14); + t16 = *((unsigned int *)t7); + t17 = *((unsigned int *)t8); + t18 = (t16 | t17); + t19 = (~(t18)); + t20 = (t15 & t19); + if (t20 != 0) + goto LAB9; + +LAB6: if (t18 != 0) + goto LAB8; + +LAB7: *((unsigned int *)t6) = 1; + +LAB9: t22 = (t6 + 4); + t23 = *((unsigned int *)t22); + t24 = (~(t23)); + t25 = *((unsigned int *)t6); + t26 = (t25 & t24); + t27 = (t26 != 0); + if (t27 > 0) + goto LAB10; + +LAB11: xsi_set_current_line(21, ng0); + +LAB14: xsi_set_current_line(22, ng0); + t2 = (t0 + 1368U); + t3 = *((char **)t2); + t2 = (t0 + 2088); + xsi_vlogvar_wait_assign_value(t2, t3, 0, 0, 1, 0LL); + xsi_set_current_line(23, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 2248); + xsi_vlogvar_wait_assign_value(t5, t4, 0, 0, 1, 0LL); + +LAB12: goto LAB2; + +LAB8: t21 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t21) = 1; + goto LAB9; + +LAB10: xsi_set_current_line(17, ng0); + +LAB13: xsi_set_current_line(18, ng0); + t28 = ((char*)((ng2))); + t29 = (t0 + 2088); + xsi_vlogvar_wait_assign_value(t29, t28, 0, 0, 1, 0LL); + xsi_set_current_line(19, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 2248); + xsi_vlogvar_wait_assign_value(t3, t2, 0, 0, 1, 0LL); + goto LAB12; + +} + +static void Always_28_1(char *t0) +{ + char t6[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t7; + char *t8; + unsigned int t9; + unsigned int t10; + unsigned int t11; + unsigned int t12; + unsigned int t13; + unsigned int t14; + unsigned int t15; + unsigned int t16; + unsigned int t17; + unsigned int t18; + unsigned int t19; + unsigned int t20; + char *t21; + char *t22; + unsigned int t23; + unsigned int t24; + unsigned int t25; + unsigned int t26; + unsigned int t27; + char *t28; + char *t29; + +LAB0: t1 = (t0 + 3568U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(28, ng0); + t2 = (t0 + 4152); + *((int *)t2) = 1; + t3 = (t0 + 3600); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(28, ng0); + +LAB5: xsi_set_current_line(29, ng0); + t4 = (t0 + 1208U); + t5 = *((char **)t4); + t4 = ((char*)((ng1))); + memset(t6, 0, 8); + t7 = (t5 + 4); + t8 = (t4 + 4); + t9 = *((unsigned int *)t5); + t10 = *((unsigned int *)t4); + t11 = (t9 ^ t10); + t12 = *((unsigned int *)t7); + t13 = *((unsigned int *)t8); + t14 = (t12 ^ t13); + t15 = (t11 | t14); + t16 = *((unsigned int *)t7); + t17 = *((unsigned int *)t8); + t18 = (t16 | t17); + t19 = (~(t18)); + t20 = (t15 & t19); + if (t20 != 0) + goto LAB9; + +LAB6: if (t18 != 0) + goto LAB8; + +LAB7: *((unsigned int *)t6) = 1; + +LAB9: t22 = (t6 + 4); + t23 = *((unsigned int *)t22); + t24 = (~(t23)); + t25 = *((unsigned int *)t6); + t26 = (t25 & t24); + t27 = (t26 != 0); + if (t27 > 0) + goto LAB10; + +LAB11: xsi_set_current_line(32, ng0); + +LAB14: xsi_set_current_line(33, ng0); + t2 = (t0 + 2248); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 2408); + xsi_vlogvar_wait_assign_value(t5, t4, 0, 0, 1, 0LL); + +LAB12: goto LAB2; + +LAB8: t21 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t21) = 1; + goto LAB9; + +LAB10: xsi_set_current_line(29, ng0); + +LAB13: xsi_set_current_line(30, ng0); + t28 = ((char*)((ng2))); + t29 = (t0 + 2408); + xsi_vlogvar_wait_assign_value(t29, t28, 0, 0, 1, 0LL); + goto LAB12; + +} + +static void Always_38_2(char *t0) +{ + char t6[8]; + char t32[8]; + char t48[8]; + char t64[8]; + char t80[8]; + char t88[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t7; + char *t8; + unsigned int t9; + unsigned int t10; + unsigned int t11; + unsigned int t12; + unsigned int t13; + unsigned int t14; + unsigned int t15; + unsigned int t16; + unsigned int t17; + unsigned int t18; + unsigned int t19; + unsigned int t20; + char *t21; + char *t22; + unsigned int t23; + unsigned int t24; + unsigned int t25; + unsigned int t26; + unsigned int t27; + char *t28; + char *t29; + char *t30; + char *t31; + char *t33; + char *t34; + unsigned int t35; + unsigned int t36; + unsigned int t37; + unsigned int t38; + unsigned int t39; + unsigned int t40; + unsigned int t41; + unsigned int t42; + unsigned int t43; + unsigned int t44; + unsigned int t45; + unsigned int t46; + char *t47; + char *t49; + unsigned int t50; + unsigned int t51; + unsigned int t52; + unsigned int t53; + unsigned int t54; + char *t55; + char *t56; + unsigned int t57; + unsigned int t58; + unsigned int t59; + char *t60; + char *t61; + char *t62; + char *t63; + char *t65; + char *t66; + unsigned int t67; + unsigned int t68; + unsigned int t69; + unsigned int t70; + unsigned int t71; + unsigned int t72; + unsigned int t73; + unsigned int t74; + unsigned int t75; + unsigned int t76; + unsigned int t77; + unsigned int t78; + char *t79; + char *t81; + unsigned int t82; + unsigned int t83; + unsigned int t84; + unsigned int t85; + unsigned int t86; + char *t87; + unsigned int t89; + unsigned int t90; + unsigned int t91; + char *t92; + char *t93; + char *t94; + unsigned int t95; + unsigned int t96; + unsigned int t97; + unsigned int t98; + unsigned int t99; + unsigned int t100; + unsigned int t101; + char *t102; + char *t103; + unsigned int t104; + unsigned int t105; + unsigned int t106; + unsigned int t107; + unsigned int t108; + unsigned int t109; + unsigned int t110; + unsigned int t111; + int t112; + int t113; + unsigned int t114; + unsigned int t115; + unsigned int t116; + unsigned int t117; + unsigned int t118; + unsigned int t119; + char *t120; + unsigned int t121; + unsigned int t122; + unsigned int t123; + unsigned int t124; + unsigned int t125; + char *t126; + char *t127; + +LAB0: t1 = (t0 + 3816U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(38, ng0); + t2 = (t0 + 4168); + *((int *)t2) = 1; + t3 = (t0 + 3848); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(38, ng0); + +LAB5: xsi_set_current_line(39, ng0); + t4 = (t0 + 1208U); + t5 = *((char **)t4); + t4 = ((char*)((ng1))); + memset(t6, 0, 8); + t7 = (t5 + 4); + t8 = (t4 + 4); + t9 = *((unsigned int *)t5); + t10 = *((unsigned int *)t4); + t11 = (t9 ^ t10); + t12 = *((unsigned int *)t7); + t13 = *((unsigned int *)t8); + t14 = (t12 ^ t13); + t15 = (t11 | t14); + t16 = *((unsigned int *)t7); + t17 = *((unsigned int *)t8); + t18 = (t16 | t17); + t19 = (~(t18)); + t20 = (t15 & t19); + if (t20 != 0) + goto LAB9; + +LAB6: if (t18 != 0) + goto LAB8; + +LAB7: *((unsigned int *)t6) = 1; + +LAB9: t22 = (t6 + 4); + t23 = *((unsigned int *)t22); + t24 = (~(t23)); + t25 = *((unsigned int *)t6); + t26 = (t25 & t24); + t27 = (t26 != 0); + if (t27 > 0) + goto LAB10; + +LAB11: xsi_set_current_line(42, ng0); + +LAB14: xsi_set_current_line(43, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = ((char*)((ng2))); + memset(t6, 0, 8); + t7 = (t4 + 4); + t8 = (t5 + 4); + t9 = *((unsigned int *)t4); + t10 = *((unsigned int *)t5); + t11 = (t9 ^ t10); + t12 = *((unsigned int *)t7); + t13 = *((unsigned int *)t8); + t14 = (t12 ^ t13); + t15 = (t11 | t14); + t16 = *((unsigned int *)t7); + t17 = *((unsigned int *)t8); + t18 = (t16 | t17); + t19 = (~(t18)); + t20 = (t15 & t19); + if (t20 != 0) + goto LAB18; + +LAB15: if (t18 != 0) + goto LAB17; + +LAB16: *((unsigned int *)t6) = 1; + +LAB18: t22 = (t6 + 4); + t23 = *((unsigned int *)t22); + t24 = (~(t23)); + t25 = *((unsigned int *)t6); + t26 = (t25 & t24); + t27 = (t26 != 0); + if (t27 > 0) + goto LAB19; + +LAB20: xsi_set_current_line(49, ng0); + +LAB49: xsi_set_current_line(50, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = ((char*)((ng4))); + memset(t6, 0, 8); + xsi_vlog_unsigned_minus(t6, 22, t4, 22, t5, 22); + t7 = (t0 + 1928); + xsi_vlogvar_wait_assign_value(t7, t6, 0, 0, 22, 0LL); + xsi_set_current_line(51, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1768); + xsi_vlogvar_wait_assign_value(t3, t2, 0, 0, 1, 0LL); + +LAB21: +LAB12: goto LAB2; + +LAB8: t21 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t21) = 1; + goto LAB9; + +LAB10: xsi_set_current_line(39, ng0); + +LAB13: xsi_set_current_line(40, ng0); + t28 = ((char*)((ng2))); + t29 = (t0 + 1928); + xsi_vlogvar_wait_assign_value(t29, t28, 0, 0, 22, 0LL); + goto LAB12; + +LAB17: t21 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t21) = 1; + goto LAB18; + +LAB19: xsi_set_current_line(43, ng0); + +LAB22: xsi_set_current_line(44, ng0); + t28 = (t0 + 2248); + t29 = (t28 + 56U); + t30 = *((char **)t29); + t31 = ((char*)((ng1))); + memset(t32, 0, 8); + t33 = (t30 + 4); + t34 = (t31 + 4); + t35 = *((unsigned int *)t30); + t36 = *((unsigned int *)t31); + t37 = (t35 ^ t36); + t38 = *((unsigned int *)t33); + t39 = *((unsigned int *)t34); + t40 = (t38 ^ t39); + t41 = (t37 | t40); + t42 = *((unsigned int *)t33); + t43 = *((unsigned int *)t34); + t44 = (t42 | t43); + t45 = (~(t44)); + t46 = (t41 & t45); + if (t46 != 0) + goto LAB26; + +LAB23: if (t44 != 0) + goto LAB25; + +LAB24: *((unsigned int *)t32) = 1; + +LAB26: memset(t48, 0, 8); + t49 = (t32 + 4); + t50 = *((unsigned int *)t49); + t51 = (~(t50)); + t52 = *((unsigned int *)t32); + t53 = (t52 & t51); + t54 = (t53 & 1U); + if (t54 != 0) + goto LAB27; + +LAB28: if (*((unsigned int *)t49) != 0) + goto LAB29; + +LAB30: t56 = (t48 + 4); + t57 = *((unsigned int *)t48); + t58 = *((unsigned int *)t56); + t59 = (t57 || t58); + if (t59 > 0) + goto LAB31; + +LAB32: memcpy(t88, t48, 8); + +LAB33: t120 = (t88 + 4); + t121 = *((unsigned int *)t120); + t122 = (~(t121)); + t123 = *((unsigned int *)t88); + t124 = (t123 & t122); + t125 = (t124 != 0); + if (t125 > 0) + goto LAB45; + +LAB46: +LAB47: xsi_set_current_line(47, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 1768); + xsi_vlogvar_wait_assign_value(t3, t2, 0, 0, 1, 0LL); + goto LAB21; + +LAB25: t47 = (t32 + 4); + *((unsigned int *)t32) = 1; + *((unsigned int *)t47) = 1; + goto LAB26; + +LAB27: *((unsigned int *)t48) = 1; + goto LAB30; + +LAB29: t55 = (t48 + 4); + *((unsigned int *)t48) = 1; + *((unsigned int *)t55) = 1; + goto LAB30; + +LAB31: t60 = (t0 + 2408); + t61 = (t60 + 56U); + t62 = *((char **)t61); + t63 = ((char*)((ng2))); + memset(t64, 0, 8); + t65 = (t62 + 4); + t66 = (t63 + 4); + t67 = *((unsigned int *)t62); + t68 = *((unsigned int *)t63); + t69 = (t67 ^ t68); + t70 = *((unsigned int *)t65); + t71 = *((unsigned int *)t66); + t72 = (t70 ^ t71); + t73 = (t69 | t72); + t74 = *((unsigned int *)t65); + t75 = *((unsigned int *)t66); + t76 = (t74 | t75); + t77 = (~(t76)); + t78 = (t73 & t77); + if (t78 != 0) + goto LAB37; + +LAB34: if (t76 != 0) + goto LAB36; + +LAB35: *((unsigned int *)t64) = 1; + +LAB37: memset(t80, 0, 8); + t81 = (t64 + 4); + t82 = *((unsigned int *)t81); + t83 = (~(t82)); + t84 = *((unsigned int *)t64); + t85 = (t84 & t83); + t86 = (t85 & 1U); + if (t86 != 0) + goto LAB38; + +LAB39: if (*((unsigned int *)t81) != 0) + goto LAB40; + +LAB41: t89 = *((unsigned int *)t48); + t90 = *((unsigned int *)t80); + t91 = (t89 & t90); + *((unsigned int *)t88) = t91; + t92 = (t48 + 4); + t93 = (t80 + 4); + t94 = (t88 + 4); + t95 = *((unsigned int *)t92); + t96 = *((unsigned int *)t93); + t97 = (t95 | t96); + *((unsigned int *)t94) = t97; + t98 = *((unsigned int *)t94); + t99 = (t98 != 0); + if (t99 == 1) + goto LAB42; + +LAB43: +LAB44: goto LAB33; + +LAB36: t79 = (t64 + 4); + *((unsigned int *)t64) = 1; + *((unsigned int *)t79) = 1; + goto LAB37; + +LAB38: *((unsigned int *)t80) = 1; + goto LAB41; + +LAB40: t87 = (t80 + 4); + *((unsigned int *)t80) = 1; + *((unsigned int *)t87) = 1; + goto LAB41; + +LAB42: t100 = *((unsigned int *)t88); + t101 = *((unsigned int *)t94); + *((unsigned int *)t88) = (t100 | t101); + t102 = (t48 + 4); + t103 = (t80 + 4); + t104 = *((unsigned int *)t48); + t105 = (~(t104)); + t106 = *((unsigned int *)t102); + t107 = (~(t106)); + t108 = *((unsigned int *)t80); + t109 = (~(t108)); + t110 = *((unsigned int *)t103); + t111 = (~(t110)); + t112 = (t105 & t107); + t113 = (t109 & t111); + t114 = (~(t112)); + t115 = (~(t113)); + t116 = *((unsigned int *)t94); + *((unsigned int *)t94) = (t116 & t114); + t117 = *((unsigned int *)t94); + *((unsigned int *)t94) = (t117 & t115); + t118 = *((unsigned int *)t88); + *((unsigned int *)t88) = (t118 & t114); + t119 = *((unsigned int *)t88); + *((unsigned int *)t88) = (t119 & t115); + goto LAB44; + +LAB45: xsi_set_current_line(44, ng0); + +LAB48: xsi_set_current_line(45, ng0); + t126 = ((char*)((ng3))); + t127 = (t0 + 1928); + xsi_vlogvar_wait_assign_value(t127, t126, 0, 0, 22, 0LL); + goto LAB47; + +} + + +extern void work_m_06185630164696979556_3598138731_init() +{ + static char *pe[] = {(void *)Always_16_0,(void *)Always_28_1,(void *)Always_38_2}; + xsi_register_didat("work_m_06185630164696979556_3598138731", "isim/Test_ContdownController_isim_beh.exe.sim/work/m_06185630164696979556_3598138731.didat"); + xsi_register_executes(pe); +} diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06185630164696979556_3598138731.didat b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06185630164696979556_3598138731.didat Binary files differnew file mode 100644 index 0000000..7883ad1 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06185630164696979556_3598138731.didat diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06185630164696979556_3598138731.lin64.o b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06185630164696979556_3598138731.lin64.o Binary files differnew file mode 100644 index 0000000..9b5da10 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06185630164696979556_3598138731.lin64.o diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.c b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.c new file mode 100644 index 0000000..f615a15 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.c @@ -0,0 +1,279 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab4/Countdown.v"; +static int ng1[] = {1, 0}; +static int ng2[] = {0, 0}; + + + +static void Always_32_0(char *t0) +{ + char t4[8]; + char *t1; + char *t2; + char *t3; + char *t5; + char *t6; + char *t7; + char *t8; + unsigned int t9; + unsigned int t10; + unsigned int t11; + unsigned int t12; + unsigned int t13; + char *t14; + char *t15; + unsigned int t16; + unsigned int t17; + unsigned int t18; + unsigned int t19; + unsigned int t20; + char *t21; + char *t22; + +LAB0: t1 = (t0 + 3000U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(32, ng0); + t2 = (t0 + 4064); + *((int *)t2) = 1; + t3 = (t0 + 3032); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(32, ng0); + +LAB5: xsi_set_current_line(33, ng0); + t5 = (t0 + 2088); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memset(t4, 0, 8); + t8 = (t7 + 4); + t9 = *((unsigned int *)t8); + t10 = (~(t9)); + t11 = *((unsigned int *)t7); + t12 = (t11 & t10); + t13 = (t12 & 1U); + if (t13 != 0) + goto LAB9; + +LAB7: if (*((unsigned int *)t8) == 0) + goto LAB6; + +LAB8: t14 = (t4 + 4); + *((unsigned int *)t4) = 1; + *((unsigned int *)t14) = 1; + +LAB9: t15 = (t4 + 4); + t16 = *((unsigned int *)t15); + t17 = (~(t16)); + t18 = *((unsigned int *)t4); + t19 = (t18 & t17); + t20 = (t19 != 0); + if (t20 > 0) + goto LAB10; + +LAB11: xsi_set_current_line(35, ng0); + +LAB14: xsi_set_current_line(36, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t5 = *((char **)t3); + t6 = (t0 + 1928); + xsi_vlogvar_assign_value(t6, t5, 0, 0, 8); + +LAB12: goto LAB2; + +LAB6: *((unsigned int *)t4) = 1; + goto LAB9; + +LAB10: xsi_set_current_line(33, ng0); + +LAB13: xsi_set_current_line(34, ng0); + t21 = (t0 + 1528U); + t22 = *((char **)t21); + t21 = (t0 + 1928); + xsi_vlogvar_assign_value(t21, t22, 0, 0, 8); + goto LAB12; + +} + +static void Always_40_1(char *t0) +{ + char t17[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + unsigned int t10; + unsigned int t11; + unsigned int t12; + char *t13; + char *t14; + char *t15; + char *t16; + char *t18; + +LAB0: t1 = (t0 + 3248U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(40, ng0); + t2 = (t0 + 4080); + *((int *)t2) = 1; + t3 = (t0 + 3280); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(40, ng0); + +LAB5: xsi_set_current_line(41, ng0); + t4 = (t0 + 2088); + t5 = (t4 + 56U); + t6 = *((char **)t5); + t7 = (t6 + 4); + t8 = *((unsigned int *)t7); + t9 = (~(t8)); + t10 = *((unsigned int *)t6); + t11 = (t10 & t9); + t12 = (t11 != 0); + if (t12 > 0) + goto LAB6; + +LAB7: xsi_set_current_line(43, ng0); + +LAB10: xsi_set_current_line(44, ng0); + t2 = (t0 + 1528U); + t3 = *((char **)t2); + t2 = (t0 + 1928); + xsi_vlogvar_wait_assign_value(t2, t3, 0, 0, 8, 0LL); + +LAB8: goto LAB2; + +LAB6: xsi_set_current_line(41, ng0); + +LAB9: xsi_set_current_line(42, ng0); + t13 = (t0 + 1928); + t14 = (t13 + 56U); + t15 = *((char **)t14); + t16 = ((char*)((ng1))); + memset(t17, 0, 8); + xsi_vlog_unsigned_minus(t17, 32, t15, 8, t16, 32); + t18 = (t0 + 1928); + xsi_vlogvar_wait_assign_value(t18, t17, 0, 0, 8, 0LL); + goto LAB8; + +} + +static void Always_48_2(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + +LAB0: t1 = (t0 + 3496U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(48, ng0); + t2 = (t0 + 4096); + *((int *)t2) = 1; + t3 = (t0 + 3528); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(48, ng0); + +LAB5: xsi_set_current_line(49, ng0); + t4 = ((char*)((ng1))); + t5 = (t0 + 2088); + xsi_vlogvar_assign_value(t5, t4, 0, 0, 1); + goto LAB2; + +} + +static void Always_52_3(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + +LAB0: t1 = (t0 + 3744U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(52, ng0); + t2 = (t0 + 4112); + *((int *)t2) = 1; + t3 = (t0 + 3776); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(52, ng0); + +LAB5: xsi_set_current_line(53, ng0); + t4 = ((char*)((ng2))); + t5 = (t0 + 2088); + xsi_vlogvar_assign_value(t5, t4, 0, 0, 1); + xsi_set_current_line(54, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 8); + goto LAB2; + +} + + +extern void work_m_06453055231304268951_4281377536_init() +{ + static char *pe[] = {(void *)Always_32_0,(void *)Always_40_1,(void *)Always_48_2,(void *)Always_52_3}; + xsi_register_didat("work_m_06453055231304268951_4281377536", "isim/Test_ContdownController_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.didat"); + xsi_register_executes(pe); +} diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.didat b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.didat Binary files differnew file mode 100644 index 0000000..1597deb --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.didat diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.lin64.o b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.lin64.o Binary files differnew file mode 100644 index 0000000..889883c --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.lin64.o diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_08578567565259243700_1151371814.c b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_08578567565259243700_1151371814.c new file mode 100644 index 0000000..e76415d --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_08578567565259243700_1151371814.c @@ -0,0 +1,192 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab4/CountdownController.v"; +static int ng1[] = {100, 0}; +static int ng2[] = {50, 0}; +static int ng3[] = {0, 0}; + + + +static void Always_75_0(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + +LAB0: t1 = (t0 + 6040U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(75, ng0); + t2 = (t0 + 7352); + *((int *)t2) = 1; + t3 = (t0 + 6072); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(75, ng0); + +LAB5: xsi_set_current_line(76, ng0); + t4 = (t0 + 1848U); + t5 = *((char **)t4); + t4 = (t0 + 4968); + xsi_vlogvar_wait_assign_value(t4, t5, 0, 0, 7, 0LL); + xsi_set_current_line(77, ng0); + t2 = (t0 + 2008U); + t3 = *((char **)t2); + t2 = (t0 + 5128); + xsi_vlogvar_wait_assign_value(t2, t3, 0, 0, 4, 0LL); + goto LAB2; + +} + +static void implSig1_execute(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + +LAB0: t1 = (t0 + 6288U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: t2 = ((char*)((ng1))); + t3 = (t0 + 7432); + t4 = (t3 + 56U); + t5 = *((char **)t4); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memcpy(t7, t2, 8); + xsi_driver_vfirst_trans(t3, 0, 31); + +LAB1: return; +} + +static void implSig2_execute(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + +LAB0: t1 = (t0 + 6536U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: t2 = ((char*)((ng1))); + t3 = (t0 + 7496); + t4 = (t3 + 56U); + t5 = *((char **)t4); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memcpy(t7, t2, 8); + xsi_driver_vfirst_trans(t3, 0, 31); + +LAB1: return; +} + +static void implSig3_execute(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + +LAB0: t1 = (t0 + 6784U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: t2 = ((char*)((ng2))); + t3 = (t0 + 7560); + t4 = (t3 + 56U); + t5 = *((char **)t4); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memcpy(t7, t2, 8); + xsi_driver_vfirst_trans(t3, 0, 31); + +LAB1: return; +} + +static void implSig4_execute(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + +LAB0: t1 = (t0 + 7032U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: t2 = ((char*)((ng3))); + t3 = (t0 + 7624); + t4 = (t3 + 56U); + t5 = *((char **)t4); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memcpy(t7, t2, 8); + xsi_driver_vfirst_trans(t3, 0, 31); + +LAB1: return; +} + + +extern void work_m_08578567565259243700_1151371814_init() +{ + static char *pe[] = {(void *)Always_75_0,(void *)implSig1_execute,(void *)implSig2_execute,(void *)implSig3_execute,(void *)implSig4_execute}; + xsi_register_didat("work_m_08578567565259243700_1151371814", "isim/Test_ContdownController_isim_beh.exe.sim/work/m_08578567565259243700_1151371814.didat"); + xsi_register_executes(pe); +} diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_08578567565259243700_1151371814.didat b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_08578567565259243700_1151371814.didat Binary files differnew file mode 100644 index 0000000..c085f25 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_08578567565259243700_1151371814.didat diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_08578567565259243700_1151371814.lin64.o b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_08578567565259243700_1151371814.lin64.o Binary files differnew file mode 100644 index 0000000..6a4750e --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_08578567565259243700_1151371814.lin64.o diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.c b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.c new file mode 100644 index 0000000..65cbf9d --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.c @@ -0,0 +1,273 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab4/ClockDivider.v"; +static int ng1[] = {1, 0}; +static int ng2[] = {0, 0}; + + + +static void Always_31_0(char *t0) +{ + char t6[8]; + char t30[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t7; + char *t8; + unsigned int t9; + unsigned int t10; + unsigned int t11; + unsigned int t12; + unsigned int t13; + unsigned int t14; + unsigned int t15; + unsigned int t16; + unsigned int t17; + unsigned int t18; + unsigned int t19; + unsigned int t20; + char *t21; + char *t22; + unsigned int t23; + unsigned int t24; + unsigned int t25; + unsigned int t26; + unsigned int t27; + char *t28; + char *t29; + char *t31; + char *t32; + unsigned int t33; + unsigned int t34; + unsigned int t35; + unsigned int t36; + unsigned int t37; + char *t38; + char *t39; + char *t40; + unsigned int t41; + unsigned int t42; + unsigned int t43; + unsigned int t44; + unsigned int t45; + unsigned int t46; + unsigned int t47; + unsigned int t48; + char *t49; + +LAB0: t1 = (t0 + 2840U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(31, ng0); + t2 = (t0 + 3160); + *((int *)t2) = 1; + t3 = (t0 + 2872); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(31, ng0); + +LAB5: xsi_set_current_line(32, ng0); + t4 = (t0 + 1208U); + t5 = *((char **)t4); + t4 = ((char*)((ng1))); + memset(t6, 0, 8); + t7 = (t5 + 4); + t8 = (t4 + 4); + t9 = *((unsigned int *)t5); + t10 = *((unsigned int *)t4); + t11 = (t9 ^ t10); + t12 = *((unsigned int *)t7); + t13 = *((unsigned int *)t8); + t14 = (t12 ^ t13); + t15 = (t11 | t14); + t16 = *((unsigned int *)t7); + t17 = *((unsigned int *)t8); + t18 = (t16 | t17); + t19 = (~(t18)); + t20 = (t15 & t19); + if (t20 != 0) + goto LAB9; + +LAB6: if (t18 != 0) + goto LAB8; + +LAB7: *((unsigned int *)t6) = 1; + +LAB9: t22 = (t6 + 4); + t23 = *((unsigned int *)t22); + t24 = (~(t23)); + t25 = *((unsigned int *)t6); + t26 = (t25 & t24); + t27 = (t26 != 0); + if (t27 > 0) + goto LAB10; + +LAB11: xsi_set_current_line(35, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 1368U); + t7 = *((char **)t5); + memset(t6, 0, 8); + t5 = (t4 + 4); + t8 = (t7 + 4); + t9 = *((unsigned int *)t4); + t10 = *((unsigned int *)t7); + t11 = (t9 ^ t10); + t12 = *((unsigned int *)t5); + t13 = *((unsigned int *)t8); + t14 = (t12 ^ t13); + t15 = (t11 | t14); + t16 = *((unsigned int *)t5); + t17 = *((unsigned int *)t8); + t18 = (t16 | t17); + t19 = (~(t18)); + t20 = (t15 & t19); + if (t20 != 0) + goto LAB17; + +LAB14: if (t18 != 0) + goto LAB16; + +LAB15: *((unsigned int *)t6) = 1; + +LAB17: t22 = (t6 + 4); + t23 = *((unsigned int *)t22); + t24 = (~(t23)); + t25 = *((unsigned int *)t6); + t26 = (t25 & t24); + t27 = (t26 != 0); + if (t27 > 0) + goto LAB18; + +LAB19: xsi_set_current_line(38, ng0); + +LAB28: xsi_set_current_line(39, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = ((char*)((ng1))); + memset(t6, 0, 8); + xsi_vlog_unsigned_add(t6, 32, t4, 24, t5, 32); + t7 = (t0 + 1928); + xsi_vlogvar_assign_value(t7, t6, 0, 0, 24); + +LAB20: +LAB12: goto LAB2; + +LAB8: t21 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t21) = 1; + goto LAB9; + +LAB10: xsi_set_current_line(32, ng0); + +LAB13: xsi_set_current_line(33, ng0); + t28 = ((char*)((ng2))); + t29 = (t0 + 1928); + xsi_vlogvar_assign_value(t29, t28, 0, 0, 24); + xsi_set_current_line(34, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 1768); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + goto LAB12; + +LAB16: t21 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t21) = 1; + goto LAB17; + +LAB18: xsi_set_current_line(35, ng0); + +LAB21: xsi_set_current_line(36, ng0); + t28 = (t0 + 1768); + t29 = (t28 + 56U); + t31 = *((char **)t29); + memset(t30, 0, 8); + t32 = (t31 + 4); + t33 = *((unsigned int *)t32); + t34 = (~(t33)); + t35 = *((unsigned int *)t31); + t36 = (t35 & t34); + t37 = (t36 & 1U); + if (t37 != 0) + goto LAB25; + +LAB23: if (*((unsigned int *)t32) == 0) + goto LAB22; + +LAB24: t38 = (t30 + 4); + *((unsigned int *)t30) = 1; + *((unsigned int *)t38) = 1; + +LAB25: t39 = (t30 + 4); + t40 = (t31 + 4); + t41 = *((unsigned int *)t31); + t42 = (~(t41)); + *((unsigned int *)t30) = t42; + *((unsigned int *)t39) = 0; + if (*((unsigned int *)t40) != 0) + goto LAB27; + +LAB26: t47 = *((unsigned int *)t30); + *((unsigned int *)t30) = (t47 & 1U); + t48 = *((unsigned int *)t39); + *((unsigned int *)t39) = (t48 & 1U); + t49 = (t0 + 1768); + xsi_vlogvar_assign_value(t49, t30, 0, 0, 1); + xsi_set_current_line(37, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 24); + goto LAB20; + +LAB22: *((unsigned int *)t30) = 1; + goto LAB25; + +LAB27: t43 = *((unsigned int *)t30); + t44 = *((unsigned int *)t40); + *((unsigned int *)t30) = (t43 | t44); + t45 = *((unsigned int *)t39); + t46 = *((unsigned int *)t40); + *((unsigned int *)t39) = (t45 | t46); + goto LAB26; + +} + + +extern void work_m_09461933616065074075_2531671071_init() +{ + static char *pe[] = {(void *)Always_31_0}; + xsi_register_didat("work_m_09461933616065074075_2531671071", "isim/Test_ContdownController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.didat"); + xsi_register_executes(pe); +} diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.didat b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.didat Binary files differnew file mode 100644 index 0000000..93ffdf8 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.didat diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.lin64.o b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.lin64.o Binary files differnew file mode 100644 index 0000000..34c2d23 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.lin64.o diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09637473393135046702_3413554552.c b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09637473393135046702_3413554552.c new file mode 100644 index 0000000..938dcc2 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09637473393135046702_3413554552.c @@ -0,0 +1,722 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab4/Test_ContdownController.v"; +static int ng1[] = {0, 0}; +static int ng2[] = {11, 0}; +static int ng3[] = {100, 0}; +static int ng4[] = {1, 0}; +static int ng5[] = {50, 0}; +static int ng6[] = {5, 0}; +static int ng7[] = {2, 0}; +static int ng8[] = {90, 0}; + + + +static void Initial_51_0(char *t0) +{ + char t9[8]; + char t33[8]; + char *t1; + char *t2; + char *t3; + unsigned int t4; + unsigned int t5; + unsigned int t6; + unsigned int t7; + unsigned int t8; + char *t10; + char *t11; + char *t12; + char *t13; + unsigned int t14; + unsigned int t15; + unsigned int t16; + unsigned int t17; + unsigned int t18; + char *t19; + char *t20; + char *t21; + unsigned int t22; + unsigned int t23; + unsigned int t24; + unsigned int t25; + unsigned int t26; + unsigned int t27; + unsigned int t28; + unsigned int t29; + char *t30; + char *t31; + char *t32; + char *t34; + +LAB0: t1 = (t0 + 3480U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(51, ng0); + +LAB4: xsi_set_current_line(53, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1608); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(54, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1768); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(55, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(56, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 2088); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(57, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 2248); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(60, ng0); + t2 = (t0 + 3288); + xsi_process_wait(t2, 100000LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(67, ng0); + +LAB6: t2 = ((char*)((ng2))); + t3 = (t2 + 4); + t4 = *((unsigned int *)t3); + t5 = (~(t4)); + t6 = *((unsigned int *)t2); + t7 = (t6 & t5); + t8 = (t7 != 0); + if (t8 > 0) + goto LAB7; + +LAB8: goto LAB1; + +LAB7: xsi_set_current_line(67, ng0); + +LAB9: xsi_set_current_line(68, ng0); + t10 = (t0 + 2088); + t11 = (t10 + 56U); + t12 = *((char **)t11); + memset(t9, 0, 8); + t13 = (t12 + 4); + t14 = *((unsigned int *)t13); + t15 = (~(t14)); + t16 = *((unsigned int *)t12); + t17 = (t16 & t15); + t18 = (t17 & 1U); + if (t18 != 0) + goto LAB13; + +LAB11: if (*((unsigned int *)t13) == 0) + goto LAB10; + +LAB12: t19 = (t9 + 4); + *((unsigned int *)t9) = 1; + *((unsigned int *)t19) = 1; + +LAB13: t20 = (t9 + 4); + t21 = (t12 + 4); + t22 = *((unsigned int *)t12); + t23 = (~(t22)); + *((unsigned int *)t9) = t23; + *((unsigned int *)t20) = 0; + if (*((unsigned int *)t21) != 0) + goto LAB15; + +LAB14: t28 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t28 & 1U); + t29 = *((unsigned int *)t20); + *((unsigned int *)t20) = (t29 & 1U); + t30 = (t0 + 2088); + xsi_vlogvar_assign_value(t30, t9, 0, 0, 1); + xsi_set_current_line(68, ng0); + t2 = (t0 + 3288); + xsi_process_wait(t2, 1000LL); + *((char **)t1) = &&LAB16; + goto LAB1; + +LAB10: *((unsigned int *)t9) = 1; + goto LAB13; + +LAB15: t24 = *((unsigned int *)t9); + t25 = *((unsigned int *)t21); + *((unsigned int *)t9) = (t24 | t25); + t26 = *((unsigned int *)t20); + t27 = *((unsigned int *)t21); + *((unsigned int *)t20) = (t26 | t27); + goto LAB14; + +LAB16: xsi_set_current_line(69, ng0); + t2 = (t0 + 2408); + t3 = (t2 + 56U); + t10 = *((char **)t3); + t11 = ((char*)((ng3))); + memset(t9, 0, 8); + t12 = (t10 + 4); + if (*((unsigned int *)t12) != 0) + goto LAB18; + +LAB17: t13 = (t11 + 4); + if (*((unsigned int *)t13) != 0) + goto LAB18; + +LAB21: if (*((unsigned int *)t10) < *((unsigned int *)t11)) + goto LAB19; + +LAB20: t20 = (t9 + 4); + t4 = *((unsigned int *)t20); + t5 = (~(t4)); + t6 = *((unsigned int *)t9); + t7 = (t6 & t5); + t8 = (t7 != 0); + if (t8 > 0) + goto LAB22; + +LAB23: +LAB24: goto LAB6; + +LAB18: t19 = (t9 + 4); + *((unsigned int *)t9) = 1; + *((unsigned int *)t19) = 1; + goto LAB20; + +LAB19: *((unsigned int *)t9) = 1; + goto LAB20; + +LAB22: xsi_set_current_line(69, ng0); + +LAB25: xsi_set_current_line(70, ng0); + t21 = (t0 + 2408); + t30 = (t21 + 56U); + t31 = *((char **)t30); + t32 = ((char*)((ng4))); + memset(t33, 0, 8); + xsi_vlog_unsigned_add(t33, 32, t31, 32, t32, 32); + t34 = (t0 + 2408); + xsi_vlogvar_assign_value(t34, t33, 0, 0, 32); + xsi_set_current_line(71, ng0); + t2 = (t0 + 2408); + t3 = (t2 + 56U); + t10 = *((char **)t3); + t11 = ((char*)((ng5))); + memset(t9, 0, 8); + t12 = (t10 + 4); + t13 = (t11 + 4); + t4 = *((unsigned int *)t10); + t5 = *((unsigned int *)t11); + t6 = (t4 ^ t5); + t7 = *((unsigned int *)t12); + t8 = *((unsigned int *)t13); + t14 = (t7 ^ t8); + t15 = (t6 | t14); + t16 = *((unsigned int *)t12); + t17 = *((unsigned int *)t13); + t18 = (t16 | t17); + t22 = (~(t18)); + t23 = (t15 & t22); + if (t23 != 0) + goto LAB29; + +LAB26: if (t18 != 0) + goto LAB28; + +LAB27: *((unsigned int *)t9) = 1; + +LAB29: t20 = (t9 + 4); + t24 = *((unsigned int *)t20); + t25 = (~(t24)); + t26 = *((unsigned int *)t9); + t27 = (t26 & t25); + t28 = (t27 != 0); + if (t28 > 0) + goto LAB30; + +LAB31: +LAB32: xsi_set_current_line(85, ng0); + t2 = (t0 + 2408); + t3 = (t2 + 56U); + t10 = *((char **)t3); + t11 = ((char*)((ng8))); + memset(t9, 0, 8); + t12 = (t10 + 4); + t13 = (t11 + 4); + t4 = *((unsigned int *)t10); + t5 = *((unsigned int *)t11); + t6 = (t4 ^ t5); + t7 = *((unsigned int *)t12); + t8 = *((unsigned int *)t13); + t14 = (t7 ^ t8); + t15 = (t6 | t14); + t16 = *((unsigned int *)t12); + t17 = *((unsigned int *)t13); + t18 = (t16 | t17); + t22 = (~(t18)); + t23 = (t15 & t22); + if (t23 != 0) + goto LAB83; + +LAB80: if (t18 != 0) + goto LAB82; + +LAB81: *((unsigned int *)t9) = 1; + +LAB83: t20 = (t9 + 4); + t24 = *((unsigned int *)t20); + t25 = (~(t24)); + t26 = *((unsigned int *)t9); + t27 = (t26 & t25); + t28 = (t27 != 0); + if (t28 > 0) + goto LAB84; + +LAB85: +LAB86: goto LAB24; + +LAB28: t19 = (t9 + 4); + *((unsigned int *)t9) = 1; + *((unsigned int *)t19) = 1; + goto LAB29; + +LAB30: xsi_set_current_line(71, ng0); + +LAB33: xsi_set_current_line(72, ng0); + xsi_set_current_line(72, ng0); + t21 = ((char*)((ng1))); + t30 = (t0 + 2568); + xsi_vlogvar_assign_value(t30, t21, 0, 0, 4); + +LAB34: t2 = (t0 + 2568); + t3 = (t2 + 56U); + t10 = *((char **)t3); + t11 = ((char*)((ng6))); + memset(t9, 0, 8); + t12 = (t10 + 4); + if (*((unsigned int *)t12) != 0) + goto LAB36; + +LAB35: t13 = (t11 + 4); + if (*((unsigned int *)t13) != 0) + goto LAB36; + +LAB39: if (*((unsigned int *)t10) < *((unsigned int *)t11)) + goto LAB37; + +LAB38: t20 = (t9 + 4); + t4 = *((unsigned int *)t20); + t5 = (~(t4)); + t6 = *((unsigned int *)t9); + t7 = (t6 & t5); + t8 = (t7 != 0); + if (t8 > 0) + goto LAB40; + +LAB41: xsi_set_current_line(78, ng0); + xsi_set_current_line(78, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 2568); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 4); + +LAB57: t2 = (t0 + 2568); + t3 = (t2 + 56U); + t10 = *((char **)t3); + t11 = ((char*)((ng7))); + memset(t9, 0, 8); + t12 = (t10 + 4); + if (*((unsigned int *)t12) != 0) + goto LAB59; + +LAB58: t13 = (t11 + 4); + if (*((unsigned int *)t13) != 0) + goto LAB59; + +LAB62: if (*((unsigned int *)t10) < *((unsigned int *)t11)) + goto LAB60; + +LAB61: t20 = (t9 + 4); + t4 = *((unsigned int *)t20); + t5 = (~(t4)); + t6 = *((unsigned int *)t9); + t7 = (t6 & t5); + t8 = (t7 != 0); + if (t8 > 0) + goto LAB63; + +LAB64: goto LAB32; + +LAB36: t19 = (t9 + 4); + *((unsigned int *)t9) = 1; + *((unsigned int *)t19) = 1; + goto LAB38; + +LAB37: *((unsigned int *)t9) = 1; + goto LAB38; + +LAB40: xsi_set_current_line(72, ng0); + +LAB42: xsi_set_current_line(73, ng0); + t21 = ((char*)((ng4))); + t30 = (t0 + 1608); + xsi_vlogvar_assign_value(t30, t21, 0, 0, 1); + xsi_set_current_line(73, ng0); + t2 = (t0 + 3288); + xsi_process_wait(t2, 1000LL); + *((char **)t1) = &&LAB43; + goto LAB1; + +LAB43: xsi_set_current_line(74, ng0); + t3 = (t0 + 2088); + t10 = (t3 + 56U); + t11 = *((char **)t10); + memset(t9, 0, 8); + t12 = (t11 + 4); + t4 = *((unsigned int *)t12); + t5 = (~(t4)); + t6 = *((unsigned int *)t11); + t7 = (t6 & t5); + t8 = (t7 & 1U); + if (t8 != 0) + goto LAB47; + +LAB45: if (*((unsigned int *)t12) == 0) + goto LAB44; + +LAB46: t13 = (t9 + 4); + *((unsigned int *)t9) = 1; + *((unsigned int *)t13) = 1; + +LAB47: t19 = (t9 + 4); + t20 = (t11 + 4); + t14 = *((unsigned int *)t11); + t15 = (~(t14)); + *((unsigned int *)t9) = t15; + *((unsigned int *)t19) = 0; + if (*((unsigned int *)t20) != 0) + goto LAB49; + +LAB48: t23 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t23 & 1U); + t24 = *((unsigned int *)t19); + *((unsigned int *)t19) = (t24 & 1U); + t21 = (t0 + 2088); + xsi_vlogvar_assign_value(t21, t9, 0, 0, 1); + xsi_set_current_line(75, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1608); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(75, ng0); + t2 = (t0 + 3288); + xsi_process_wait(t2, 1000LL); + *((char **)t1) = &&LAB50; + goto LAB1; + +LAB44: *((unsigned int *)t9) = 1; + goto LAB47; + +LAB49: t16 = *((unsigned int *)t9); + t17 = *((unsigned int *)t20); + *((unsigned int *)t9) = (t16 | t17); + t18 = *((unsigned int *)t19); + t22 = *((unsigned int *)t20); + *((unsigned int *)t19) = (t18 | t22); + goto LAB48; + +LAB50: xsi_set_current_line(76, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t10 = *((char **)t3); + memset(t9, 0, 8); + t11 = (t10 + 4); + t4 = *((unsigned int *)t11); + t5 = (~(t4)); + t6 = *((unsigned int *)t10); + t7 = (t6 & t5); + t8 = (t7 & 1U); + if (t8 != 0) + goto LAB54; + +LAB52: if (*((unsigned int *)t11) == 0) + goto LAB51; + +LAB53: t12 = (t9 + 4); + *((unsigned int *)t9) = 1; + *((unsigned int *)t12) = 1; + +LAB54: t13 = (t9 + 4); + t19 = (t10 + 4); + t14 = *((unsigned int *)t10); + t15 = (~(t14)); + *((unsigned int *)t9) = t15; + *((unsigned int *)t13) = 0; + if (*((unsigned int *)t19) != 0) + goto LAB56; + +LAB55: t23 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t23 & 1U); + t24 = *((unsigned int *)t13); + *((unsigned int *)t13) = (t24 & 1U); + t20 = (t0 + 2088); + xsi_vlogvar_assign_value(t20, t9, 0, 0, 1); + xsi_set_current_line(72, ng0); + t2 = (t0 + 2568); + t3 = (t2 + 56U); + t10 = *((char **)t3); + t11 = ((char*)((ng4))); + memset(t9, 0, 8); + xsi_vlog_unsigned_add(t9, 32, t10, 4, t11, 32); + t12 = (t0 + 2568); + xsi_vlogvar_assign_value(t12, t9, 0, 0, 4); + goto LAB34; + +LAB51: *((unsigned int *)t9) = 1; + goto LAB54; + +LAB56: t16 = *((unsigned int *)t9); + t17 = *((unsigned int *)t19); + *((unsigned int *)t9) = (t16 | t17); + t18 = *((unsigned int *)t13); + t22 = *((unsigned int *)t19); + *((unsigned int *)t13) = (t18 | t22); + goto LAB55; + +LAB59: t19 = (t9 + 4); + *((unsigned int *)t9) = 1; + *((unsigned int *)t19) = 1; + goto LAB61; + +LAB60: *((unsigned int *)t9) = 1; + goto LAB61; + +LAB63: xsi_set_current_line(78, ng0); + +LAB65: xsi_set_current_line(79, ng0); + t21 = ((char*)((ng4))); + t30 = (t0 + 1768); + xsi_vlogvar_assign_value(t30, t21, 0, 0, 1); + xsi_set_current_line(79, ng0); + t2 = (t0 + 3288); + xsi_process_wait(t2, 1000LL); + *((char **)t1) = &&LAB66; + goto LAB1; + +LAB66: xsi_set_current_line(80, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t10 = *((char **)t3); + memset(t9, 0, 8); + t11 = (t10 + 4); + t4 = *((unsigned int *)t11); + t5 = (~(t4)); + t6 = *((unsigned int *)t10); + t7 = (t6 & t5); + t8 = (t7 & 1U); + if (t8 != 0) + goto LAB70; + +LAB68: if (*((unsigned int *)t11) == 0) + goto LAB67; + +LAB69: t12 = (t9 + 4); + *((unsigned int *)t9) = 1; + *((unsigned int *)t12) = 1; + +LAB70: t13 = (t9 + 4); + t19 = (t10 + 4); + t14 = *((unsigned int *)t10); + t15 = (~(t14)); + *((unsigned int *)t9) = t15; + *((unsigned int *)t13) = 0; + if (*((unsigned int *)t19) != 0) + goto LAB72; + +LAB71: t23 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t23 & 1U); + t24 = *((unsigned int *)t13); + *((unsigned int *)t13) = (t24 & 1U); + t20 = (t0 + 2088); + xsi_vlogvar_assign_value(t20, t9, 0, 0, 1); + xsi_set_current_line(81, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1768); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(81, ng0); + t2 = (t0 + 3288); + xsi_process_wait(t2, 1000LL); + *((char **)t1) = &&LAB73; + goto LAB1; + +LAB67: *((unsigned int *)t9) = 1; + goto LAB70; + +LAB72: t16 = *((unsigned int *)t9); + t17 = *((unsigned int *)t19); + *((unsigned int *)t9) = (t16 | t17); + t18 = *((unsigned int *)t13); + t22 = *((unsigned int *)t19); + *((unsigned int *)t13) = (t18 | t22); + goto LAB71; + +LAB73: xsi_set_current_line(82, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t10 = *((char **)t3); + memset(t9, 0, 8); + t11 = (t10 + 4); + t4 = *((unsigned int *)t11); + t5 = (~(t4)); + t6 = *((unsigned int *)t10); + t7 = (t6 & t5); + t8 = (t7 & 1U); + if (t8 != 0) + goto LAB77; + +LAB75: if (*((unsigned int *)t11) == 0) + goto LAB74; + +LAB76: t12 = (t9 + 4); + *((unsigned int *)t9) = 1; + *((unsigned int *)t12) = 1; + +LAB77: t13 = (t9 + 4); + t19 = (t10 + 4); + t14 = *((unsigned int *)t10); + t15 = (~(t14)); + *((unsigned int *)t9) = t15; + *((unsigned int *)t13) = 0; + if (*((unsigned int *)t19) != 0) + goto LAB79; + +LAB78: t23 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t23 & 1U); + t24 = *((unsigned int *)t13); + *((unsigned int *)t13) = (t24 & 1U); + t20 = (t0 + 2088); + xsi_vlogvar_assign_value(t20, t9, 0, 0, 1); + xsi_set_current_line(78, ng0); + t2 = (t0 + 2568); + t3 = (t2 + 56U); + t10 = *((char **)t3); + t11 = ((char*)((ng4))); + memset(t9, 0, 8); + xsi_vlog_unsigned_add(t9, 32, t10, 4, t11, 32); + t12 = (t0 + 2568); + xsi_vlogvar_assign_value(t12, t9, 0, 0, 4); + goto LAB57; + +LAB74: *((unsigned int *)t9) = 1; + goto LAB77; + +LAB79: t16 = *((unsigned int *)t9); + t17 = *((unsigned int *)t19); + *((unsigned int *)t9) = (t16 | t17); + t18 = *((unsigned int *)t13); + t22 = *((unsigned int *)t19); + *((unsigned int *)t13) = (t18 | t22); + goto LAB78; + +LAB82: t19 = (t9 + 4); + *((unsigned int *)t9) = 1; + *((unsigned int *)t19) = 1; + goto LAB83; + +LAB84: xsi_set_current_line(85, ng0); + +LAB87: xsi_set_current_line(86, ng0); + t21 = ((char*)((ng4))); + t30 = (t0 + 1928); + xsi_vlogvar_assign_value(t30, t21, 0, 0, 1); + xsi_set_current_line(86, ng0); + t2 = (t0 + 3288); + xsi_process_wait(t2, 1000LL); + *((char **)t1) = &&LAB88; + goto LAB1; + +LAB88: xsi_set_current_line(86, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t10 = *((char **)t3); + memset(t9, 0, 8); + t11 = (t10 + 4); + t4 = *((unsigned int *)t11); + t5 = (~(t4)); + t6 = *((unsigned int *)t10); + t7 = (t6 & t5); + t8 = (t7 & 1U); + if (t8 != 0) + goto LAB92; + +LAB90: if (*((unsigned int *)t11) == 0) + goto LAB89; + +LAB91: t12 = (t9 + 4); + *((unsigned int *)t9) = 1; + *((unsigned int *)t12) = 1; + +LAB92: t13 = (t9 + 4); + t19 = (t10 + 4); + t14 = *((unsigned int *)t10); + t15 = (~(t14)); + *((unsigned int *)t9) = t15; + *((unsigned int *)t13) = 0; + if (*((unsigned int *)t19) != 0) + goto LAB94; + +LAB93: t23 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t23 & 1U); + t24 = *((unsigned int *)t13); + *((unsigned int *)t13) = (t24 & 1U); + t20 = (t0 + 2088); + xsi_vlogvar_assign_value(t20, t9, 0, 0, 1); + xsi_set_current_line(86, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + goto LAB86; + +LAB89: *((unsigned int *)t9) = 1; + goto LAB92; + +LAB94: t16 = *((unsigned int *)t9); + t17 = *((unsigned int *)t19); + *((unsigned int *)t9) = (t16 | t17); + t18 = *((unsigned int *)t13); + t22 = *((unsigned int *)t19); + *((unsigned int *)t13) = (t18 | t22); + goto LAB93; + +} + + +extern void work_m_09637473393135046702_3413554552_init() +{ + static char *pe[] = {(void *)Initial_51_0}; + xsi_register_didat("work_m_09637473393135046702_3413554552", "isim/Test_ContdownController_isim_beh.exe.sim/work/m_09637473393135046702_3413554552.didat"); + xsi_register_executes(pe); +} diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09637473393135046702_3413554552.didat b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09637473393135046702_3413554552.didat Binary files differnew file mode 100644 index 0000000..9824e28 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09637473393135046702_3413554552.didat diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09637473393135046702_3413554552.lin64.o b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09637473393135046702_3413554552.lin64.o Binary files differnew file mode 100644 index 0000000..be3d391 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_09637473393135046702_3413554552.lin64.o diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14079594305330756291_2618506667.c b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14079594305330756291_2618506667.c new file mode 100644 index 0000000..67e2282 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14079594305330756291_2618506667.c @@ -0,0 +1,590 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab4/Bin2BCD.v"; +static int ng1[] = {0, 0}; +static int ng2[] = {7, 0}; +static int ng3[] = {1, 0}; +static int ng4[] = {5, 0}; +static int ng5[] = {3, 0}; +static int ng6[] = {19, 0}; +static int ng7[] = {16, 0}; +static int ng8[] = {15, 0}; +static int ng9[] = {12, 0}; +static int ng10[] = {11, 0}; +static int ng11[] = {8, 0}; + + + +static void Always_32_0(char *t0) +{ + char t6[8]; + char t20[8]; + char t28[8]; + char t38[8]; + char t40[8]; + char t41[8]; + char t42[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t7; + char *t8; + char *t9; + char *t10; + char *t11; + char *t12; + char *t13; + unsigned int t14; + unsigned int t15; + unsigned int t16; + unsigned int t17; + unsigned int t18; + char *t19; + char *t21; + unsigned int t22; + unsigned int t23; + unsigned int t24; + unsigned int t25; + unsigned int t26; + unsigned int t27; + char *t29; + char *t30; + unsigned int t31; + unsigned int t32; + unsigned int t33; + unsigned int t34; + unsigned int t35; + unsigned int t36; + char *t37; + char *t39; + char *t43; + char *t44; + char *t45; + char *t46; + char *t47; + char *t48; + unsigned int t49; + int t50; + char *t51; + unsigned int t52; + int t53; + int t54; + char *t55; + unsigned int t56; + int t57; + int t58; + unsigned int t59; + int t60; + unsigned int t61; + unsigned int t62; + int t63; + int t64; + +LAB0: t1 = (t0 + 3000U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(32, ng0); + t2 = (t0 + 3320); + *((int *)t2) = 1; + t3 = (t0 + 3032); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(32, ng0); + +LAB5: xsi_set_current_line(33, ng0); + t4 = ((char*)((ng1))); + t5 = (t0 + 1768); + xsi_vlogvar_assign_value(t5, t4, 0, 0, 4); + xsi_set_current_line(33, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1608); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 4); + xsi_set_current_line(33, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1448); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 4); + xsi_set_current_line(34, ng0); + t2 = (t0 + 1048U); + t3 = *((char **)t2); + t2 = (t0 + 1448); + t4 = (t2 + 56U); + t5 = *((char **)t4); + t7 = (t0 + 1608); + t8 = (t7 + 56U); + t9 = *((char **)t8); + t10 = (t0 + 1768); + t11 = (t10 + 56U); + t12 = *((char **)t11); + xsi_vlogtype_concat(t6, 20, 20, 4U, t12, 4, t9, 4, t5, 4, t3, 8); + t13 = (t0 + 1928); + xsi_vlogvar_assign_value(t13, t6, 0, 0, 20); + xsi_set_current_line(36, ng0); + xsi_set_current_line(36, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 2088); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 4); + +LAB6: t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = ((char*)((ng2))); + memset(t6, 0, 8); + t7 = (t4 + 4); + if (*((unsigned int *)t7) != 0) + goto LAB8; + +LAB7: t8 = (t5 + 4); + if (*((unsigned int *)t8) != 0) + goto LAB8; + +LAB11: if (*((unsigned int *)t4) < *((unsigned int *)t5)) + goto LAB9; + +LAB10: t10 = (t6 + 4); + t14 = *((unsigned int *)t10); + t15 = (~(t14)); + t16 = *((unsigned int *)t6); + t17 = (t16 & t15); + t18 = (t17 != 0); + if (t18 > 0) + goto LAB12; + +LAB13: xsi_set_current_line(49, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = ((char*)((ng3))); + memset(t6, 0, 8); + xsi_vlog_unsigned_lshift(t6, 20, t4, 20, t5, 32); + t7 = (t0 + 1928); + xsi_vlogvar_assign_value(t7, t6, 0, 0, 20); + xsi_set_current_line(51, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t6 + 4); + t7 = (t4 + 4); + t14 = *((unsigned int *)t4); + t15 = (t14 >> 16); + *((unsigned int *)t6) = t15; + t16 = *((unsigned int *)t7); + t17 = (t16 >> 16); + *((unsigned int *)t5) = t17; + t18 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t18 & 15U); + t22 = *((unsigned int *)t5); + *((unsigned int *)t5) = (t22 & 15U); + t8 = (t0 + 1768); + xsi_vlogvar_assign_value(t8, t6, 0, 0, 4); + xsi_set_current_line(52, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t6 + 4); + t7 = (t4 + 4); + t14 = *((unsigned int *)t4); + t15 = (t14 >> 12); + *((unsigned int *)t6) = t15; + t16 = *((unsigned int *)t7); + t17 = (t16 >> 12); + *((unsigned int *)t5) = t17; + t18 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t18 & 15U); + t22 = *((unsigned int *)t5); + *((unsigned int *)t5) = (t22 & 15U); + t8 = (t0 + 1608); + xsi_vlogvar_assign_value(t8, t6, 0, 0, 4); + xsi_set_current_line(53, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t6 + 4); + t7 = (t4 + 4); + t14 = *((unsigned int *)t4); + t15 = (t14 >> 8); + *((unsigned int *)t6) = t15; + t16 = *((unsigned int *)t7); + t17 = (t16 >> 8); + *((unsigned int *)t5) = t17; + t18 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t18 & 15U); + t22 = *((unsigned int *)t5); + *((unsigned int *)t5) = (t22 & 15U); + t8 = (t0 + 1448); + xsi_vlogvar_assign_value(t8, t6, 0, 0, 4); + goto LAB2; + +LAB8: t9 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t9) = 1; + goto LAB10; + +LAB9: *((unsigned int *)t6) = 1; + goto LAB10; + +LAB12: xsi_set_current_line(36, ng0); + +LAB14: xsi_set_current_line(37, ng0); + t11 = (t0 + 1928); + t12 = (t11 + 56U); + t13 = *((char **)t12); + t19 = ((char*)((ng3))); + memset(t20, 0, 8); + xsi_vlog_unsigned_lshift(t20, 20, t13, 20, t19, 32); + t21 = (t0 + 1928); + xsi_vlogvar_assign_value(t21, t20, 0, 0, 20); + xsi_set_current_line(38, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t6 + 4); + t7 = (t4 + 4); + t14 = *((unsigned int *)t4); + t15 = (t14 >> 16); + *((unsigned int *)t6) = t15; + t16 = *((unsigned int *)t7); + t17 = (t16 >> 16); + *((unsigned int *)t5) = t17; + t18 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t18 & 15U); + t22 = *((unsigned int *)t5); + *((unsigned int *)t5) = (t22 & 15U); + t8 = ((char*)((ng4))); + memset(t20, 0, 8); + t9 = (t6 + 4); + if (*((unsigned int *)t9) != 0) + goto LAB16; + +LAB15: t10 = (t8 + 4); + if (*((unsigned int *)t10) != 0) + goto LAB16; + +LAB19: if (*((unsigned int *)t6) < *((unsigned int *)t8)) + goto LAB18; + +LAB17: *((unsigned int *)t20) = 1; + +LAB18: t12 = (t20 + 4); + t23 = *((unsigned int *)t12); + t24 = (~(t23)); + t25 = *((unsigned int *)t20); + t26 = (t25 & t24); + t27 = (t26 != 0); + if (t27 > 0) + goto LAB20; + +LAB21: +LAB22: xsi_set_current_line(41, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t6 + 4); + t7 = (t4 + 4); + t14 = *((unsigned int *)t4); + t15 = (t14 >> 12); + *((unsigned int *)t6) = t15; + t16 = *((unsigned int *)t7); + t17 = (t16 >> 12); + *((unsigned int *)t5) = t17; + t18 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t18 & 15U); + t22 = *((unsigned int *)t5); + *((unsigned int *)t5) = (t22 & 15U); + t8 = ((char*)((ng4))); + memset(t20, 0, 8); + t9 = (t6 + 4); + if (*((unsigned int *)t9) != 0) + goto LAB27; + +LAB26: t10 = (t8 + 4); + if (*((unsigned int *)t10) != 0) + goto LAB27; + +LAB30: if (*((unsigned int *)t6) < *((unsigned int *)t8)) + goto LAB29; + +LAB28: *((unsigned int *)t20) = 1; + +LAB29: t12 = (t20 + 4); + t23 = *((unsigned int *)t12); + t24 = (~(t23)); + t25 = *((unsigned int *)t20); + t26 = (t25 & t24); + t27 = (t26 != 0); + if (t27 > 0) + goto LAB31; + +LAB32: +LAB33: xsi_set_current_line(44, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t6 + 4); + t7 = (t4 + 4); + t14 = *((unsigned int *)t4); + t15 = (t14 >> 8); + *((unsigned int *)t6) = t15; + t16 = *((unsigned int *)t7); + t17 = (t16 >> 8); + *((unsigned int *)t5) = t17; + t18 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t18 & 15U); + t22 = *((unsigned int *)t5); + *((unsigned int *)t5) = (t22 & 15U); + t8 = ((char*)((ng4))); + memset(t20, 0, 8); + t9 = (t6 + 4); + if (*((unsigned int *)t9) != 0) + goto LAB38; + +LAB37: t10 = (t8 + 4); + if (*((unsigned int *)t10) != 0) + goto LAB38; + +LAB41: if (*((unsigned int *)t6) < *((unsigned int *)t8)) + goto LAB40; + +LAB39: *((unsigned int *)t20) = 1; + +LAB40: t12 = (t20 + 4); + t23 = *((unsigned int *)t12); + t24 = (~(t23)); + t25 = *((unsigned int *)t20); + t26 = (t25 & t24); + t27 = (t26 != 0); + if (t27 > 0) + goto LAB42; + +LAB43: +LAB44: xsi_set_current_line(36, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = ((char*)((ng3))); + memset(t6, 0, 8); + xsi_vlog_unsigned_add(t6, 32, t4, 4, t5, 32); + t7 = (t0 + 2088); + xsi_vlogvar_assign_value(t7, t6, 0, 0, 4); + goto LAB6; + +LAB16: t11 = (t20 + 4); + *((unsigned int *)t20) = 1; + *((unsigned int *)t11) = 1; + goto LAB18; + +LAB20: xsi_set_current_line(38, ng0); + +LAB23: xsi_set_current_line(39, ng0); + t13 = (t0 + 1928); + t19 = (t13 + 56U); + t21 = *((char **)t19); + memset(t28, 0, 8); + t29 = (t28 + 4); + t30 = (t21 + 4); + t31 = *((unsigned int *)t21); + t32 = (t31 >> 16); + *((unsigned int *)t28) = t32; + t33 = *((unsigned int *)t30); + t34 = (t33 >> 16); + *((unsigned int *)t29) = t34; + t35 = *((unsigned int *)t28); + *((unsigned int *)t28) = (t35 & 15U); + t36 = *((unsigned int *)t29); + *((unsigned int *)t29) = (t36 & 15U); + t37 = ((char*)((ng5))); + memset(t38, 0, 8); + xsi_vlog_unsigned_add(t38, 32, t28, 32, t37, 32); + t39 = (t0 + 1928); + t43 = (t0 + 1928); + t44 = (t43 + 72U); + t45 = *((char **)t44); + t46 = ((char*)((ng6))); + t47 = ((char*)((ng7))); + xsi_vlog_convert_partindices(t40, t41, t42, ((int*)(t45)), 2, t46, 32, 1, t47, 32, 1); + t48 = (t40 + 4); + t49 = *((unsigned int *)t48); + t50 = (!(t49)); + t51 = (t41 + 4); + t52 = *((unsigned int *)t51); + t53 = (!(t52)); + t54 = (t50 && t53); + t55 = (t42 + 4); + t56 = *((unsigned int *)t55); + t57 = (!(t56)); + t58 = (t54 && t57); + if (t58 == 1) + goto LAB24; + +LAB25: goto LAB22; + +LAB24: t59 = *((unsigned int *)t42); + t60 = (t59 + 0); + t61 = *((unsigned int *)t40); + t62 = *((unsigned int *)t41); + t63 = (t61 - t62); + t64 = (t63 + 1); + xsi_vlogvar_assign_value(t39, t38, t60, *((unsigned int *)t41), t64); + goto LAB25; + +LAB27: t11 = (t20 + 4); + *((unsigned int *)t20) = 1; + *((unsigned int *)t11) = 1; + goto LAB29; + +LAB31: xsi_set_current_line(41, ng0); + +LAB34: xsi_set_current_line(42, ng0); + t13 = (t0 + 1928); + t19 = (t13 + 56U); + t21 = *((char **)t19); + memset(t28, 0, 8); + t29 = (t28 + 4); + t30 = (t21 + 4); + t31 = *((unsigned int *)t21); + t32 = (t31 >> 12); + *((unsigned int *)t28) = t32; + t33 = *((unsigned int *)t30); + t34 = (t33 >> 12); + *((unsigned int *)t29) = t34; + t35 = *((unsigned int *)t28); + *((unsigned int *)t28) = (t35 & 15U); + t36 = *((unsigned int *)t29); + *((unsigned int *)t29) = (t36 & 15U); + t37 = ((char*)((ng5))); + memset(t38, 0, 8); + xsi_vlog_unsigned_add(t38, 32, t28, 32, t37, 32); + t39 = (t0 + 1928); + t43 = (t0 + 1928); + t44 = (t43 + 72U); + t45 = *((char **)t44); + t46 = ((char*)((ng8))); + t47 = ((char*)((ng9))); + xsi_vlog_convert_partindices(t40, t41, t42, ((int*)(t45)), 2, t46, 32, 1, t47, 32, 1); + t48 = (t40 + 4); + t49 = *((unsigned int *)t48); + t50 = (!(t49)); + t51 = (t41 + 4); + t52 = *((unsigned int *)t51); + t53 = (!(t52)); + t54 = (t50 && t53); + t55 = (t42 + 4); + t56 = *((unsigned int *)t55); + t57 = (!(t56)); + t58 = (t54 && t57); + if (t58 == 1) + goto LAB35; + +LAB36: goto LAB33; + +LAB35: t59 = *((unsigned int *)t42); + t60 = (t59 + 0); + t61 = *((unsigned int *)t40); + t62 = *((unsigned int *)t41); + t63 = (t61 - t62); + t64 = (t63 + 1); + xsi_vlogvar_assign_value(t39, t38, t60, *((unsigned int *)t41), t64); + goto LAB36; + +LAB38: t11 = (t20 + 4); + *((unsigned int *)t20) = 1; + *((unsigned int *)t11) = 1; + goto LAB40; + +LAB42: xsi_set_current_line(44, ng0); + +LAB45: xsi_set_current_line(45, ng0); + t13 = (t0 + 1928); + t19 = (t13 + 56U); + t21 = *((char **)t19); + memset(t28, 0, 8); + t29 = (t28 + 4); + t30 = (t21 + 4); + t31 = *((unsigned int *)t21); + t32 = (t31 >> 8); + *((unsigned int *)t28) = t32; + t33 = *((unsigned int *)t30); + t34 = (t33 >> 8); + *((unsigned int *)t29) = t34; + t35 = *((unsigned int *)t28); + *((unsigned int *)t28) = (t35 & 15U); + t36 = *((unsigned int *)t29); + *((unsigned int *)t29) = (t36 & 15U); + t37 = ((char*)((ng5))); + memset(t38, 0, 8); + xsi_vlog_unsigned_add(t38, 32, t28, 32, t37, 32); + t39 = (t0 + 1928); + t43 = (t0 + 1928); + t44 = (t43 + 72U); + t45 = *((char **)t44); + t46 = ((char*)((ng10))); + t47 = ((char*)((ng11))); + xsi_vlog_convert_partindices(t40, t41, t42, ((int*)(t45)), 2, t46, 32, 1, t47, 32, 1); + t48 = (t40 + 4); + t49 = *((unsigned int *)t48); + t50 = (!(t49)); + t51 = (t41 + 4); + t52 = *((unsigned int *)t51); + t53 = (!(t52)); + t54 = (t50 && t53); + t55 = (t42 + 4); + t56 = *((unsigned int *)t55); + t57 = (!(t56)); + t58 = (t54 && t57); + if (t58 == 1) + goto LAB46; + +LAB47: goto LAB44; + +LAB46: t59 = *((unsigned int *)t42); + t60 = (t59 + 0); + t61 = *((unsigned int *)t40); + t62 = *((unsigned int *)t41); + t63 = (t61 - t62); + t64 = (t63 + 1); + xsi_vlogvar_assign_value(t39, t38, t60, *((unsigned int *)t41), t64); + goto LAB47; + +} + + +extern void work_m_14079594305330756291_2618506667_init() +{ + static char *pe[] = {(void *)Always_32_0}; + xsi_register_didat("work_m_14079594305330756291_2618506667", "isim/Test_ContdownController_isim_beh.exe.sim/work/m_14079594305330756291_2618506667.didat"); + xsi_register_executes(pe); +} diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14079594305330756291_2618506667.didat b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14079594305330756291_2618506667.didat Binary files differnew file mode 100644 index 0000000..ab5f612 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14079594305330756291_2618506667.didat diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14079594305330756291_2618506667.lin64.o b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14079594305330756291_2618506667.lin64.o Binary files differnew file mode 100644 index 0000000..d8618b6 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14079594305330756291_2618506667.lin64.o diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14181161885881575918_3845763652.c b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14181161885881575918_3845763652.c new file mode 100644 index 0000000..c8ac153 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14181161885881575918_3845763652.c @@ -0,0 +1,249 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab4/DisplayController.v"; +static unsigned int ng1[] = {3U, 0U}; + + + +static void Always_41_0(char *t0) +{ + char t4[8]; + char t26[8]; + char *t1; + char *t2; + char *t3; + char *t5; + char *t6; + char *t7; + char *t8; + unsigned int t9; + unsigned int t10; + unsigned int t11; + unsigned int t12; + unsigned int t13; + char *t14; + char *t15; + char *t16; + unsigned int t17; + unsigned int t18; + unsigned int t19; + unsigned int t20; + unsigned int t21; + unsigned int t22; + unsigned int t23; + unsigned int t24; + char *t25; + char *t27; + char *t28; + +LAB0: t1 = (t0 + 3480U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(41, ng0); + t2 = (t0 + 3800); + *((int *)t2) = 1; + t3 = (t0 + 3512); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(41, ng0); + +LAB5: xsi_set_current_line(42, ng0); + t5 = (t0 + 2568); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memset(t4, 0, 8); + t8 = (t7 + 4); + t9 = *((unsigned int *)t8); + t10 = (~(t9)); + t11 = *((unsigned int *)t7); + t12 = (t11 & t10); + t13 = (t12 & 1U); + if (t13 != 0) + goto LAB9; + +LAB7: if (*((unsigned int *)t8) == 0) + goto LAB6; + +LAB8: t14 = (t4 + 4); + *((unsigned int *)t4) = 1; + *((unsigned int *)t14) = 1; + +LAB9: t15 = (t4 + 4); + t16 = (t7 + 4); + t17 = *((unsigned int *)t7); + t18 = (~(t17)); + *((unsigned int *)t4) = t18; + *((unsigned int *)t15) = 0; + if (*((unsigned int *)t16) != 0) + goto LAB11; + +LAB10: t23 = *((unsigned int *)t4); + *((unsigned int *)t4) = (t23 & 1U); + t24 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t24 & 1U); + t25 = (t0 + 2568); + xsi_vlogvar_wait_assign_value(t25, t4, 0, 0, 1, 0LL); + xsi_set_current_line(43, ng0); + t2 = (t0 + 2568); + t3 = (t2 + 56U); + t5 = *((char **)t3); + memset(t26, 0, 8); + t6 = (t5 + 4); + t9 = *((unsigned int *)t6); + t10 = (~(t9)); + t11 = *((unsigned int *)t5); + t12 = (t11 & t10); + t13 = (t12 & 1U); + if (t13 != 0) + goto LAB12; + +LAB13: if (*((unsigned int *)t6) != 0) + goto LAB14; + +LAB15: t8 = (t26 + 4); + t17 = *((unsigned int *)t26); + t18 = *((unsigned int *)t8); + t19 = (t17 || t18); + if (t19 > 0) + goto LAB16; + +LAB17: t20 = *((unsigned int *)t26); + t21 = (~(t20)); + t22 = *((unsigned int *)t8); + t23 = (t21 || t22); + if (t23 > 0) + goto LAB18; + +LAB19: if (*((unsigned int *)t8) > 0) + goto LAB20; + +LAB21: if (*((unsigned int *)t26) > 0) + goto LAB22; + +LAB23: memcpy(t4, t16, 8); + +LAB24: t14 = (t0 + 2248); + xsi_vlogvar_wait_assign_value(t14, t4, 0, 0, 7, 0LL); + xsi_set_current_line(44, ng0); + t2 = (t0 + 2568); + t3 = (t2 + 56U); + t5 = *((char **)t3); + memset(t26, 0, 8); + t6 = (t5 + 4); + t9 = *((unsigned int *)t6); + t10 = (~(t9)); + t11 = *((unsigned int *)t5); + t12 = (t11 & t10); + t13 = (t12 & 1U); + if (t13 != 0) + goto LAB28; + +LAB26: if (*((unsigned int *)t6) == 0) + goto LAB25; + +LAB27: t7 = (t26 + 4); + *((unsigned int *)t26) = 1; + *((unsigned int *)t7) = 1; + +LAB28: t8 = (t26 + 4); + t14 = (t5 + 4); + t17 = *((unsigned int *)t5); + t18 = (~(t17)); + *((unsigned int *)t26) = t18; + *((unsigned int *)t8) = 0; + if (*((unsigned int *)t14) != 0) + goto LAB30; + +LAB29: t23 = *((unsigned int *)t26); + *((unsigned int *)t26) = (t23 & 1U); + t24 = *((unsigned int *)t8); + *((unsigned int *)t8) = (t24 & 1U); + t15 = (t0 + 2568); + t16 = (t15 + 56U); + t25 = *((char **)t16); + t27 = ((char*)((ng1))); + xsi_vlogtype_concat(t4, 4, 4, 3U, t27, 2, t25, 1, t26, 1); + t28 = (t0 + 2408); + xsi_vlogvar_wait_assign_value(t28, t4, 0, 0, 4, 0LL); + goto LAB2; + +LAB6: *((unsigned int *)t4) = 1; + goto LAB9; + +LAB11: t19 = *((unsigned int *)t4); + t20 = *((unsigned int *)t16); + *((unsigned int *)t4) = (t19 | t20); + t21 = *((unsigned int *)t15); + t22 = *((unsigned int *)t16); + *((unsigned int *)t15) = (t21 | t22); + goto LAB10; + +LAB12: *((unsigned int *)t26) = 1; + goto LAB15; + +LAB14: t7 = (t26 + 4); + *((unsigned int *)t26) = 1; + *((unsigned int *)t7) = 1; + goto LAB15; + +LAB16: t14 = (t0 + 1688U); + t15 = *((char **)t14); + goto LAB17; + +LAB18: t14 = (t0 + 1848U); + t16 = *((char **)t14); + goto LAB19; + +LAB20: xsi_vlog_unsigned_bit_combine(t4, 7, t15, 7, t16, 7); + goto LAB24; + +LAB22: memcpy(t4, t15, 8); + goto LAB24; + +LAB25: *((unsigned int *)t26) = 1; + goto LAB28; + +LAB30: t19 = *((unsigned int *)t26); + t20 = *((unsigned int *)t14); + *((unsigned int *)t26) = (t19 | t20); + t21 = *((unsigned int *)t8); + t22 = *((unsigned int *)t14); + *((unsigned int *)t8) = (t21 | t22); + goto LAB29; + +} + + +extern void work_m_14181161885881575918_3845763652_init() +{ + static char *pe[] = {(void *)Always_41_0}; + xsi_register_didat("work_m_14181161885881575918_3845763652", "isim/Test_ContdownController_isim_beh.exe.sim/work/m_14181161885881575918_3845763652.didat"); + xsi_register_executes(pe); +} diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14181161885881575918_3845763652.didat b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14181161885881575918_3845763652.didat Binary files differnew file mode 100644 index 0000000..b86ca85 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14181161885881575918_3845763652.didat diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14181161885881575918_3845763652.lin64.o b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14181161885881575918_3845763652.lin64.o Binary files differnew file mode 100644 index 0000000..52f30b3 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14181161885881575918_3845763652.lin64.o diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14878824473863214981_2647877144.c b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14878824473863214981_2647877144.c new file mode 100644 index 0000000..848bccb --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14878824473863214981_2647877144.c @@ -0,0 +1,203 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab4/Increment.v"; +static int ng1[] = {9, 0}; +static int ng2[] = {0, 0}; +static int ng3[] = {1, 0}; + + + +static void Always_28_0(char *t0) +{ + char t4[8]; + char t5[8]; + char t10[8]; + char t46[8]; + char *t1; + char *t2; + char *t3; + char *t6; + char *t7; + char *t8; + char *t9; + char *t11; + char *t12; + unsigned int t13; + unsigned int t14; + unsigned int t15; + unsigned int t16; + unsigned int t17; + unsigned int t18; + unsigned int t19; + unsigned int t20; + unsigned int t21; + unsigned int t22; + unsigned int t23; + unsigned int t24; + char *t25; + char *t26; + unsigned int t27; + unsigned int t28; + unsigned int t29; + unsigned int t30; + unsigned int t31; + char *t32; + char *t33; + unsigned int t34; + unsigned int t35; + unsigned int t36; + char *t37; + unsigned int t38; + unsigned int t39; + unsigned int t40; + unsigned int t41; + char *t42; + char *t43; + char *t44; + char *t45; + char *t47; + +LAB0: t1 = (t0 + 2360U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(28, ng0); + t2 = (t0 + 2680); + *((int *)t2) = 1; + t3 = (t0 + 2392); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(28, ng0); + +LAB5: xsi_set_current_line(29, ng0); + t6 = (t0 + 1448); + t7 = (t6 + 56U); + t8 = *((char **)t7); + t9 = ((char*)((ng1))); + memset(t10, 0, 8); + t11 = (t8 + 4); + t12 = (t9 + 4); + t13 = *((unsigned int *)t8); + t14 = *((unsigned int *)t9); + t15 = (t13 ^ t14); + t16 = *((unsigned int *)t11); + t17 = *((unsigned int *)t12); + t18 = (t16 ^ t17); + t19 = (t15 | t18); + t20 = *((unsigned int *)t11); + t21 = *((unsigned int *)t12); + t22 = (t20 | t21); + t23 = (~(t22)); + t24 = (t19 & t23); + if (t24 != 0) + goto LAB9; + +LAB6: if (t22 != 0) + goto LAB8; + +LAB7: *((unsigned int *)t10) = 1; + +LAB9: memset(t5, 0, 8); + t26 = (t10 + 4); + t27 = *((unsigned int *)t26); + t28 = (~(t27)); + t29 = *((unsigned int *)t10); + t30 = (t29 & t28); + t31 = (t30 & 1U); + if (t31 != 0) + goto LAB10; + +LAB11: if (*((unsigned int *)t26) != 0) + goto LAB12; + +LAB13: t33 = (t5 + 4); + t34 = *((unsigned int *)t5); + t35 = *((unsigned int *)t33); + t36 = (t34 || t35); + if (t36 > 0) + goto LAB14; + +LAB15: t38 = *((unsigned int *)t5); + t39 = (~(t38)); + t40 = *((unsigned int *)t33); + t41 = (t39 || t40); + if (t41 > 0) + goto LAB16; + +LAB17: if (*((unsigned int *)t33) > 0) + goto LAB18; + +LAB19: if (*((unsigned int *)t5) > 0) + goto LAB20; + +LAB21: memcpy(t4, t46, 8); + +LAB22: t47 = (t0 + 1448); + xsi_vlogvar_assign_value(t47, t4, 0, 0, 4); + goto LAB2; + +LAB8: t25 = (t10 + 4); + *((unsigned int *)t10) = 1; + *((unsigned int *)t25) = 1; + goto LAB9; + +LAB10: *((unsigned int *)t5) = 1; + goto LAB13; + +LAB12: t32 = (t5 + 4); + *((unsigned int *)t5) = 1; + *((unsigned int *)t32) = 1; + goto LAB13; + +LAB14: t37 = ((char*)((ng2))); + goto LAB15; + +LAB16: t42 = (t0 + 1448); + t43 = (t42 + 56U); + t44 = *((char **)t43); + t45 = ((char*)((ng3))); + memset(t46, 0, 8); + xsi_vlog_unsigned_add(t46, 32, t44, 4, t45, 32); + goto LAB17; + +LAB18: xsi_vlog_unsigned_bit_combine(t4, 32, t37, 32, t46, 32); + goto LAB22; + +LAB20: memcpy(t4, t37, 8); + goto LAB22; + +} + + +extern void work_m_14878824473863214981_2647877144_init() +{ + static char *pe[] = {(void *)Always_28_0}; + xsi_register_didat("work_m_14878824473863214981_2647877144", "isim/Test_ContdownController_isim_beh.exe.sim/work/m_14878824473863214981_2647877144.didat"); + xsi_register_executes(pe); +} diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14878824473863214981_2647877144.didat b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14878824473863214981_2647877144.didat Binary files differnew file mode 100644 index 0000000..1af083e --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14878824473863214981_2647877144.didat diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14878824473863214981_2647877144.lin64.o b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14878824473863214981_2647877144.lin64.o Binary files differnew file mode 100644 index 0000000..18e78cf --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_14878824473863214981_2647877144.lin64.o diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c new file mode 100644 index 0000000..960761b --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c @@ -0,0 +1,337 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/verilog/src/glbl.v"; +static unsigned int ng1[] = {1U, 0U}; +static unsigned int ng2[] = {0U, 0U}; + + + +static void NetDecl_16_0(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + char *t10; + unsigned int t11; + unsigned int t12; + char *t13; + unsigned int t14; + unsigned int t15; + char *t16; + +LAB0: t1 = (t0 + 6952U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(16, ng0); + t2 = (t0 + 1960U); + t3 = *((char **)t2); + t2 = (t0 + 8640); + t4 = (t2 + 56U); + t5 = *((char **)t4); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memset(t7, 0, 8); + t8 = 1U; + t9 = t8; + t10 = (t3 + 4); + t11 = *((unsigned int *)t3); + t8 = (t8 & t11); + t12 = *((unsigned int *)t10); + t9 = (t9 & t12); + t13 = (t7 + 4); + t14 = *((unsigned int *)t7); + *((unsigned int *)t7) = (t14 | t8); + t15 = *((unsigned int *)t13); + *((unsigned int *)t13) = (t15 | t9); + xsi_driver_vfirst_trans(t2, 0, 0U); + t16 = (t0 + 8512); + *((int *)t16) = 1; + +LAB1: return; +} + +static void Cont_48_1(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7200U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(48, ng0); + t2 = (t0 + 3640); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8704); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8528); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Cont_49_2(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7448U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(49, ng0); + t2 = (t0 + 3800); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8768); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8544); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Cont_50_3(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7696U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(50, ng0); + t2 = (t0 + 3960); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8832); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8560); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Initial_52_4(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + +LAB0: t1 = (t0 + 7944U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(52, ng0); + +LAB4: xsi_set_current_line(53, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3640); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(54, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3960); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(55, ng0); + t2 = (t0 + 7752); + xsi_process_wait(t2, 100000LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(56, ng0); + t3 = ((char*)((ng2))); + t4 = (t0 + 3640); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + xsi_set_current_line(57, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 3960); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + goto LAB1; + +} + +static void Initial_60_5(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + +LAB0: t1 = (t0 + 8192U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(60, ng0); + +LAB4: xsi_set_current_line(61, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3800); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(62, ng0); + t2 = (t0 + 8000); + xsi_process_wait(t2, 0LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(63, ng0); + t3 = ((char*)((ng2))); + t4 = (t0 + 3800); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + goto LAB1; + +} + + +extern void work_m_16541823861846354283_2073120511_init() +{ + static char *pe[] = {(void *)NetDecl_16_0,(void *)Cont_48_1,(void *)Cont_49_2,(void *)Cont_50_3,(void *)Initial_52_4,(void *)Initial_60_5}; + xsi_register_didat("work_m_16541823861846354283_2073120511", "isim/Test_ContdownController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat"); + xsi_register_executes(pe); +} diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat Binary files differnew file mode 100644 index 0000000..542d5ed --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o Binary files differnew file mode 100644 index 0000000..b79f2d7 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_17579661360444318263_0092613024.c b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_17579661360444318263_0092613024.c new file mode 100644 index 0000000..dd4c38d --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_17579661360444318263_0092613024.c @@ -0,0 +1,538 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab4/BCD2Bin.v"; +static int ng1[] = {0, 0}; +static int ng2[] = {7, 0}; +static int ng3[] = {1, 0}; +static int ng4[] = {5, 0}; +static int ng5[] = {3, 0}; +static int ng6[] = {19, 0}; +static int ng7[] = {16, 0}; +static int ng8[] = {15, 0}; +static int ng9[] = {12, 0}; +static int ng10[] = {11, 0}; +static int ng11[] = {8, 0}; + + + +static void Always_33_0(char *t0) +{ + char t4[8]; + char t20[8]; + char t28[8]; + char t38[8]; + char t40[8]; + char t41[8]; + char t42[8]; + char *t1; + char *t2; + char *t3; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + char *t10; + char *t11; + unsigned int t12; + unsigned int t13; + unsigned int t14; + unsigned int t15; + unsigned int t16; + char *t17; + char *t18; + char *t19; + char *t21; + unsigned int t22; + unsigned int t23; + unsigned int t24; + unsigned int t25; + unsigned int t26; + unsigned int t27; + char *t29; + char *t30; + unsigned int t31; + unsigned int t32; + unsigned int t33; + unsigned int t34; + unsigned int t35; + unsigned int t36; + char *t37; + char *t39; + char *t43; + char *t44; + char *t45; + char *t46; + char *t47; + char *t48; + unsigned int t49; + int t50; + char *t51; + unsigned int t52; + int t53; + int t54; + char *t55; + unsigned int t56; + int t57; + int t58; + unsigned int t59; + int t60; + unsigned int t61; + unsigned int t62; + int t63; + int t64; + +LAB0: t1 = (t0 + 3000U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(33, ng0); + t2 = (t0 + 3320); + *((int *)t2) = 1; + t3 = (t0 + 3032); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(33, ng0); + +LAB5: xsi_set_current_line(35, ng0); + t5 = (t0 + 1768); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t0 + 1368U); + t9 = *((char **)t8); + t8 = (t0 + 1208U); + t10 = *((char **)t8); + t8 = (t0 + 1048U); + t11 = *((char **)t8); + xsi_vlogtype_concat(t4, 20, 20, 4U, t11, 4, t10, 4, t9, 4, t7, 8); + t8 = (t0 + 2088); + xsi_vlogvar_assign_value(t8, t4, 0, 0, 20); + xsi_set_current_line(39, ng0); + xsi_set_current_line(39, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 3); + +LAB6: t2 = (t0 + 1928); + t3 = (t2 + 56U); + t5 = *((char **)t3); + t6 = ((char*)((ng2))); + memset(t4, 0, 8); + t7 = (t5 + 4); + if (*((unsigned int *)t7) != 0) + goto LAB8; + +LAB7: t8 = (t6 + 4); + if (*((unsigned int *)t8) != 0) + goto LAB8; + +LAB11: if (*((unsigned int *)t5) < *((unsigned int *)t6)) + goto LAB9; + +LAB10: t10 = (t4 + 4); + t12 = *((unsigned int *)t10); + t13 = (~(t12)); + t14 = *((unsigned int *)t4); + t15 = (t14 & t13); + t16 = (t15 != 0); + if (t16 > 0) + goto LAB12; + +LAB13: xsi_set_current_line(52, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t5 = *((char **)t3); + t6 = ((char*)((ng3))); + memset(t4, 0, 8); + xsi_vlog_unsigned_rshift(t4, 20, t5, 20, t6, 32); + t7 = (t0 + 2088); + xsi_vlogvar_assign_value(t7, t4, 0, 0, 20); + xsi_set_current_line(54, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t5 = *((char **)t3); + memset(t4, 0, 8); + t6 = (t4 + 4); + t7 = (t5 + 4); + t12 = *((unsigned int *)t5); + t13 = (t12 >> 0); + *((unsigned int *)t4) = t13; + t14 = *((unsigned int *)t7); + t15 = (t14 >> 0); + *((unsigned int *)t6) = t15; + t16 = *((unsigned int *)t4); + *((unsigned int *)t4) = (t16 & 255U); + t22 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t22 & 255U); + t8 = (t0 + 1768); + xsi_vlogvar_assign_value(t8, t4, 0, 0, 8); + goto LAB2; + +LAB8: t9 = (t4 + 4); + *((unsigned int *)t4) = 1; + *((unsigned int *)t9) = 1; + goto LAB10; + +LAB9: *((unsigned int *)t4) = 1; + goto LAB10; + +LAB12: xsi_set_current_line(39, ng0); + +LAB14: xsi_set_current_line(40, ng0); + t11 = (t0 + 2088); + t17 = (t11 + 56U); + t18 = *((char **)t17); + t19 = ((char*)((ng3))); + memset(t20, 0, 8); + xsi_vlog_unsigned_rshift(t20, 20, t18, 20, t19, 32); + t21 = (t0 + 2088); + xsi_vlogvar_assign_value(t21, t20, 0, 0, 20); + xsi_set_current_line(41, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t5 = *((char **)t3); + memset(t4, 0, 8); + t6 = (t4 + 4); + t7 = (t5 + 4); + t12 = *((unsigned int *)t5); + t13 = (t12 >> 16); + *((unsigned int *)t4) = t13; + t14 = *((unsigned int *)t7); + t15 = (t14 >> 16); + *((unsigned int *)t6) = t15; + t16 = *((unsigned int *)t4); + *((unsigned int *)t4) = (t16 & 15U); + t22 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t22 & 15U); + t8 = ((char*)((ng4))); + memset(t20, 0, 8); + t9 = (t4 + 4); + if (*((unsigned int *)t9) != 0) + goto LAB16; + +LAB15: t10 = (t8 + 4); + if (*((unsigned int *)t10) != 0) + goto LAB16; + +LAB19: if (*((unsigned int *)t4) < *((unsigned int *)t8)) + goto LAB18; + +LAB17: *((unsigned int *)t20) = 1; + +LAB18: t17 = (t20 + 4); + t23 = *((unsigned int *)t17); + t24 = (~(t23)); + t25 = *((unsigned int *)t20); + t26 = (t25 & t24); + t27 = (t26 != 0); + if (t27 > 0) + goto LAB20; + +LAB21: +LAB22: xsi_set_current_line(44, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t5 = *((char **)t3); + memset(t4, 0, 8); + t6 = (t4 + 4); + t7 = (t5 + 4); + t12 = *((unsigned int *)t5); + t13 = (t12 >> 12); + *((unsigned int *)t4) = t13; + t14 = *((unsigned int *)t7); + t15 = (t14 >> 12); + *((unsigned int *)t6) = t15; + t16 = *((unsigned int *)t4); + *((unsigned int *)t4) = (t16 & 15U); + t22 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t22 & 15U); + t8 = ((char*)((ng4))); + memset(t20, 0, 8); + t9 = (t4 + 4); + if (*((unsigned int *)t9) != 0) + goto LAB27; + +LAB26: t10 = (t8 + 4); + if (*((unsigned int *)t10) != 0) + goto LAB27; + +LAB30: if (*((unsigned int *)t4) < *((unsigned int *)t8)) + goto LAB29; + +LAB28: *((unsigned int *)t20) = 1; + +LAB29: t17 = (t20 + 4); + t23 = *((unsigned int *)t17); + t24 = (~(t23)); + t25 = *((unsigned int *)t20); + t26 = (t25 & t24); + t27 = (t26 != 0); + if (t27 > 0) + goto LAB31; + +LAB32: +LAB33: xsi_set_current_line(47, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t5 = *((char **)t3); + memset(t4, 0, 8); + t6 = (t4 + 4); + t7 = (t5 + 4); + t12 = *((unsigned int *)t5); + t13 = (t12 >> 8); + *((unsigned int *)t4) = t13; + t14 = *((unsigned int *)t7); + t15 = (t14 >> 8); + *((unsigned int *)t6) = t15; + t16 = *((unsigned int *)t4); + *((unsigned int *)t4) = (t16 & 15U); + t22 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t22 & 15U); + t8 = ((char*)((ng4))); + memset(t20, 0, 8); + t9 = (t4 + 4); + if (*((unsigned int *)t9) != 0) + goto LAB38; + +LAB37: t10 = (t8 + 4); + if (*((unsigned int *)t10) != 0) + goto LAB38; + +LAB41: if (*((unsigned int *)t4) < *((unsigned int *)t8)) + goto LAB40; + +LAB39: *((unsigned int *)t20) = 1; + +LAB40: t17 = (t20 + 4); + t23 = *((unsigned int *)t17); + t24 = (~(t23)); + t25 = *((unsigned int *)t20); + t26 = (t25 & t24); + t27 = (t26 != 0); + if (t27 > 0) + goto LAB42; + +LAB43: +LAB44: xsi_set_current_line(39, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t5 = *((char **)t3); + t6 = ((char*)((ng3))); + memset(t4, 0, 8); + xsi_vlog_unsigned_add(t4, 32, t5, 3, t6, 32); + t7 = (t0 + 1928); + xsi_vlogvar_assign_value(t7, t4, 0, 0, 3); + goto LAB6; + +LAB16: t11 = (t20 + 4); + *((unsigned int *)t20) = 1; + *((unsigned int *)t11) = 1; + goto LAB18; + +LAB20: xsi_set_current_line(41, ng0); + +LAB23: xsi_set_current_line(42, ng0); + t18 = (t0 + 2088); + t19 = (t18 + 56U); + t21 = *((char **)t19); + memset(t28, 0, 8); + t29 = (t28 + 4); + t30 = (t21 + 4); + t31 = *((unsigned int *)t21); + t32 = (t31 >> 16); + *((unsigned int *)t28) = t32; + t33 = *((unsigned int *)t30); + t34 = (t33 >> 16); + *((unsigned int *)t29) = t34; + t35 = *((unsigned int *)t28); + *((unsigned int *)t28) = (t35 & 15U); + t36 = *((unsigned int *)t29); + *((unsigned int *)t29) = (t36 & 15U); + t37 = ((char*)((ng5))); + memset(t38, 0, 8); + xsi_vlog_unsigned_minus(t38, 32, t28, 32, t37, 32); + t39 = (t0 + 2088); + t43 = (t0 + 2088); + t44 = (t43 + 72U); + t45 = *((char **)t44); + t46 = ((char*)((ng6))); + t47 = ((char*)((ng7))); + xsi_vlog_convert_partindices(t40, t41, t42, ((int*)(t45)), 2, t46, 32, 1, t47, 32, 1); + t48 = (t40 + 4); + t49 = *((unsigned int *)t48); + t50 = (!(t49)); + t51 = (t41 + 4); + t52 = *((unsigned int *)t51); + t53 = (!(t52)); + t54 = (t50 && t53); + t55 = (t42 + 4); + t56 = *((unsigned int *)t55); + t57 = (!(t56)); + t58 = (t54 && t57); + if (t58 == 1) + goto LAB24; + +LAB25: goto LAB22; + +LAB24: t59 = *((unsigned int *)t42); + t60 = (t59 + 0); + t61 = *((unsigned int *)t40); + t62 = *((unsigned int *)t41); + t63 = (t61 - t62); + t64 = (t63 + 1); + xsi_vlogvar_assign_value(t39, t38, t60, *((unsigned int *)t41), t64); + goto LAB25; + +LAB27: t11 = (t20 + 4); + *((unsigned int *)t20) = 1; + *((unsigned int *)t11) = 1; + goto LAB29; + +LAB31: xsi_set_current_line(44, ng0); + +LAB34: xsi_set_current_line(45, ng0); + t18 = (t0 + 2088); + t19 = (t18 + 56U); + t21 = *((char **)t19); + memset(t28, 0, 8); + t29 = (t28 + 4); + t30 = (t21 + 4); + t31 = *((unsigned int *)t21); + t32 = (t31 >> 12); + *((unsigned int *)t28) = t32; + t33 = *((unsigned int *)t30); + t34 = (t33 >> 12); + *((unsigned int *)t29) = t34; + t35 = *((unsigned int *)t28); + *((unsigned int *)t28) = (t35 & 15U); + t36 = *((unsigned int *)t29); + *((unsigned int *)t29) = (t36 & 15U); + t37 = ((char*)((ng5))); + memset(t38, 0, 8); + xsi_vlog_unsigned_minus(t38, 32, t28, 32, t37, 32); + t39 = (t0 + 2088); + t43 = (t0 + 2088); + t44 = (t43 + 72U); + t45 = *((char **)t44); + t46 = ((char*)((ng8))); + t47 = ((char*)((ng9))); + xsi_vlog_convert_partindices(t40, t41, t42, ((int*)(t45)), 2, t46, 32, 1, t47, 32, 1); + t48 = (t40 + 4); + t49 = *((unsigned int *)t48); + t50 = (!(t49)); + t51 = (t41 + 4); + t52 = *((unsigned int *)t51); + t53 = (!(t52)); + t54 = (t50 && t53); + t55 = (t42 + 4); + t56 = *((unsigned int *)t55); + t57 = (!(t56)); + t58 = (t54 && t57); + if (t58 == 1) + goto LAB35; + +LAB36: goto LAB33; + +LAB35: t59 = *((unsigned int *)t42); + t60 = (t59 + 0); + t61 = *((unsigned int *)t40); + t62 = *((unsigned int *)t41); + t63 = (t61 - t62); + t64 = (t63 + 1); + xsi_vlogvar_assign_value(t39, t38, t60, *((unsigned int *)t41), t64); + goto LAB36; + +LAB38: t11 = (t20 + 4); + *((unsigned int *)t20) = 1; + *((unsigned int *)t11) = 1; + goto LAB40; + +LAB42: xsi_set_current_line(47, ng0); + +LAB45: xsi_set_current_line(48, ng0); + t18 = (t0 + 2088); + t19 = (t18 + 56U); + t21 = *((char **)t19); + memset(t28, 0, 8); + t29 = (t28 + 4); + t30 = (t21 + 4); + t31 = *((unsigned int *)t21); + t32 = (t31 >> 8); + *((unsigned int *)t28) = t32; + t33 = *((unsigned int *)t30); + t34 = (t33 >> 8); + *((unsigned int *)t29) = t34; + t35 = *((unsigned int *)t28); + *((unsigned int *)t28) = (t35 & 15U); + t36 = *((unsigned int *)t29); + *((unsigned int *)t29) = (t36 & 15U); + t37 = ((char*)((ng5))); + memset(t38, 0, 8); + xsi_vlog_unsigned_minus(t38, 32, t28, 32, t37, 32); + t39 = (t0 + 2088); + t43 = (t0 + 2088); + t44 = (t43 + 72U); + t45 = *((char **)t44); + t46 = ((char*)((ng10))); + t47 = ((char*)((ng11))); + xsi_vlog_convert_partindices(t40, t41, t42, ((int*)(t45)), 2, t46, 32, 1, t47, 32, 1); + t48 = (t40 + 4); + t49 = *((unsigned int *)t48); + t50 = (!(t49)); + t51 = (t41 + 4); + t52 = *((unsigned int *)t51); + t53 = (!(t52)); + t54 = (t50 && t53); + t55 = (t42 + 4); + t56 = *((unsigned int *)t55); + t57 = (!(t56)); + t58 = (t54 && t57); + if (t58 == 1) + goto LAB46; + +LAB47: goto LAB44; + +LAB46: t59 = *((unsigned int *)t42); + t60 = (t59 + 0); + t61 = *((unsigned int *)t40); + t62 = *((unsigned int *)t41); + t63 = (t61 - t62); + t64 = (t63 + 1); + xsi_vlogvar_assign_value(t39, t38, t60, *((unsigned int *)t41), t64); + goto LAB47; + +} + + +extern void work_m_17579661360444318263_0092613024_init() +{ + static char *pe[] = {(void *)Always_33_0}; + xsi_register_didat("work_m_17579661360444318263_0092613024", "isim/Test_ContdownController_isim_beh.exe.sim/work/m_17579661360444318263_0092613024.didat"); + xsi_register_executes(pe); +} diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_17579661360444318263_0092613024.didat b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_17579661360444318263_0092613024.didat Binary files differnew file mode 100644 index 0000000..15f3a36 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_17579661360444318263_0092613024.didat diff --git a/isim/Test_ContdownController_isim_beh.exe.sim/work/m_17579661360444318263_0092613024.lin64.o b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_17579661360444318263_0092613024.lin64.o Binary files differnew file mode 100644 index 0000000..44deea7 --- /dev/null +++ b/isim/Test_ContdownController_isim_beh.exe.sim/work/m_17579661360444318263_0092613024.lin64.o diff --git a/isim/isim_usage_statistics.html b/isim/isim_usage_statistics.html new file mode 100644 index 0000000..c994ede --- /dev/null +++ b/isim/isim_usage_statistics.html @@ -0,0 +1,16 @@ +<TABLE BORDER CELLSPACING=0 WIDTH='100%'> +<xtag-section name="ISimStatistics"> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR> +<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value></xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>1610 ms, 393132 KB</xtag-isim-property-value></TD></TR> + +<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>67</xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>223</xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>16</xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>55</xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.07 sec, 256151 KB</xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR> +</xtag-section> +</TABLE> diff --git a/isim/lockfile b/isim/lockfile new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/isim/lockfile diff --git a/isim/pn_info b/isim/pn_info new file mode 100644 index 0000000..c5644b4 --- /dev/null +++ b/isim/pn_info @@ -0,0 +1 @@ +13.4 diff --git a/isim/work/@b@c@d2@bin.sdb b/isim/work/@b@c@d2@bin.sdb Binary files differnew file mode 100644 index 0000000..5446114 --- /dev/null +++ b/isim/work/@b@c@d2@bin.sdb diff --git a/isim/work/@bin2@b@c@d.sdb b/isim/work/@bin2@b@c@d.sdb Binary files differnew file mode 100644 index 0000000..b05009d --- /dev/null +++ b/isim/work/@bin2@b@c@d.sdb diff --git a/isim/work/@clock@divider.sdb b/isim/work/@clock@divider.sdb Binary files differnew file mode 100644 index 0000000..643e0f3 --- /dev/null +++ b/isim/work/@clock@divider.sdb diff --git a/isim/work/@countdown.sdb b/isim/work/@countdown.sdb Binary files differnew file mode 100644 index 0000000..6f2fe1c --- /dev/null +++ b/isim/work/@countdown.sdb diff --git a/isim/work/@countdown@controller.sdb b/isim/work/@countdown@controller.sdb Binary files differnew file mode 100644 index 0000000..7eb46a4 --- /dev/null +++ b/isim/work/@countdown@controller.sdb diff --git a/isim/work/@display@controller.sdb b/isim/work/@display@controller.sdb Binary files differnew file mode 100644 index 0000000..cacbd04 --- /dev/null +++ b/isim/work/@display@controller.sdb diff --git a/isim/work/@increment.sdb b/isim/work/@increment.sdb Binary files differnew file mode 100644 index 0000000..fc0650a --- /dev/null +++ b/isim/work/@increment.sdb diff --git a/isim/work/@sev@seg@disp.sdb b/isim/work/@sev@seg@disp.sdb Binary files differnew file mode 100644 index 0000000..a249a35 --- /dev/null +++ b/isim/work/@sev@seg@disp.sdb diff --git a/isim/work/@test_@contdown@controller.sdb b/isim/work/@test_@contdown@controller.sdb Binary files differnew file mode 100644 index 0000000..6bc1184 --- /dev/null +++ b/isim/work/@test_@contdown@controller.sdb diff --git a/isim/work/debouncer.sdb b/isim/work/debouncer.sdb Binary files differnew file mode 100644 index 0000000..dbfeaa0 --- /dev/null +++ b/isim/work/debouncer.sdb diff --git a/isim/work/glbl.sdb b/isim/work/glbl.sdb Binary files differnew file mode 100644 index 0000000..cabad6c --- /dev/null +++ b/isim/work/glbl.sdb diff --git a/lab4.gise b/lab4.gise new file mode 100644 index 0000000..69a679c --- /dev/null +++ b/lab4.gise @@ -0,0 +1,135 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="lab4.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="CountdownController_isim_beh.exe"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Increment_isim_beh.exe"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="SevSegDisp_isim_beh.exe"/>
+ <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SevSegDisp_stx_beh.prj"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="TEST_BCD2Bin_isim_beh.exe"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="TEST_Bin2BCD_isim_beh.exe"/>
+ <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="TEST_Bin2BCD_stx_beh.prj"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="TEST_ClockDivider_isim_beh.exe"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="TEST_Countdown_isim_beh.exe"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="TEST_DisplayController_isim_beh.exe"/>
+ <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="TEST_DisplayController_stx_beh.prj"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="TEST_Increment_isim_beh.exe"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="TEST_SevSegDisp_isim_beh.exe"/>
+ <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_ContdownController_beh.prj"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_ContdownController_isim_beh.exe"/>
+ <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_ContdownController_isim_beh.wdb"/>
+ <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">
+ <transform xil_pn:end_ts="1331910423" xil_pn:name="TRANEXT_compLibraries_FPGA" xil_pn:prop_ck="-3594876569575637225" xil_pn:start_ts="1331910423">
+ <status xil_pn:value="FailedRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1331910159" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1331910159">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1332349811" xil_pn:in_ck="-1165842576399624296" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1332349811">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <outfile xil_pn:name="BCD2Bin.v"/>
+ <outfile xil_pn:name="Bin2BCD.v"/>
+ <outfile xil_pn:name="ClockDivider.v"/>
+ <outfile xil_pn:name="Countdown.v"/>
+ <outfile xil_pn:name="CountdownController.v"/>
+ <outfile xil_pn:name="DisplayController.v"/>
+ <outfile xil_pn:name="Increment.v"/>
+ <outfile xil_pn:name="SevSegDisp.v"/>
+ <outfile xil_pn:name="TEST_BCD2Bin.v"/>
+ <outfile xil_pn:name="TEST_Bin2BCD.v"/>
+ <outfile xil_pn:name="TEST_ClockDivider.v"/>
+ <outfile xil_pn:name="TEST_Countdown.v"/>
+ <outfile xil_pn:name="TEST_DisplayController.v"/>
+ <outfile xil_pn:name="TEST_Increment.v"/>
+ <outfile xil_pn:name="TEST_SevSegDisp.v"/>
+ <outfile xil_pn:name="Test_ContdownController.v"/>
+ <outfile xil_pn:name="debouncer.v"/>
+ </transform>
+ <transform xil_pn:end_ts="1332349894" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="2118202629798375462" xil_pn:start_ts="1332349894">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1332349894" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-5189240632515767324" xil_pn:start_ts="1332349894">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1331932635" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8061018727666707863" xil_pn:start_ts="1331932635">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1332349811" xil_pn:in_ck="-1165842576399624296" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1332349811">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <outfile xil_pn:name="BCD2Bin.v"/>
+ <outfile xil_pn:name="Bin2BCD.v"/>
+ <outfile xil_pn:name="ClockDivider.v"/>
+ <outfile xil_pn:name="Countdown.v"/>
+ <outfile xil_pn:name="CountdownController.v"/>
+ <outfile xil_pn:name="DisplayController.v"/>
+ <outfile xil_pn:name="Increment.v"/>
+ <outfile xil_pn:name="SevSegDisp.v"/>
+ <outfile xil_pn:name="TEST_BCD2Bin.v"/>
+ <outfile xil_pn:name="TEST_Bin2BCD.v"/>
+ <outfile xil_pn:name="TEST_ClockDivider.v"/>
+ <outfile xil_pn:name="TEST_Countdown.v"/>
+ <outfile xil_pn:name="TEST_DisplayController.v"/>
+ <outfile xil_pn:name="TEST_Increment.v"/>
+ <outfile xil_pn:name="TEST_SevSegDisp.v"/>
+ <outfile xil_pn:name="Test_ContdownController.v"/>
+ <outfile xil_pn:name="debouncer.v"/>
+ </transform>
+ <transform xil_pn:end_ts="1332349897" xil_pn:in_ck="-1165842576399624296" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-4271467981599954997" xil_pn:start_ts="1332349894">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="Test_ContdownController_beh.prj"/>
+ <outfile xil_pn:name="Test_ContdownController_isim_beh.exe"/>
+ <outfile xil_pn:name="fuse.log"/>
+ <outfile xil_pn:name="isim"/>
+ <outfile xil_pn:name="isim.log"/>
+ <outfile xil_pn:name="xilinxsim.ini"/>
+ </transform>
+ <transform xil_pn:end_ts="1332349898" xil_pn:in_ck="5762157264321675852" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="1925828390295595889" xil_pn:start_ts="1332349897">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForProperties"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="Test_ContdownController_isim_beh.wdb"/>
+ <outfile xil_pn:name="isim.cmd"/>
+ <outfile xil_pn:name="isim.log"/>
+ </transform>
+ </transforms>
+
+</generated_project>
diff --git a/lab4.xise b/lab4.xise new file mode 100644 index 0000000..ad74d59 --- /dev/null +++ b/lab4.xise @@ -0,0 +1,441 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="Bin2BCD.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="TEST_Bin2BCD.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/> + </file> + <file xil_pn:name="Increment.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="15"/> + </file> + <file xil_pn:name="TEST_Increment.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="16"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="16"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="16"/> + </file> + <file xil_pn:name="debouncer.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="Implementation" xil_pn:seqID="21"/> + </file> + <file xil_pn:name="BCD2Bin.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> + <association xil_pn:name="Implementation" xil_pn:seqID="22"/> + </file> + <file xil_pn:name="TEST_BCD2Bin.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="23"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="23"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="23"/> + </file> + <file xil_pn:name="Countdown.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> + <association xil_pn:name="Implementation" xil_pn:seqID="27"/> + </file> + <file xil_pn:name="TEST_Countdown.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="28"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="28"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="28"/> + </file> + <file xil_pn:name="ClockDivider.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> + <association xil_pn:name="Implementation" xil_pn:seqID="32"/> + </file> + <file xil_pn:name="TEST_ClockDivider.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="33"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="33"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="33"/> + </file> + <file xil_pn:name="SevSegDisp.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> + <association xil_pn:name="Implementation" xil_pn:seqID="41"/> + </file> + <file xil_pn:name="DisplayController.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="42"/> + </file> + <file xil_pn:name="CountdownController.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> + <association xil_pn:name="Implementation" xil_pn:seqID="45"/> + </file> + <file xil_pn:name="Test_ContdownController.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="33"/> + <association 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xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Other Simulator 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xil_pn:value="/Test_ContdownController" xil_pn:valueState="non-default"/> + <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_ContdownController" xil_pn:valueState="non-default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> + <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> + <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" 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<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> + <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> + <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> + <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> + <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Project File 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+ <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> + <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/> + <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> + <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> + <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> + <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|Test_ContdownController" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DesignName" xil_pn:value="lab4" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-03-16T10:14:53" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9949CD523CE8CFE8C4C2ECF880A3F0B8" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/xilinxsim.ini b/xilinxsim.ini new file mode 100644 index 0000000..600496d --- /dev/null +++ b/xilinxsim.ini @@ -0,0 +1 @@ +work=isim/work |