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| author | Michael Abed <michaelabed@gmail.com> | 2012-03-21 13:17:47 -0400 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-03-21 13:17:47 -0400 |
| commit | 2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4 (patch) | |
| tree | 9819721233275cee6e39483867818a54299a4fc1 | |
| download | ec311-lab4-2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4.tar.gz ec311-lab4-2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4.tar.bz2 ec311-lab4-2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4.zip | |
Initial Commit
111 files changed, 8339 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..57cdc36 --- /dev/null +++ b/.gitignore @@ -0,0 +1,4 @@ + +*.wdb +*.exe +*.un~ diff --git a/BCD2Bin.v b/BCD2Bin.v new file mode 100644 index 0000000..06a38c8 --- /dev/null +++ b/BCD2Bin.v @@ -0,0 +1,58 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:39:02 03/16/2012 +// Design Name: +// Module Name: BCD2Bin +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module BCD2Bin( + input [3:0] hun, + input [3:0] ten, + input [3:0] one, + output [7:0] bin + ); + +reg [7:0] bin = 0; +reg [2:0] i = 0; + +reg [19:0] work; + +always @ ( hun, ten, one ) begin + + work = {hun, ten, one, bin}; + + //work = work >> 1; + + for (i = 0; i < 7; i = i + 1) begin + work = work >> 1; + if (work[19:16] >= 5) begin + work[19:16] = work[19:16] - 3; + end + if (work[15:12] >= 5) begin + work[15:12] = work[15:12] - 3; + end + if (work[11:8] >= 5) begin + work [11:8] = work[11:8] - 3; + end + end + + work = work >> 1; + + bin = work[7:0]; + +end + +endmodule diff --git a/Bin2BCD.v b/Bin2BCD.v new file mode 100644 index 0000000..ce79f2b --- /dev/null +++ b/Bin2BCD.v @@ -0,0 +1,56 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 10:16:12 03/16/2012 +// Design Name: +// Module Name: Bin2BCD +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Bin2BCD( + input [7:0] bin, + output [3:0] one, + output [3:0] ten, + output [3:0] hun + ); + +reg [3:0] one, ten, hun; +reg [19:0] work; +reg [3:0] i; + +always @( bin ) begin + hun = 0; ten = 0; one = 0; + work = {hun, ten, one, bin}; + + for (i = 0; i < 7; i = i +1) begin + work = work << 1; + if (work[19:16] >= 5) begin + work[19:16] = work[19:16] + 3; + end + if (work[15:12] >= 5) begin + work[15:12] = work[15:12] + 3; + end + if (work[11:8] >= 5) begin + work[11:8] = work[11:8] + 3; + end + end + + work = work << 1; + + hun = work[19:16]; + ten = work[15:12]; + one = work[11:8]; +end + +endmodule diff --git a/Bin2BCD_beh.prj b/Bin2BCD_beh.prj new file mode 100644 index 0000000..837a173 --- /dev/null +++ b/Bin2BCD_beh.prj @@ -0,0 +1,2 @@ +verilog work "Bin2BCD.v" +verilog work "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/Bin2BCD_summary.html b/Bin2BCD_summary.html new file mode 100644 index 0000000..f11693f --- /dev/null +++ b/Bin2BCD_summary.html @@ -0,0 +1,79 @@ +<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> +<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> +<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'> +<TD ALIGN=CENTER COLSPAN='4'><B>Bin2BCD Project Status</B></TD></TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> +<TD>lab4.xise</TD> +<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> +<TD> No Errors </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> +<TD>Bin2BCD</TD> +<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> +<TD>New</TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> +<TD>xc6slx16-3csg324</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> +<TD>Balanced</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> +<TD> + </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> +<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> +<TD> </TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> +<TD> </TD> +</TR> +</TABLE> + + + + + + + + + + + + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> +<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> +<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> +<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +</TABLE> + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> +<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> +</TABLE> + + +<br><center><b>Date Generated:</b> 03/16/2012 - 11:06:11</center> +</BODY></HTML>
\ No newline at end of file diff --git a/ClockDivider.v b/ClockDivider.v new file mode 100644 index 0000000..2447e7e --- /dev/null +++ b/ClockDivider.v @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +/////////////////////////////////// |