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author | Michael Abed <michaelabed@gmail.com> | 2012-03-21 13:50:55 -0400 |
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committer | Michael Abed <michaelabed@gmail.com> | 2012-03-21 13:50:55 -0400 |
commit | 334a727da522f84f4f243cd743c7f29971e462fe (patch) | |
tree | fe0194cc48227790f9a2c691366ae73af022bbda /CountdownController.v | |
parent | 1a28b82559b9fe09de7f18249d0ca4870fa9c501 (diff) | |
download | ec311-lab4-334a727da522f84f4f243cd743c7f29971e462fe.tar.gz ec311-lab4-334a727da522f84f4f243cd743c7f29971e462fe.tar.bz2 ec311-lab4-334a727da522f84f4f243cd743c7f29971e462fe.zip |
testing debouncer is silly
Diffstat (limited to 'CountdownController.v')
-rw-r--r-- | CountdownController.v | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/CountdownController.v b/CountdownController.v index ac50bf0..35c84f9 100644 --- a/CountdownController.v +++ b/CountdownController.v @@ -50,9 +50,14 @@ wire [3:0] ado, bdo, cdo; wire [7:0] init; wire [7:0] tout; -ClockDivider dbc(.count(1_000_000), .rst(rst), .clk_in(clk), .clk_out(dbclk)); -ClockDivider sec(.count(100_000_000), .rst(rst), .clk_in(clk), .clk_out(seconds)); -ClockDivider dcc(.count(7_500_000), .rst(rst), .clk_in(clk), .clk_out(dispclk)); +//ClockDivider dbc(.count(1_000_000), .rst(rst), .clk_in(clk), .clk_out(dbclk)); +//ClockDivider sec(.count(100_000_000), .rst(rst), .clk_in(clk), .clk_out(seconds)); +//ClockDivider dcc(.count(7_500_000), .rst(rst), .clk_in(clk), .clk_out(dispclk)); + +ClockDivider dbc(.count(10), .rst(rst), .clk_in(clk), .clk_out(dbclk)); +ClockDivider sec(.count(100), .rst(rst), .clk_in(clk), .clk_out(seconds)); +ClockDivider dcc(.count(25), .rst(rst), .clk_in(clk), .clk_out(dispclk)); + debouncer dbA(.dout(a), .din(btnA), .rst(rst), .clk_1M(dbclk)); debouncer dbB(.dout(b), .din(btnB), .rst(rst), .clk_1M(dbclk)); @@ -72,8 +77,7 @@ Bin2BCD b2bcb(.hun(cdo), .ten(ado), .one(bdo), .bin(tout)); DisplayController dispcont(.result(ssdo), .AN(ANo), .A(ado), .B(bdo), .clk_in(dispclk), .rst(rst)); -always @(posedge clk) begin - ssd <= ssdo; - AN <= ANo; -end +assign ssd = ssdo; +assign AN = ANo; + endmodule |