Initial Commit

1 files changed, 48 insertions, 0 deletions

diff --git a/DisplayController.v b/DisplayController.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:03:47 03/16/2012 
+// Design Name: 
+// Module Name:    DisplayController 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module DisplayController(
+    input [3:0] A,
+    input [3:0] B,
+	 input clk_in,
+	 input rst,
+    output [6:0] result,
+    output [3:0] AN
+    );
+	 
+reg [3:0] AN;
+reg [6:0] result = 0;
+
+wire [6:0] ssd1;
+wire [6:0] ssd2;
+
+reg prev = 0;
+
+SevSegDisp d1(.A(A), .out(ssd1));
+SevSegDisp d2(.A(B), .out(ssd2));
+
+always @( posedge clk_in ) begin
+	prev <= ~prev;
+	result <= prev ? ssd1 : ssd2;
+	AN <= { 2'b11, prev, ~prev };
+end
+
+
+endmodule