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diff --git a/TEST_BCD2Bin.v b/TEST_BCD2Bin.v
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+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   14:42:39 03/16/2012
+// Design Name:   BCD2Bin
+// Module Name:   /home/michael/Documents/School/EC311/lab4/TEST_BCD2Bin.v
+// Project Name:  lab4
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: BCD2Bin
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module TEST_BCD2Bin;
+
+	// Inputs
+	reg [3:0] hun;
+	reg [3:0] ten;
+	reg [3:0] one;
+	wire [7:0] bin;
+
+	// Instantiate the Unit Under Test (UUT)
+	BCD2Bin uut (
+		.hun(hun), 
+		.ten(ten), 
+		.one(one), 
+		.bin(bin)
+	);
+
+	initial begin
+		// Initialize Inputs
+		hun = 0;
+		ten = 0;
+		one = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+		
+		one = 5; ten = 2; hun = 1; #10;
+		one = 4; ten = 7; hun = 1; #10;
+		one = 8; ten = 2; hun = 0; #10;
+		one = 3; ten = 1; hun = 0; #10;
+		one = 2; ten = 0; hun = 0; #10;
+        
+		// Add stimulus here
+
+	end
+      
+endmodule
+