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+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   14:57:17 03/16/2012
+// Design Name:   Countdown
+// Module Name:   /home/michael/Documents/School/EC311/lab4/TEST_Countdown.v
+// Project Name:  lab4
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: Countdown
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module TEST_Countdown;
+
+	// Inputs
+	reg clk_1hz;
+	reg rst;
+	reg start;
+	reg [7:0] init;
+
+	// Outputs
+	wire [7:0] t;
+
+	reg [7:0] i=0;
+	// Instantiate the Unit Under Test (UUT)
+	Countdown uut (
+		.clk_1hz(clk_1hz), 
+		.rst(rst), 
+		.start(start), 
+		.init(init), 
+		.t(t)
+	);
+
+	initial begin
+		// Initialize Inputs
+		clk_1hz = 0;
+		rst = 0;
+		start = 0;
+		init = 0;
+
+		// Wait 50 ns for global reset to finish
+		#50;
+        
+		// Add stimulus here
+		
+		init = 218; #50;		
+		
+		for (i = 0; i < 255; i = i + 1) begin
+			#5; clk_1hz = ~clk_1hz;
+			if (i == 10) begin
+				start = 1; #5; clk_1hz = ~clk_1hz; start = 0;
+			end
+		end
+		
+	end
+      
+endmodule
+