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author | Michael Abed <michaelabed@gmail.com> | 2012-03-21 13:17:47 -0400 |
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committer | Michael Abed <michaelabed@gmail.com> | 2012-03-21 13:17:47 -0400 |
commit | 2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4 (patch) | |
tree | 9819721233275cee6e39483867818a54299a4fc1 /TEST_SevSegDisp.v | |
download | ec311-lab4-2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4.tar.gz ec311-lab4-2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4.tar.bz2 ec311-lab4-2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4.zip |
Initial Commit
Diffstat (limited to 'TEST_SevSegDisp.v')
-rw-r--r-- | TEST_SevSegDisp.v | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/TEST_SevSegDisp.v b/TEST_SevSegDisp.v new file mode 100644 index 0000000..a818547 --- /dev/null +++ b/TEST_SevSegDisp.v @@ -0,0 +1,55 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:48:24 03/16/2012 +// Design Name: SevSegDisp +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_SevSegDisp.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: SevSegDisp +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_SevSegDisp; + + // Inputs + reg [3:0] A; + + // Outputs + wire [6:0] out; + + // Instantiate the Unit Under Test (UUT) + SevSegDisp uut ( + .A(A), + .out(out) + ); + reg [3:0] i = 0; + initial begin + // Initialize Inputs + A = 0; + + // Wait 100 ns for global reset to finish + #100; + + // Add stimulus here + + for (i = 0; i < 10; i = i + 1) begin + A = A + 1; #50; + end + + end + +endmodule + |