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| author | Michael Abed <michaelabed@gmail.com> | 2012-03-22 16:14:11 -0400 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-03-22 16:14:11 -0400 |
| commit | 11a0ed5a6e8af2e224caf1cb782829dfd8737b5e (patch) | |
| tree | 5c7aa13704d69357887328db7c4926be76858c72 /_xmsgs/pn_parser.xmsgs | |
| parent | bab97470acd4dd09ef19b669ff6c6f933aece0f8 (diff) | |
| download | ec311-lab4-11a0ed5a6e8af2e224caf1cb782829dfd8737b5e.tar.gz ec311-lab4-11a0ed5a6e8af2e224caf1cb782829dfd8737b5e.tar.bz2 ec311-lab4-11a0ed5a6e8af2e224caf1cb782829dfd8737b5e.zip | |
updates
Diffstat (limited to '_xmsgs/pn_parser.xmsgs')
| -rw-r--r-- | _xmsgs/pn_parser.xmsgs | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs index d1c52e5..446c254 100644 --- a/_xmsgs/pn_parser.xmsgs +++ b/_xmsgs/pn_parser.xmsgs @@ -1,15 +1,15 @@ -<?xml version="1.0" encoding="UTF-8"?> -<!-- IMPORTANT: This is an internal file that has been generated --> -<!-- by the Xilinx ISE software. Any direct editing or --> -<!-- changes made to this file may result in unpredictable --> -<!-- behavior or data corruption. It is strongly advised that --> -<!-- users do not edit the contents of this file. --> -<!-- --> -<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> - -<messages> -<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Test_ContdownController.v" into library work</arg> -</msg> - -</messages> - +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated -->
+<!-- by the Xilinx ISE software. Any direct editing or -->
+<!-- changes made to this file may result in unpredictable -->
+<!-- behavior or data corruption. It is strongly advised that -->
+<!-- users do not edit the contents of this file. -->
+<!-- -->
+<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1835" ><arg fmt="%s" index="1">Analyzing Verilog file "X:/My Documents/ec311/ec311-lab4/Countdown.v" into library work</arg>
+</msg>
+
+</messages>
+
|