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| author | Michael Abed <michaelabed@gmail.com> | 2012-03-21 13:17:47 -0400 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-03-21 13:17:47 -0400 |
| commit | 2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4 (patch) | |
| tree | 9819721233275cee6e39483867818a54299a4fc1 /fuse.log | |
| download | ec311-lab4-2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4.tar.gz ec311-lab4-2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4.tar.bz2 ec311-lab4-2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4.zip | |
Initial Commit
Diffstat (limited to 'fuse.log')
| -rw-r--r-- | fuse.log | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/fuse.log b/fuse.log new file mode 100644 index 0000000..d9cd2af --- /dev/null +++ b/fuse.log @@ -0,0 +1,52 @@ +Running: /home/michael/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o /home/michael/Documents/School/EC311/lab4/Test_ContdownController_isim_beh.exe -prj /home/michael/Documents/School/EC311/lab4/Test_ContdownController_beh.prj work.Test_ContdownController work.glbl +ISim O.87xd (signature 0x8ddf5b5d) +Number of CPUs detected in this system: 2 +Turning on mult-threading, number of parallel sub-compilation jobs: 4 +Determining compilation order of HDL files +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/SevSegDisp.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/SevSegDisp.v" Line 27: Redeclaration of ansi port out is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Increment.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/Increment.v" Line 26: Redeclaration of ansi port value is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/DisplayController.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 30: Redeclaration of ansi port AN is not allowed +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 31: Redeclaration of ansi port result is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/debouncer.v" into library work +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Countdown.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/Countdown.v" Line 29: Redeclaration of ansi port t is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/ClockDivider.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/ClockDivider.v" Line 28: Redeclaration of ansi port clk_out is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Bin2BCD.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/Bin2BCD.v" Line 28: Redeclaration of ansi port one is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/BCD2Bin.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/BCD2Bin.v" Line 28: Redeclaration of ansi port bin is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/CountdownController.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 31: Redeclaration of ansi port ssd is not allowed +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 32: Redeclaration of ansi port AN is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Test_ContdownController.v" into library work +Analyzing Verilog file "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" into library work +Starting static elaboration +WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 54: Size mismatch in connection of port <count>. Formal port size is 24-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 55: Size mismatch in connection of port <count>. Formal port size is 24-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 53: Size mismatch in connection of port <count>. Formal port size is 24-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 66: Size mismatch in connection of port <hun>. Formal port size is 4-bit while actual signal size is 32-bit. +Completed static elaboration +Fuse Memory Usage: 95008 KB +Fuse CPU Usage: 1560 ms +Compiling module ClockDivider +Compiling module debouncer +Compiling module Increment +Compiling module BCD2Bin +Compiling module Countdown +Compiling module Bin2BCD +Compiling module SevSegDisp +Compiling module DisplayController +Compiling module CountdownController +Compiling module Test_ContdownController +Compiling module glbl +Time Resolution for simulation is 1ps. +Waiting for 8 sub-compilation(s) to finish... +Compiled 11 Verilog Units +Built simulation executable /home/michael/Documents/School/EC311/lab4/Test_ContdownController_isim_beh.exe +Fuse Memory Usage: 393132 KB +Fuse CPU Usage: 1610 ms +GCC CPU Usage: 1250 ms |