diff options
| author | Michael Abed <michaelabed@gmail.com> | 2012-03-21 13:17:47 -0400 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-03-21 13:17:47 -0400 |
| commit | 2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4 (patch) | |
| tree | 9819721233275cee6e39483867818a54299a4fc1 /iseconfig | |
| download | ec311-lab4-2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4.tar.gz ec311-lab4-2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4.tar.bz2 ec311-lab4-2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4.zip | |
Initial Commit
Diffstat (limited to 'iseconfig')
| -rw-r--r-- | iseconfig/Bin2BCD.xreport | 215 | ||||
| -rw-r--r-- | iseconfig/CountdownController.xreport | 215 | ||||
| -rw-r--r-- | iseconfig/DisplayController.xreport | 215 | ||||
| -rw-r--r-- | iseconfig/lab4.projectmgr | 213 |
4 files changed, 858 insertions, 0 deletions
diff --git a/iseconfig/Bin2BCD.xreport b/iseconfig/Bin2BCD.xreport new file mode 100644 index 0000000..606b2bb --- /dev/null +++ b/iseconfig/Bin2BCD.xreport @@ -0,0 +1,215 @@ +<?xml version='1.0' encoding='UTF-8'?> +<report-views version="2.0" > + <header> + <DateModified>2012-03-16T10:16:13</DateModified> + <ModuleName>Bin2BCD</ModuleName> + <SummaryTimeStamp>Unknown</SummaryTimeStamp> + <SavedFilePath>/home/michael/Documents/School/EC311/lab4/iseconfig/Bin2BCD.xreport</SavedFilePath> + <ImplementationReportsDirectory>/home/michael/Documents/School/EC311/lab4</ImplementationReportsDirectory> + <DateInitialized>2012-03-16T10:16:12</DateInitialized> + <EnableMessageFiltering>false</EnableMessageFiltering> + </header> + <body> + <viewgroup label="Design Overview" > + <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="Bin2BCD_summary.html" label="Summary" > + <toc-item title="Design Overview" target="Design Overview" /> + <toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> + <toc-item title="Performance Summary" target="Performance Summary" /> + <toc-item title="Failing Constraints" target="Failing Constraints" /> + <toc-item title="Detailed Reports" target="Detailed Reports" /> + </view> + <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="Bin2BCD_envsettings.html" label="System Settings" /> + <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="Bin2BCD_map.xrpt" label="IOB Properties" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="Bin2BCD_map.xrpt" label="Control Set Information" /> + <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="Bin2BCD_map.xrpt" label="Module Level Utilization" /> + <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="Bin2BCD.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" /> + <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="Bin2BCD_par.xrpt" label="Pinout Report" /> + <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="Bin2BCD_par.xrpt" label="Clock Report" /> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="Bin2BCD.twx" label="Static Timing" /> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="Bin2BCD_html/fit/report.htm" label="CPLD Fitter Report" /> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="Bin2BCD_html/tim/report.htm" label="CPLD Timing Report" /> + </viewgroup> + <viewgroup label="XPS Errors and Warnings" > + <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> + <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> + <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> + </viewgroup> + <viewgroup label="XPS Reports" > + <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" /> + <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> + <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> + <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="Bin2BCD.log" label="System Log File" /> + </viewgroup> + <viewgroup label="Errors and Warnings" > + <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> + <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" /> + <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" /> + <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" /> + <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" /> + <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" /> + <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" /> + <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" /> + <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" /> + <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" /> + <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" /> + </viewgroup> + <viewgroup label="Detailed Reports" > + <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="Bin2BCD.syr" label="Synthesis Report" > + <toc-item title="Top of Report" target="Copyright " searchDir="Forward" /> + <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> + <toc-item title="HDL Compilation" target=" HDL Compilation " /> + <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> + <toc-item title="HDL Analysis" target=" HDL Analysis " /> + <toc-item title="HDL Parsing" target=" HDL Parsing " /> + <toc-item title="HDL Elaboration" target=" HDL Elaboration " /> + <toc-item title="HDL Synthesis" target=" HDL Synthesis " /> + <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" /> + <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" /> + <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" /> + <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " /> + <toc-item title="Partition Report" target=" Partition Report " /> + <toc-item title="Final Report" target=" Final Report " /> + <toc-item title="Design Summary" target=" Design Summary " /> + <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" /> + <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" /> + <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" /> + <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" /> + <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" /> + <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" /> + <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" /> + <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" /> + <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" /> + </view> + <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="Bin2BCD.srr" label="Synplify Report" /> + <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="Bin2BCD.prec_log" label="Precision Report" /> + <view inputState="Synthesized" program="ngdbuild" type="Report" file="Bin2BCD.bld" label="Translation Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Command Line" target="Command Line:" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> + </view> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="Bin2BCD_map.mrp" label="Map Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> + <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" /> + <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" /> + <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" /> + <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" /> + <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" /> + <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" /> + <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" /> + <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" /> + <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" /> + <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" /> + <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" /> + <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="Bin2BCD.par" label="Place and Route Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Device Utilization" target="Device Utilization Summary:" /> + <toc-item title="Router Information" target="Starting Router" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Clock Report" target="Generating Clock Report" /> + <toc-item title="Timing Results" target="Timing Score:" /> + <toc-item title="Final Summary" target="Peak Memory Usage:" /> + </view> + <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="Bin2BCD.twr" label="Post-PAR Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="Bin2BCD.rpt" label="CPLD Fitter Report (Text)" > + <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" /> + <toc-item title="Resources Summary" target="** Mapped Resource Summary **" /> + <toc-item title="Pin Resources" target="** Pin Resources **" /> + <toc-item title="Global Resources" target="** Global Control Resources **" /> + </view> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="Bin2BCD.tim" label="CPLD Timing Report (Text)" > + <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> + <toc-item title="Performance Summary" target="Performance Summary:" /> + </view> + <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="Bin2BCD.pwr" label="Power Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Power summary" target="Power summary" /> + <toc-item title="Thermal summary" target="Thermal summary" /> + </view> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="Bin2BCD.bgn" label="Bitgen Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> + <toc-item title="Final Summary" target="DRC detected" /> + </view> + </viewgroup> + <viewgroup label="Secondary Reports" > + <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> + <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/Bin2BCD_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/Bin2BCD_translate.nlf" label="Post-Translate Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="Bin2BCD_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="Bin2BCD_map.map" label="Map Log File" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Design Information" target="Design Information" /> + <toc-item title="Design Summary" target="Design Summary" /> + </view> + <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" /> + <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD_preroute.twr" label="Post-Map Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/Bin2BCD_map.nlf" label="Post-Map Simulation Model Report" /> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD_map.psr" label="Physical Synthesis Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="Bin2BCD_pad.txt" label="Pad Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="Bin2BCD.unroutes" label="Unroutes Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD_preroute.tsi" label="Post-Map Constraints Interaction Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD.grf" label="Guide Results Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD.dly" label="Asynchronous Delay Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD.clk_rgn" label="Clock Region Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD.tsi" label="Post-Place and Route Constraints Interaction Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="Bin2BCD_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" /> + <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/Bin2BCD_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="Bin2BCD_sta.nlf" label="Primetime Netlist Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="Bin2BCD.ibs" label="IBIS Model" > + <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" /> + <toc-item title="Component" target="Component " /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD.lck" label="Back-annotate Pin Report" > + <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" /> + <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Bin2BCD.lpc" label="Locked Pin Constraints" > + <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" /> + <toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> + </view> + <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/Bin2BCD_timesim.nlf" label="Post-Fit Simulation Model Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" /> + </viewgroup> + </body> +</report-views> diff --git a/iseconfig/CountdownController.xreport b/iseconfig/CountdownController.xreport new file mode 100644 index 0000000..81912a7 --- /dev/null +++ b/iseconfig/CountdownController.xreport @@ -0,0 +1,215 @@ +<?xml version='1.0' encoding='UTF-8'?> +<report-views version="2.0" > + <header> + <DateModified>2012-03-21T11:25:15</DateModified> + <ModuleName>CountdownController</ModuleName> + <SummaryTimeStamp>Unknown</SummaryTimeStamp> + <SavedFilePath>/home/michael/Documents/School/EC311/lab4/iseconfig/CountdownController.xreport</SavedFilePath> + <ImplementationReportsDirectory>/home/michael/Documents/School/EC311/lab4/</ImplementationReportsDirectory> + <DateInitialized>2012-03-17T11:17:09</DateInitialized> + <EnableMessageFiltering>false</EnableMessageFiltering> + </header> + <body> + <viewgroup label="Design Overview" > + <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="CountdownController_summary.html" label="Summary" > + <toc-item title="Design Overview" target="Design Overview" /> + <toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> + <toc-item title="Performance Summary" target="Performance Summary" /> + <toc-item title="Failing Constraints" target="Failing Constraints" /> + <toc-item title="Detailed Reports" target="Detailed Reports" /> + </view> + <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="CountdownController_envsettings.html" label="System Settings" /> + <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="CountdownController_map.xrpt" label="IOB Properties" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="CountdownController_map.xrpt" label="Control Set Information" /> + <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="CountdownController_map.xrpt" label="Module Level Utilization" /> + <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="CountdownController.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" /> + <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="CountdownController_par.xrpt" label="Pinout Report" /> + <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="CountdownController_par.xrpt" label="Clock Report" /> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="CountdownController.twx" label="Static Timing" /> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="CountdownController_html/fit/report.htm" label="CPLD Fitter Report" /> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="CountdownController_html/tim/report.htm" label="CPLD Timing Report" /> + </viewgroup> + <viewgroup label="XPS Errors and Warnings" > + <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> + <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> + <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> + </viewgroup> + <viewgroup label="XPS Reports" > + <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" /> + <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> + <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> + <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="CountdownController.log" label="System Log File" /> + </viewgroup> + <viewgroup label="Errors and Warnings" > + <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> + <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" /> + <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" /> + <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" /> + <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" /> + <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" /> + <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" /> + <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" /> + <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" /> + <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" /> + <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" /> + </viewgroup> + <viewgroup label="Detailed Reports" > + <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="CountdownController.syr" label="Synthesis Report" > + <toc-item title="Top of Report" target="Copyright " searchDir="Forward" /> + <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> + <toc-item title="HDL Compilation" target=" HDL Compilation " /> + <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> + <toc-item title="HDL Analysis" target=" HDL Analysis " /> + <toc-item title="HDL Parsing" target=" HDL Parsing " /> + <toc-item title="HDL Elaboration" target=" HDL Elaboration " /> + <toc-item title="HDL Synthesis" target=" HDL Synthesis " /> + <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" /> + <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" /> + <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" /> + <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " /> + <toc-item title="Partition Report" target=" Partition Report " /> + <toc-item title="Final Report" target=" Final Report " /> + <toc-item title="Design Summary" target=" Design Summary " /> + <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" /> + <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" /> + <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" /> + <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" /> + <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" /> + <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" /> + <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" /> + <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" /> + <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" /> + </view> + <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="CountdownController.srr" label="Synplify Report" /> + <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="CountdownController.prec_log" label="Precision Report" /> + <view inputState="Synthesized" program="ngdbuild" type="Report" file="CountdownController.bld" label="Translation Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Command Line" target="Command Line:" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> + </view> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="CountdownController_map.mrp" label="Map Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> + <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" /> + <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" /> + <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" /> + <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" /> + <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" /> + <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" /> + <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" /> + <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" /> + <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" /> + <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" /> + <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" /> + <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="CountdownController.par" label="Place and Route Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Device Utilization" target="Device Utilization Summary:" /> + <toc-item title="Router Information" target="Starting Router" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Clock Report" target="Generating Clock Report" /> + <toc-item title="Timing Results" target="Timing Score:" /> + <toc-item title="Final Summary" target="Peak Memory Usage:" /> + </view> + <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="CountdownController.twr" label="Post-PAR Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="CountdownController.rpt" label="CPLD Fitter Report (Text)" > + <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" /> + <toc-item title="Resources Summary" target="** Mapped Resource Summary **" /> + <toc-item title="Pin Resources" target="** Pin Resources **" /> + <toc-item title="Global Resources" target="** Global Control Resources **" /> + </view> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="CountdownController.tim" label="CPLD Timing Report (Text)" > + <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> + <toc-item title="Performance Summary" target="Performance Summary:" /> + </view> + <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="CountdownController.pwr" label="Power Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Power summary" target="Power summary" /> + <toc-item title="Thermal summary" target="Thermal summary" /> + </view> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="CountdownController.bgn" label="Bitgen Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> + <toc-item title="Final Summary" target="DRC detected" /> + </view> + </viewgroup> + <viewgroup label="Secondary Reports" > + <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> + <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/CountdownController_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/CountdownController_translate.nlf" label="Post-Translate Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="CountdownController_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="CountdownController_map.map" label="Map Log File" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Design Information" target="Design Information" /> + <toc-item title="Design Summary" target="Design Summary" /> + </view> + <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" /> + <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController_preroute.twr" label="Post-Map Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/CountdownController_map.nlf" label="Post-Map Simulation Model Report" /> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController_map.psr" label="Physical Synthesis Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="CountdownController_pad.txt" label="Pad Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="CountdownController.unroutes" label="Unroutes Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController_preroute.tsi" label="Post-Map Constraints Interaction Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.grf" label="Guide Results Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.dly" label="Asynchronous Delay Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.clk_rgn" label="Clock Region Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.tsi" label="Post-Place and Route Constraints Interaction Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="CountdownController_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" /> + <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/CountdownController_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="CountdownController_sta.nlf" label="Primetime Netlist Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="CountdownController.ibs" label="IBIS Model" > + <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" /> + <toc-item title="Component" target="Component " /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.lck" label="Back-annotate Pin Report" > + <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" /> + <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.lpc" label="Locked Pin Constraints" > + <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" /> + <toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> + </view> + <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/CountdownController_timesim.nlf" label="Post-Fit Simulation Model Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" /> + </viewgroup> + </body> +</report-views> diff --git a/iseconfig/DisplayController.xreport b/iseconfig/DisplayController.xreport new file mode 100644 index 0000000..f40a6a4 --- /dev/null +++ b/iseconfig/DisplayController.xreport @@ -0,0 +1,215 @@ +<?xml version='1.0' encoding='UTF-8'?> +<report-views version="2.0" > + <header> + <DateModified>2012-03-16T17:38:52</DateModified> + <ModuleName>CountdownController</ModuleName> + <SummaryTimeStamp>Unknown</SummaryTimeStamp> + <SavedFilePath>/home/michael/Documents/School/EC311/lab4/iseconfig/DisplayController.xreport</SavedFilePath> + <ImplementationReportsDirectory>/home/michael/Documents/School/EC311/lab4</ImplementationReportsDirectory> + <DateInitialized>2012-03-16T17:38:51</DateInitialized> + <EnableMessageFiltering>false</EnableMessageFiltering> + </header> + <body> + <viewgroup label="Design Overview" > + <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="CountdownController_summary.html" label="Summary" > + <toc-item title="Design Overview" target="Design Overview" /> + <toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> + <toc-item title="Performance Summary" target="Performance Summary" /> + <toc-item title="Failing Constraints" target="Failing Constraints" /> + <toc-item title="Detailed Reports" target="Detailed Reports" /> + </view> + <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="CountdownController_envsettings.html" label="System Settings" /> + <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="CountdownController_map.xrpt" label="IOB Properties" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="CountdownController_map.xrpt" label="Control Set Information" /> + <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="CountdownController_map.xrpt" label="Module Level Utilization" /> + <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="CountdownController.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" /> + <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="CountdownController_par.xrpt" label="Pinout Report" /> + <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="CountdownController_par.xrpt" label="Clock Report" /> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="CountdownController.twx" label="Static Timing" /> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="CountdownController_html/fit/report.htm" label="CPLD Fitter Report" /> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="CountdownController_html/tim/report.htm" label="CPLD Timing Report" /> + </viewgroup> + <viewgroup label="XPS Errors and Warnings" > + <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> + <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> + <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> + </viewgroup> + <viewgroup label="XPS Reports" > + <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" /> + <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> + <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> + <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="CountdownController.log" label="System Log File" /> + </viewgroup> + <viewgroup label="Errors and Warnings" > + <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> + <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" /> + <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" /> + <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" /> + <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" /> + <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" /> + <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" /> + <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" /> + <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" /> + <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" /> + <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" /> + </viewgroup> + <viewgroup label="Detailed Reports" > + <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="CountdownController.syr" label="Synthesis Report" > + <toc-item title="Top of Report" target="Copyright " searchDir="Forward" /> + <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> + <toc-item title="HDL Compilation" target=" HDL Compilation " /> + <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> + <toc-item title="HDL Analysis" target=" HDL Analysis " /> + <toc-item title="HDL Parsing" target=" HDL Parsing " /> + <toc-item title="HDL Elaboration" target=" HDL Elaboration " /> + <toc-item title="HDL Synthesis" target=" HDL Synthesis " /> + <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" /> + <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" /> + <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" /> + <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " /> + <toc-item title="Partition Report" target=" Partition Report " /> + <toc-item title="Final Report" target=" Final Report " /> + <toc-item title="Design Summary" target=" Design Summary " /> + <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" /> + <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" /> + <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" /> + <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" /> + <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" /> + <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" /> + <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" /> + <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" /> + <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" /> + </view> + <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="CountdownController.srr" label="Synplify Report" /> + <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="CountdownController.prec_log" label="Precision Report" /> + <view inputState="Synthesized" program="ngdbuild" type="Report" file="CountdownController.bld" label="Translation Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Command Line" target="Command Line:" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> + </view> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="CountdownController_map.mrp" label="Map Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> + <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" /> + <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" /> + <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" /> + <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" /> + <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" /> + <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" /> + <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" /> + <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" /> + <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" /> + <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" /> + <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" /> + <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="CountdownController.par" label="Place and Route Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Device Utilization" target="Device Utilization Summary:" /> + <toc-item title="Router Information" target="Starting Router" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Clock Report" target="Generating Clock Report" /> + <toc-item title="Timing Results" target="Timing Score:" /> + <toc-item title="Final Summary" target="Peak Memory Usage:" /> + </view> + <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="CountdownController.twr" label="Post-PAR Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="CountdownController.rpt" label="CPLD Fitter Report (Text)" > + <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" /> + <toc-item title="Resources Summary" target="** Mapped Resource Summary **" /> + <toc-item title="Pin Resources" target="** Pin Resources **" /> + <toc-item title="Global Resources" target="** Global Control Resources **" /> + </view> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="CountdownController.tim" label="CPLD Timing Report (Text)" > + <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> + <toc-item title="Performance Summary" target="Performance Summary:" /> + </view> + <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="CountdownController.pwr" label="Power Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Power summary" target="Power summary" /> + <toc-item title="Thermal summary" target="Thermal summary" /> + </view> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="CountdownController.bgn" label="Bitgen Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> + <toc-item title="Final Summary" target="DRC detected" /> + </view> + </viewgroup> + <viewgroup label="Secondary Reports" > + <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> + <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/CountdownController_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/CountdownController_translate.nlf" label="Post-Translate Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="CountdownController_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="CountdownController_map.map" label="Map Log File" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Design Information" target="Design Information" /> + <toc-item title="Design Summary" target="Design Summary" /> + </view> + <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" /> + <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController_preroute.twr" label="Post-Map Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/CountdownController_map.nlf" label="Post-Map Simulation Model Report" /> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController_map.psr" label="Physical Synthesis Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="CountdownController_pad.txt" label="Pad Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="CountdownController.unroutes" label="Unroutes Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController_preroute.tsi" label="Post-Map Constraints Interaction Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.grf" label="Guide Results Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.dly" label="Asynchronous Delay Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.clk_rgn" label="Clock Region Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.tsi" label="Post-Place and Route Constraints Interaction Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="CountdownController_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" /> + <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/CountdownController_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="CountdownController_sta.nlf" label="Primetime Netlist Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="CountdownController.ibs" label="IBIS Model" > + <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" /> + <toc-item title="Component" target="Component " /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.lck" label="Back-annotate Pin Report" > + <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" /> + <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="CountdownController.lpc" label="Locked Pin Constraints" > + <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" /> + <toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> + </view> + <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/CountdownController_timesim.nlf" label="Post-Fit Simulation Model Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" /> + </viewgroup> + </body> +</report-views> diff --git a/iseconfig/lab4.projectmgr b/iseconfig/lab4.projectmgr new file mode 100644 index 0000000..a85babe --- /dev/null +++ b/iseconfig/lab4.projectmgr @@ -0,0 +1,213 @@ +<?xml version='1.0' encoding='utf-8'?> +<!--This is an ISE project configuration file.--> +<!--It holds project specific layout data for the projectmgr plugin.--> +<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.--> +<Project version="2" owner="projectmgr" name="lab4" > + <!--This is an ISE project configuration file.--> + <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + <ClosedNode>/CountdownController |home|michael|Documents|School|EC311|lab4|CountdownController.v/DisplayController - DisplayController</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>cntdwn - Countdown (/home/michael/Documents/School/EC311/lab4/Countdown.v)</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000017a000000020000000000000000000000000200000064ffffffff0000008100000003000000020000017a0000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> + <CurrentItem>cntdwn - Countdown (/home/michael/Documents/School/EC311/lab4/Countdown.v)</CurrentItem> + </ItemView> + <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Design Utilities</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem/> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem/> + </ItemView> + <ItemView guiview="File" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem>debouncer.v</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000287000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004a0000000100000000000000640000000100000000000000790000000100000000000001600000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>debouncer.v</CurrentItem> + </ItemView> + <ItemView guiview="Library" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>work</ClosedNode> + </ClosedNodes> + <SelectedItems/> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000117000000010001000100000000000000000000000064ffffffff000000810000000000000001000001170000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>work</CurrentItem> + </ItemView> + <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Configure Target Device</ClosedNode> + <ClosedNode>Implement Design/Map</ClosedNode> + <ClosedNode>Implement Design/Place & Route/Back-annotate Pin Locations</ClosedNode> + <ClosedNode>Implement Design/Place & Route/Generate IBIS Model</ClosedNode> + <ClosedNode>Implement Design/Place & Route/Generate Post-Place & Route Static Timing</ClosedNode> + <ClosedNode>Implement Design/Translate</ClosedNode> + <ClosedNode>User Constraints</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem></SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem></CurrentItem> + </ItemView> + <ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + <ClosedNode>/CountdownController |home|michael|Documents|School|EC311|lab4|CountdownController.v/DisplayController - DisplayController</ClosedNode> + <ClosedNode>/DisplayController |home|michael|Documents|School|EC311|lab4|DisplayController.v</ClosedNode> + <ClosedNode>/TEST_BCD2Bin |home|michael|Documents|School|EC311|lab4|TEST_BCD2Bin.v</ClosedNode> + <ClosedNode>/TEST_Bin2BCD |home|michael|Documents|School|EC311|lab4|TEST_Bin2BCD.v</ClosedNode> + <ClosedNode>/TEST_ClockDivider |home|michael|Documents|School|EC311|lab4|TEST_ClockDivider.v</ClosedNode> + <ClosedNode>/TEST_Countdown |home|michael|Documents|School|EC311|lab4|TEST_Countdown.v</ClosedNode> + <ClosedNode>/TEST_DisplayController |home|michael|Documents|School|EC311|lab4|TEST_DisplayController.v</ClosedNode> + <ClosedNode>/TEST_DisplayController |home|michael|Documents|School|EC311|lab4|TEST_DisplayController.v/uut - DisplayController</ClosedNode> + <ClosedNode>/TEST_Increment |home|michael|Documents|School|EC311|lab4|TEST_Increment.v</ClosedNode> + <ClosedNode>/TEST_SevSegDisp |home|michael|Documents|School|EC311|lab4|TEST_SevSegDisp.v</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Test_ContdownController (/home/michael/Documents/School/EC311/lab4/Test_ContdownController.v)</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >3</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000018f000000020000000000000000000000000200000064ffffffff0000008100000003000000020000018f0000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> + <CurrentItem>Test_ContdownController (/home/michael/Documents/School/EC311/lab4/Test_ContdownController.v)</CurrentItem> + </ItemView> + <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem/> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem/> + </ItemView> + <ItemView engineview="BehavioralSim" sourcetype="DESUT_VERILOG" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem></SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem></CurrentItem> + </ItemView> + <ItemView engineview="PostTransSim" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + <ClosedNode>/TEST_Bin2BCD |home|michael|Documents|School|EC311|lab4|TEST_Bin2BCD.v</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Unassigned User Library Modules</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000010d0000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Unassigned User Library Modules</CurrentItem> + </ItemView> + <ItemView engineview="PostTransSim" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Compile HDL Simulation Libraries</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Compile HDL Simulation Libraries</CurrentItem> + </ItemView> + <ItemView engineview="PostMapSim" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + <ClosedNode>/TEST_Bin2BCD |home|michael|Documents|School|EC311|lab4|TEST_Bin2BCD.v</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Unassigned User Library Modules</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000010d0000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Unassigned User Library Modules</CurrentItem> + </ItemView> + <ItemView engineview="PostMapSim" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Compile HDL Simulation Libraries</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Compile HDL Simulation Libraries</CurrentItem> + </ItemView> + <ItemView engineview="PostRouteSim" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + <ClosedNode>/TEST_Bin2BCD |home|michael|Documents|School|EC311|lab4|TEST_Bin2BCD.v</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Unassigned User Library Modules</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000010d0000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Unassigned User Library Modules</CurrentItem> + </ItemView> + <ItemView engineview="PostRouteSim" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Compile HDL Simulation Libraries</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>Compile HDL Simulation Libraries</CurrentItem> + </ItemView> + <SourceProcessView>000000ff00000000000000020000010a0000009d01000000060100000002</SourceProcessView> + <CurrentView>Behavioral Simulation</CurrentView> +</Project> |