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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:01:14 03/16/2012 
+// Design Name: 
+// Module Name:    SevSegDisp 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module SevSegDisp(
+    input [3:0] A,
+    output [6:0] result
+    );
+
+reg [6:0] result = 0;
+
+always @ ( * ) begin
+  case ( A )
+    4'b0000 : result = 7'b0000001;
+    4'b0001 : result = 7'b1001111;
+    4'b0010 : result = 7'b0010010;
+    4'b0011 : result = 7'b0000110;
+    4'b0100 : result = 7'b1001100;
+    4'b0101 : result = 7'b0100100;
+    4'b0110 : result = 7'b0100000;
+    4'b0111 : result = 7'b0001111;
+    4'b1000 : result = 7'b0000000;
+    4'b1001 : result = 7'b0001100;                                               
+    default : result = 7'b0011010;
+  endcase
+end
+
+endmodule