initial commit

13 files changed, 1213 insertions, 0 deletions

diff --git a/Bin2BCD.v b/Bin2BCD.v
new file mode 100644
index 0000000..7af8725
--- /dev/null
+++ b/Bin2BCD.v
@@ -0,0 +1,57 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:16:12 03/16/2012 
+// Design Name: 
+// Module Name:    Bin2BCD 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Bin2BCD(
+    input [15:0] bin,
+    output [3:0] one,
+    output [3:0] ten,
+    output [3:0] hun,
+	 output [3:0] thous
+    );
+
+reg [3:0] one, ten, hun, thous;
+reg [31:0] work;
+reg [3:0] i;
+
+always @( bin ) begin
+	hun = 0; ten = 0; one = 0;
+	work = {thous, hun, ten, one, bin};
+
+	for (i = 0; i < 15; i = i +1) begin
+		work = work << 1;
+		if (work[31:28] >= 5)
+			work[31:28] = work[31:28] + 4'd3;
+		if (work[27:24] >= 5)
+			work[27:24] = work[27:24] + 4'd3;
+		if (work[23:20] >= 5)
+			work[23:20] = work[23:20] + 4'd3;
+		if (work[19:16] >= 5) 
+			work[19:16] = work[19:16] + 4'd3;
+	end
+	
+	work = work << 1;
+	
+	thous = work[31:28];
+	hun = work[27:24];
+	ten = work[23:20];	
+	one = work[19:16];
+end
+
+endmodule
diff --git a/ClockDivider.v b/ClockDivider.v
new file mode 100644
index 0000000..7ced5a7
--- /dev/null
+++ b/ClockDivider.v
@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:24:11 03/16/2012 
+// Design Name: 
+// Module Name:    ClockDivider 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module ClockDivider(
+    input clk_in,
+    input rst,
+	 input [23:0] count,
+    output clk_out
+    );
+	 
+reg clk_out = 0;
+reg [23:0] c = 0;
+
+always @(posedge clk_in or posedge rst) begin
+	if (rst == 1) begin
+		c = 0;
+		clk_out = 0;
+	end else if (c == count) begin
+		clk_out = ~clk_out;
+		c = 0;
+	end else begin
+		c = c + 24'd1;
+	end
+	
+	
+end
+
+
+
+endmodule
diff --git a/DisplayController.v b/DisplayController.v
new file mode 100644
index 0000000..6da8227
--- /dev/null
+++ b/DisplayController.v
@@ -0,0 +1,65 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:52:48 03/27/2012 
+// Design Name: 
+// Module Name:    DisplayController 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module DisplayController(
+    input [3:0] A,
+    input [3:0] B,
+    input [3:0] C,
+    input [3:0] D,
+	 input clk,
+	 input rst,
+    output [6:0] ssd,
+    output [3:0] AN
+    );
+	 
+	 
+reg [6:0] ssd;
+reg [3:0] AN;
+
+wire clkdiv;
+reg [1:0] w = 2'd0;
+
+ClockDivider cdiv(.clk_out(clkdiv), .rst(rst), .clk_in(clk), .count(500_000));
+
+wire [6:0] o1, o2, o3, o4;
+
+SevSegDisp d1(.result(o1), .A(A));
+SevSegDisp d2(.result(o2), .A(B));
+SevSegDisp d3(.result(o3), .A(C));
+SevSegDisp d4(.result(o4), .A(D));
+
+always @(posedge clkdiv) begin
+	w <= w + 2'd1;
+	case (w) 
+		2'b00: AN <= 4'b1110;
+		2'b01: AN <= 4'b1101;
+		2'b10: AN <= 4'b1011;
+		2'b11: AN <= 4'b0111;
+	endcase
+	case (w) 
+		2'b00: ssd <= o1;
+		2'b01: ssd <= o2;
+		2'b10: ssd <= o3;
+		2'b11: ssd <= o4;
+	endcase
+end
+
+
+endmodule
diff --git a/DisplayController_summary.html b/DisplayController_summary.html
new file mode 100644
index 0000000..e3bd536
--- /dev/null
+++ b/DisplayController_summary.html
@@ -0,0 +1,79 @@
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>FIRController Project Status</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>lab5.xise</TD>
+<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
+<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab5/_xmsgs/pn_parser.xmsgs?&DataKey=Error'>1 Error</A></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>DisplayController</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>New</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc6slx16-3csg324</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
+<TD>&nbsp;</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+
+
+
+
+
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 03/27/2012 - 16:53:37</center>
+</BODY></HTML>
\ No newline at end of file
diff --git a/FIRController.v b/FIRController.v
new file mode 100644
index 0000000..c71ea12
--- /dev/null
+++ b/FIRController.v
@@ -0,0 +1,46 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:51:34 03/27/2012 
+// Design Name: 
+// Module Name:    FIRController 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module FIRController(
+	input clk,
+	input load,
+	input rst,
+	input [7:0] yin,
+	output [6:0] ssd,
+	output [3:0] AN
+    );
+
+wire [15:0] yout;
+
+FIRFilter ff(.yin(yin), .yout(yout));
+
+wire [3:0] one, ten, hun, thous;
+
+Bin2BCD b2bcd(.bin(yout), .thous(thous), .hun(hun), .ten(ten), .one(one));
+
+wire [6:0] ssdw;
+wire [3:0] ANw;
+
+DisplayController dc(.A(thous), .B(hun), .C(ten), .D(one), .clk(clk), .rst(rst), .ssd(ssdw), .AN(ANw));
+
+assign ssd = ssdw;
+assign AN = ANw;
+
+endmodule
diff --git a/FIRController_summary.html b/FIRController_summary.html
new file mode 100644
index 0000000..4f59e04
--- /dev/null
+++ b/FIRController_summary.html
@@ -0,0 +1,79 @@
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>FIRController Project Status</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>lab5.xise</TD>
+<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
+<TD> No Errors </TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>FIRController</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>New</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc6slx16-3csg324</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
+<TD>&nbsp;</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+
+
+
+
+
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 03/27/2012 - 15:51:36</center>
+</BODY></HTML>
\ No newline at end of file
diff --git a/FIRFilter.v b/FIRFilter.v
new file mode 100644
index 0000000..dada832
--- /dev/null
+++ b/FIRFilter.v
@@ -0,0 +1,42 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:36:01 03/27/2012 
+// Design Name: 
+// Module Name:    FIRFilter 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module FIRFilter(
+    input [7:0] yin,
+    output [15:0] yout,
+    input load,
+    input rst
+    );
+
+reg [15:0] yout;
+
+reg [15:0] yold1;
+reg [15:0] yold2;
+
+always @(*) begin
+	yout = 20*yin + 15*yold1 + 10*yold2;
+end
+
+always @(load) begin
+	yold2 = yold1;
+	yold1 = yin;
+end
+
+endmodule
diff --git a/SevSegDisp.v b/SevSegDisp.v
new file mode 100644
index 0000000..8d2c3b1
--- /dev/null
+++ b/SevSegDisp.v
@@ -0,0 +1,45 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:01:14 03/16/2012 
+// Design Name: 
+// Module Name:    SevSegDisp 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module SevSegDisp(
+    input [3:0] A,
+    output [6:0] result
+    );
+
+reg [6:0] result = 0;
+
+always @ ( * ) begin
+  case ( A )
+    4'b0000 : result = 7'b0000001;
+    4'b0001 : result = 7'b1001111;
+    4'b0010 : result = 7'b0010010;
+    4'b0011 : result = 7'b0000110;
+    4'b0100 : result = 7'b1001100;
+    4'b0101 : result = 7'b0100100;
+    4'b0110 : result = 7'b0100000;
+    4'b0111 : result = 7'b0001111;
+    4'b1000 : result = 7'b0000000;
+    4'b1001 : result = 7'b0001100;                                               
+    default : result = 7'b0011010;
+  endcase
+end
+
+endmodule
diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs
new file mode 100644
index 0000000..278dafe
--- /dev/null
+++ b/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;/home/michael/Documents/School/EC311/lab5/DisplayController.v&quot; into library work</arg>
+</msg>
+
+</messages>
+
diff --git a/iseconfig/FIRController.xreport b/iseconfig/FIRController.xreport
new file mode 100644
index 0000000..80763e1
--- /dev/null
+++ b/iseconfig/FIRController.xreport
@@ -0,0 +1,215 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="2.0" >
+ <header>
+  <DateModified>2012-03-27T16:33:33</DateModified>
+  <ModuleName>DisplayController</ModuleName>
+  <SummaryTimeStamp>Unknown</SummaryTimeStamp>
+  <SavedFilePath>/home/michael/Documents/School/EC311/lab5/iseconfig/FIRController.xreport</SavedFilePath>
+  <ImplementationReportsDirectory>/home/michael/Documents/School/EC311/lab5</ImplementationReportsDirectory>
+  <DateInitialized>2012-03-27T16:33:33</DateInitialized>
+  <EnableMessageFiltering>false</EnableMessageFiltering>
+ </header>
+ <body>
+  <viewgroup label="Design Overview" >
+   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="DisplayController_summary.html" label="Summary" >
+    <toc-item title="Design Overview" target="Design Overview" />
+    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+    <toc-item title="Performance Summary" target="Performance Summary" />
+    <toc-item title="Failing Constraints" target="Failing Constraints" />
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
+   </view>
+   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="DisplayController_envsettings.html" label="System Settings" />
+   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="DisplayController_map.xrpt" label="IOB Properties" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="DisplayController_map.xrpt" label="Control Set Information" />
+   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="DisplayController_map.xrpt" label="Module Level Utilization" />
+   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="DisplayController.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="DisplayController_par.xrpt" label="Pinout Report" />
+   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="DisplayController_par.xrpt" label="Clock Report" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="DisplayController.twx" label="Static Timing" />
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="DisplayController_html/fit/report.htm" label="CPLD Fitter Report" />
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="DisplayController_html/tim/report.htm" label="CPLD Timing Report" />
+  </viewgroup>
+  <viewgroup label="XPS Errors and Warnings" >
+   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+  </viewgroup>
+  <viewgroup label="XPS Reports" >
+   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
+   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
+   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
+   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="DisplayController.log" label="System Log File" />
+  </viewgroup>
+  <viewgroup label="Errors and Warnings" >
+   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
+   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
+  </viewgroup>
+  <viewgroup label="Detailed Reports" >
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="DisplayController.syr" label="Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
+    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
+    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
+    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
+    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
+    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
+    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
+    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
+    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
+    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
+    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
+    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
+    <toc-item title="Partition Report" target="   Partition Report     " />
+    <toc-item title="Final Report" target="   Final Report   " />
+    <toc-item title="Design Summary" target="   Design Summary   " />
+    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
+    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
+    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
+    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
+    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
+    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
+    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
+    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
+    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
+   </view>
+   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="DisplayController.srr" label="Synplify Report" />
+   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="DisplayController.prec_log" label="Precision Report" />
+   <view inputState="Synthesized" program="ngdbuild" type="Report" file="DisplayController.bld" label="Translation Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Command Line" target="Command Line:" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+   </view>
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="DisplayController_map.mrp" label="Map Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
+    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
+    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
+    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
+    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
+    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
+    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
+    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
+    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
+    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
+    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
+    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
+    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="DisplayController.par" label="Place and Route Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+    <toc-item title="Router Information" target="Starting Router" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Clock Report" target="Generating Clock Report" />
+    <toc-item title="Timing Results" target="Timing Score:" />
+    <toc-item title="Final Summary" target="Peak Memory Usage:" />
+   </view>
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="DisplayController.twr" label="Post-PAR Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="DisplayController.rpt" label="CPLD Fitter Report (Text)" >
+    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
+    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
+    <toc-item title="Pin Resources" target="** Pin Resources **" />
+    <toc-item title="Global Resources" target="** Global Control Resources **" />
+   </view>
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="DisplayController.tim" label="CPLD Timing Report (Text)" >
+    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
+    <toc-item title="Performance Summary" target="Performance Summary:" />
+   </view>
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="DisplayController.pwr" label="Power Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Power summary" target="Power summary" />
+    <toc-item title="Thermal summary" target="Thermal summary" />
+   </view>
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="DisplayController.bgn" label="Bitgen Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+    <toc-item title="Final Summary" target="DRC detected" />
+   </view>
+  </viewgroup>
+  <viewgroup label="Secondary Reports" >
+   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/DisplayController_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/DisplayController_translate.nlf" label="Post-Translate Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="DisplayController_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="DisplayController_map.map" label="Map Log File" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Design Information" target="Design Information" />
+    <toc-item title="Design Summary" target="Design Summary" />
+   </view>
+   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="DisplayController_preroute.twr" label="Post-Map Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/DisplayControlle